Fix build.
There were a couple more asm lines to turn into __asm__ when the patches got reordered slightly. Change-Id: I44be5caee6d09bb3db5dea4791592b12d175822c Reviewed-on: https://boringssl-review.googlesource.com/6741 Reviewed-by: Adam Langley <agl@google.com>
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@ -146,38 +146,38 @@ extern "C" {
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/* The first macro gives a ~30-40% performance improvement in SHA-256 compiled
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* with gcc on P4. This can only be done on x86, where unaligned data fetches
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* are possible. */
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#define HOST_c2l(c, l) \
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(void)({ \
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uint32_t r = *((const uint32_t *)(c)); \
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asm("bswapl %0" : "=r"(r) : "0"(r)); \
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(c) += 4; \
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(l) = r; \
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#define HOST_c2l(c, l) \
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(void)({ \
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uint32_t r = *((const uint32_t *)(c)); \
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__asm__("bswapl %0" : "=r"(r) : "0"(r)); \
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(c) += 4; \
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(l) = r; \
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})
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#define HOST_l2c(l, c) \
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(void)({ \
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uint32_t r = (l); \
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asm("bswapl %0" : "=r"(r) : "0"(r)); \
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*((uint32_t *)(c)) = r; \
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(c) += 4; \
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r; \
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#define HOST_l2c(l, c) \
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(void)({ \
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uint32_t r = (l); \
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__asm__("bswapl %0" : "=r"(r) : "0"(r)); \
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*((uint32_t *)(c)) = r; \
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(c) += 4; \
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r; \
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})
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#elif defined(__aarch64__) && defined(__BYTE_ORDER__)
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#if defined(__ORDER_LITTLE_ENDIAN__) && \
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__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
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#define HOST_c2l(c, l) \
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(void)({ \
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uint32_t r; \
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asm("rev %w0, %w1" : "=r"(r) : "r"(*((const uint32_t *)(c)))); \
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(c) += 4; \
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(l) = r; \
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#define HOST_c2l(c, l) \
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(void)({ \
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uint32_t r; \
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__asm__("rev %w0, %w1" : "=r"(r) : "r"(*((const uint32_t *)(c)))); \
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(c) += 4; \
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(l) = r; \
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})
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#define HOST_l2c(l, c) \
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(void)({ \
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uint32_t r; \
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asm("rev %w0, %w1" : "=r"(r) : "r"((uint32_t)(l))); \
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*((uint32_t *)(c)) = r; \
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(c) += 4; \
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r; \
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#define HOST_l2c(l, c) \
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(void)({ \
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uint32_t r; \
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__asm__("rev %w0, %w1" : "=r"(r) : "r"((uint32_t)(l))); \
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*((uint32_t *)(c)) = r; \
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(c) += 4; \
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r; \
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})
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#elif defined(__ORDER_BIG_ENDIAN__) && __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
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#define HOST_c2l(c, l) (void)((l) = *((const uint32_t *)(c)), (c) += 4)
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