sha/asm/sha512-armv4.pl: adapt for use in Linux kernel context.
Follow-up to sha256-armv4.pl in cooperation with Ard Biesheuvel (Linaro) and Sami Tolvanen (Google). (Imported from upstream's b1a5d1c652086257930a1f62ae51c9cdee654b2c.) Change-Id: Ibc4f289cc8f499924ade8d6b8d494f53bc08bda7 Reviewed-on: https://boringssl-review.googlesource.com/4467 Reviewed-by: Adam Langley <agl@google.com>
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@ -5,6 +5,8 @@
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# project. The module is, however, dual licensed under OpenSSL and
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# project. The module is, however, dual licensed under OpenSSL and
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# CRYPTOGAMS licenses depending on where you obtain it. For further
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# CRYPTOGAMS licenses depending on where you obtain it. For further
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# details see http://www.openssl.org/~appro/cryptogams/.
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# details see http://www.openssl.org/~appro/cryptogams/.
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#
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# Permission to use under GPL terms is granted.
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# ====================================================================
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# ====================================================================
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# SHA512 block procedure for ARMv4. September 2007.
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# SHA512 block procedure for ARMv4. September 2007.
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@ -136,6 +138,9 @@ $code.=<<___;
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teq $t0,#$magic
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teq $t0,#$magic
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ldr $t3,[sp,#$Coff+0] @ c.lo
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ldr $t3,[sp,#$Coff+0] @ c.lo
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#if __ARM_ARCH__>=7
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it eq @ Thumb2 thing, sanity check in ARM
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#endif
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orreq $Ktbl,$Ktbl,#1
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orreq $Ktbl,$Ktbl,#1
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@ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))
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@ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))
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@ LO lo>>28^hi<<4 ^ hi>>2^lo<<30 ^ hi>>7^lo<<25
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@ LO lo>>28^hi<<4 ^ hi>>2^lo<<30 ^ hi>>7^lo<<25
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@ -173,7 +178,17 @@ $code.=<<___;
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___
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___
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}
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}
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$code=<<___;
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$code=<<___;
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#include "arm_arch.h"
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#ifndef __KERNEL__
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# include "arm_arch.h"
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# define VFP_ABI_PUSH vstmdb sp!,{d8-d15}
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# define VFP_ABI_POP vldmia sp!,{d8-d15}
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#else
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# define __ARM_ARCH__ __LINUX_ARM_ARCH__
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# define __ARM_MAX_ARCH__ 7
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# define VFP_ABI_PUSH
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# define VFP_ABI_POP
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#endif
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#ifdef __ARMEL__
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#ifdef __ARMEL__
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# define LO 0
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# define LO 0
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# define HI 4
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# define HI 4
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@ -185,7 +200,18 @@ $code=<<___;
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#endif
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#endif
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.text
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.text
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#if __ARM_ARCH__<7
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.code 32
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.code 32
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#else
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.syntax unified
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# ifdef __thumb2__
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# define adrl adr
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.thumb
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# else
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.code 32
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# endif
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#endif
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.type K512,%object
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.type K512,%object
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.align 5
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.align 5
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K512:
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K512:
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@ -230,7 +256,7 @@ WORD64(0x3c9ebe0a,0x15c9bebc, 0x431d67c4,0x9c100d4c)
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WORD64(0x4cc5d4be,0xcb3e42b6, 0x597f299c,0xfc657e2a)
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WORD64(0x4cc5d4be,0xcb3e42b6, 0x597f299c,0xfc657e2a)
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WORD64(0x5fcb6fab,0x3ad6faec, 0x6c44198c,0x4a475817)
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WORD64(0x5fcb6fab,0x3ad6faec, 0x6c44198c,0x4a475817)
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.size K512,.-K512
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.size K512,.-K512
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#if __ARM_MAX_ARCH__>=7
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#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
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.LOPENSSL_armcap:
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.LOPENSSL_armcap:
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.word OPENSSL_armcap_P-sha512_block_data_order
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.word OPENSSL_armcap_P-sha512_block_data_order
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.skip 32-4
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.skip 32-4
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@ -241,14 +267,18 @@ WORD64(0x5fcb6fab,0x3ad6faec, 0x6c44198c,0x4a475817)
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.global sha512_block_data_order
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.global sha512_block_data_order
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.type sha512_block_data_order,%function
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.type sha512_block_data_order,%function
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sha512_block_data_order:
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sha512_block_data_order:
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#if __ARM_ARCH__<7
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sub r3,pc,#8 @ sha512_block_data_order
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sub r3,pc,#8 @ sha512_block_data_order
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add $len,$inp,$len,lsl#7 @ len to point at the end of inp
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#else
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#if __ARM_MAX_ARCH__>=7
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adr r3,sha512_block_data_order
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#endif
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#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
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ldr r12,.LOPENSSL_armcap
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ldr r12,.LOPENSSL_armcap
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ldr r12,[r3,r12] @ OPENSSL_armcap_P
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ldr r12,[r3,r12] @ OPENSSL_armcap_P
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tst r12,#1
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tst r12,#1
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bne .LNEON
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bne .LNEON
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#endif
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#endif
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add $len,$inp,$len,lsl#7 @ len to point at the end of inp
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stmdb sp!,{r4-r12,lr}
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stmdb sp!,{r4-r12,lr}
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sub $Ktbl,r3,#672 @ K512
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sub $Ktbl,r3,#672 @ K512
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sub sp,sp,#9*8
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sub sp,sp,#9*8
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@ -362,6 +392,9 @@ $code.=<<___;
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___
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___
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&BODY_00_15(0x17);
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&BODY_00_15(0x17);
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$code.=<<___;
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$code.=<<___;
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#if __ARM_ARCH__>=7
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ittt eq @ Thumb2 thing, sanity check in ARM
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#endif
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ldreq $t0,[sp,#`$Xoff+8*(16-1)`+0]
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ldreq $t0,[sp,#`$Xoff+8*(16-1)`+0]
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ldreq $t1,[sp,#`$Xoff+8*(16-1)`+4]
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ldreq $t1,[sp,#`$Xoff+8*(16-1)`+4]
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beq .L16_79
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beq .L16_79
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@ -446,6 +479,7 @@ $code.=<<___;
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moveq pc,lr @ be binary compatible with V4, yet
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moveq pc,lr @ be binary compatible with V4, yet
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bx lr @ interoperable with Thumb ISA:-)
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bx lr @ interoperable with Thumb ISA:-)
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#endif
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#endif
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.size sha512_block_data_order,.-sha512_block_data_order
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___
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___
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{
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{
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@ -552,11 +586,15 @@ $code.=<<___;
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.arch armv7-a
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.arch armv7-a
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.fpu neon
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.fpu neon
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.global sha512_block_data_order_neon
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.type sha512_block_data_order_neon,%function
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.align 4
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.align 4
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sha512_block_data_order_neon:
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.LNEON:
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.LNEON:
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dmb @ errata #451034 on early Cortex A8
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dmb @ errata #451034 on early Cortex A8
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vstmdb sp!,{d8-d15} @ ABI specification says so
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add $len,$inp,$len,lsl#7 @ len to point at the end of inp
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sub $Ktbl,r3,#672 @ K512
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VFP_ABI_PUSH
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adrl $Ktbl,K512
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vldmia $ctx,{$A-$H} @ load context
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vldmia $ctx,{$A-$H} @ load context
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.Loop_neon:
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.Loop_neon:
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___
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___
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@ -581,16 +619,16 @@ $code.=<<___;
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sub $Ktbl,#640 @ rewind K512
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sub $Ktbl,#640 @ rewind K512
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bne .Loop_neon
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bne .Loop_neon
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vldmia sp!,{d8-d15} @ epilogue
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VFP_ABI_POP
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ret @ bx lr
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ret @ bx lr
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.size sha512_block_data_order_neon,.-sha512_block_data_order_neon
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#endif
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#endif
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___
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___
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}
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}
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$code.=<<___;
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$code.=<<___;
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.size sha512_block_data_order,.-sha512_block_data_order
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.asciz "SHA512 block transform for ARMv4/NEON, CRYPTOGAMS by <appro\@openssl.org>"
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.asciz "SHA512 block transform for ARMv4/NEON, CRYPTOGAMS by <appro\@openssl.org>"
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.align 2
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.align 2
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#if __ARM_MAX_ARCH__>=7
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#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
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.comm OPENSSL_armcap_P,4,4
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.comm OPENSSL_armcap_P,4,4
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.hidden OPENSSL_armcap_P
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.hidden OPENSSL_armcap_P
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#endif
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#endif
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@ -599,5 +637,14 @@ ___
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$code =~ s/\`([^\`]*)\`/eval $1/gem;
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$code =~ s/\`([^\`]*)\`/eval $1/gem;
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$code =~ s/\bbx\s+lr\b/.word\t0xe12fff1e/gm; # make it possible to compile with -march=armv4
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$code =~ s/\bbx\s+lr\b/.word\t0xe12fff1e/gm; # make it possible to compile with -march=armv4
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$code =~ s/\bret\b/bx lr/gm;
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$code =~ s/\bret\b/bx lr/gm;
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open SELF,$0;
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while(<SELF>) {
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next if (/^#!/);
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last if (!s/^#/@/ and !/^$/);
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print;
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}
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close SELF;
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print $code;
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print $code;
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close STDOUT; # enforce flush
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close STDOUT; # enforce flush
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