05a8434484
AVX-512 adds a new text instruction syntax to x86-64 assembly to specify the writemask registers and the merge-masking vs zeroing-masking signal. This change causes these tokens to be passed through. Patch by Jeff McDonald. Change-Id: Ib15b15ac684183cc5fba329a176b63b477bc24a3 Reviewed-on: https://boringssl-review.googlesource.com/24945 Commit-Queue: David Benjamin <davidben@google.com> Reviewed-by: David Benjamin <davidben@google.com> CQ-Verified: CQ bot account: commit-bot@chromium.org <commit-bot@chromium.org>
46 lines
1.2 KiB
ArmAsm
46 lines
1.2 KiB
ArmAsm
# Most instructions and lines should pass unaltered. This is made up of
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# copy-and-pasted bits of compiler output and likely does not actually
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# run.
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.file "bcm.c"
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.text
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.type foo, @function
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.globl foo
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foo:
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.file 1 "../foo/bar.c"
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.loc 1 2 3
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.cfi_startproc
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pushq %rbp
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.cfi_def_cfa_offset 16
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.cfi_offset 6, -16
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movq %rsp, %rbp
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movq %rdi, -24(%rbp)
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movq -24(%rbp), %rax
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.loc 1 168 0 is_stmt 0 discriminator 1
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cmpq -8(%rbp), %rax
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jmpq *%rax
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movdqa %xmm3,%xmm10
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psrlq $1,%xmm3
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pxor %xmm6,%xmm5
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pxor %xmm4,%xmm3
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pand %xmm7,%xmm5
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pand %xmm7,%xmm3
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pxor %xmm5,%xmm6
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paddd 112(%r11),%xmm15
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vmovdqa %xmm0,%xmm5
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vpunpckhqdq %xmm0,%xmm0,%xmm3
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vpxor %xmm0,%xmm3,%xmm3
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vpclmulqdq $0x11,%xmm2,%xmm0,%xmm1
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vpclmulqdq $0x00,%xmm2,%xmm0,%xmm0
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vpclmulqdq $0x00,%xmm6,%xmm3,%xmm3
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vpxor %xmm0,%xmm1,%xmm4
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vpxor %xmm4,%xmm3,%xmm3
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vmovdqu8 %ymm1,%ymm6{%k1}{z}
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vmovdqu8 %ymm2,%ymm4{%k3}
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.byte 0xf3,0xc3
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movq %rax, %rbx # Comments can be on the same line as an instruction.
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.L3: # Or on the same line as a label.
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.L4: .L5: movq %rbx, %rax # This is also legal.
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.size foo, .-foo
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.type foo, @function
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