97999919bb
We are leaking asm symbols in Android builds because the asm code isn't affected by -fvisibility=hidden. This change hides all asm symbols. This assumes that no asm symbols are public API and that should be true. Some points to note: In crypto/rc4/asm/rc4-md5-x86_64.pl there are |RC4_set_key| and |RC4_options| functions which aren't getting marked as hidden. That's because those functions aren't actually ever generated. (I'm just trying to minimise drift with upstream here.) In crypto/rc4/asm/rc4-x86_64.pl there's |RC4_options| which is "public" API, except that we've never had it in the header files. So I've just deleted it. Since we have an internal caller, we'll probably have to put it back in the future, but it can just be done in rc4.c to save problems. BUG=448386 Change-Id: I3846617a0e3d73ec9e5ec3638a53364adbbc6260 Reviewed-on: https://boringssl-review.googlesource.com/3520 Reviewed-by: David Benjamin <davidben@chromium.org> Reviewed-by: Adam Langley <agl@google.com>
656 lines
15 KiB
Perl
656 lines
15 KiB
Perl
#!/usr/bin/env perl
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#
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# ====================================================================
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# Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
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# project. The module is, however, dual licensed under OpenSSL and
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# CRYPTOGAMS licenses depending on where you obtain it. For further
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# details see http://www.openssl.org/~appro/cryptogams/.
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# ====================================================================
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#
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# July 2004
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#
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# 2.22x RC4 tune-up:-) It should be noted though that my hand [as in
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# "hand-coded assembler"] doesn't stand for the whole improvement
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# coefficient. It turned out that eliminating RC4_CHAR from config
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# line results in ~40% improvement (yes, even for C implementation).
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# Presumably it has everything to do with AMD cache architecture and
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# RAW or whatever penalties. Once again! The module *requires* config
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# line *without* RC4_CHAR! As for coding "secret," I bet on partial
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# register arithmetics. For example instead of 'inc %r8; and $255,%r8'
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# I simply 'inc %r8b'. Even though optimization manual discourages
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# to operate on partial registers, it turned out to be the best bet.
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# At least for AMD... How IA32E would perform remains to be seen...
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# November 2004
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#
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# As was shown by Marc Bevand reordering of couple of load operations
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# results in even higher performance gain of 3.3x:-) At least on
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# Opteron... For reference, 1x in this case is RC4_CHAR C-code
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# compiled with gcc 3.3.2, which performs at ~54MBps per 1GHz clock.
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# Latter means that if you want to *estimate* what to expect from
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# *your* Opteron, then multiply 54 by 3.3 and clock frequency in GHz.
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# November 2004
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#
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# Intel P4 EM64T core was found to run the AMD64 code really slow...
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# The only way to achieve comparable performance on P4 was to keep
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# RC4_CHAR. Kind of ironic, huh? As it's apparently impossible to
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# compose blended code, which would perform even within 30% marginal
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# on either AMD and Intel platforms, I implement both cases. See
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# rc4_skey.c for further details...
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# April 2005
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#
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# P4 EM64T core appears to be "allergic" to 64-bit inc/dec. Replacing
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# those with add/sub results in 50% performance improvement of folded
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# loop...
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# May 2005
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#
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# As was shown by Zou Nanhai loop unrolling can improve Intel EM64T
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# performance by >30% [unlike P4 32-bit case that is]. But this is
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# provided that loads are reordered even more aggressively! Both code
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# pathes, AMD64 and EM64T, reorder loads in essentially same manner
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# as my IA-64 implementation. On Opteron this resulted in modest 5%
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# improvement [I had to test it], while final Intel P4 performance
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# achieves respectful 432MBps on 2.8GHz processor now. For reference.
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# If executed on Xeon, current RC4_CHAR code-path is 2.7x faster than
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# RC4_INT code-path. While if executed on Opteron, it's only 25%
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# slower than the RC4_INT one [meaning that if CPU <20>-arch detection
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# is not implemented, then this final RC4_CHAR code-path should be
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# preferred, as it provides better *all-round* performance].
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# March 2007
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#
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# Intel Core2 was observed to perform poorly on both code paths:-( It
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# apparently suffers from some kind of partial register stall, which
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# occurs in 64-bit mode only [as virtually identical 32-bit loop was
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# observed to outperform 64-bit one by almost 50%]. Adding two movzb to
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# cloop1 boosts its performance by 80%! This loop appears to be optimal
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# fit for Core2 and therefore the code was modified to skip cloop8 on
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# this CPU.
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# May 2010
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#
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# Intel Westmere was observed to perform suboptimally. Adding yet
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# another movzb to cloop1 improved performance by almost 50%! Core2
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# performance is improved too, but nominally...
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# May 2011
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#
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# The only code path that was not modified is P4-specific one. Non-P4
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# Intel code path optimization is heavily based on submission by Maxim
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# Perminov, Maxim Locktyukhin and Jim Guilford of Intel. I've used
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# some of the ideas even in attempt to optmize the original RC4_INT
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# code path... Current performance in cycles per processed byte (less
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# is better) and improvement coefficients relative to previous
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# version of this module are:
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#
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# Opteron 5.3/+0%(*)
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# P4 6.5
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# Core2 6.2/+15%(**)
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# Westmere 4.2/+60%
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# Sandy Bridge 4.2/+120%
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# Atom 9.3/+80%
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#
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# (*) But corresponding loop has less instructions, which should have
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# positive effect on upcoming Bulldozer, which has one less ALU.
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# For reference, Intel code runs at 6.8 cpb rate on Opteron.
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# (**) Note that Core2 result is ~15% lower than corresponding result
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# for 32-bit code, meaning that it's possible to improve it,
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# but more than likely at the cost of the others (see rc4-586.pl
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# to get the idea)...
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$flavour = shift;
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$output = shift;
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if ($flavour =~ /\./) { $output = $flavour; undef $flavour; }
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$win64=0; $win64=1 if ($flavour =~ /[nm]asm|mingw64/ || $output =~ /\.asm$/);
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$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
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( $xlate="${dir}x86_64-xlate.pl" and -f $xlate ) or
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( $xlate="${dir}../../perlasm/x86_64-xlate.pl" and -f $xlate) or
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die "can't locate x86_64-xlate.pl";
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open OUT,"| \"$^X\" $xlate $flavour $output";
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*STDOUT=*OUT;
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$dat="%rdi"; # arg1
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$len="%rsi"; # arg2
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$inp="%rdx"; # arg3
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$out="%rcx"; # arg4
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{
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$code=<<___;
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.text
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.extern OPENSSL_ia32cap_P
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.globl asm_RC4
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.type asm_RC4,\@function,4
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.hidden asm_RC4
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.align 16
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asm_RC4:
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or $len,$len
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jne .Lentry
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ret
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.Lentry:
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push %rbx
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push %r12
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push %r13
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.Lprologue:
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mov $len,%r11
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mov $inp,%r12
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mov $out,%r13
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___
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my $len="%r11"; # reassign input arguments
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my $inp="%r12";
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my $out="%r13";
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my @XX=("%r10","%rsi");
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my @TX=("%rax","%rbx");
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my $YY="%rcx";
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my $TY="%rdx";
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$code.=<<___;
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xor $XX[0],$XX[0]
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xor $YY,$YY
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lea 8($dat),$dat
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mov -8($dat),$XX[0]#b
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mov -4($dat),$YY#b
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cmpl \$-1,256($dat)
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je .LRC4_CHAR
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mov OPENSSL_ia32cap_P(%rip),%r8d
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xor $TX[1],$TX[1]
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inc $XX[0]#b
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sub $XX[0],$TX[1]
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sub $inp,$out
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movl ($dat,$XX[0],4),$TX[0]#d
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test \$-16,$len
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jz .Lloop1
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bt \$30,%r8d # Intel CPU?
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jc .Lintel
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and \$7,$TX[1]
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lea 1($XX[0]),$XX[1]
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jz .Loop8
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sub $TX[1],$len
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.Loop8_warmup:
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add $TX[0]#b,$YY#b
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movl ($dat,$YY,4),$TY#d
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movl $TX[0]#d,($dat,$YY,4)
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movl $TY#d,($dat,$XX[0],4)
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add $TY#b,$TX[0]#b
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inc $XX[0]#b
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movl ($dat,$TX[0],4),$TY#d
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movl ($dat,$XX[0],4),$TX[0]#d
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xorb ($inp),$TY#b
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movb $TY#b,($out,$inp)
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lea 1($inp),$inp
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dec $TX[1]
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jnz .Loop8_warmup
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lea 1($XX[0]),$XX[1]
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jmp .Loop8
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.align 16
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.Loop8:
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___
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for ($i=0;$i<8;$i++) {
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$code.=<<___ if ($i==7);
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add \$8,$XX[1]#b
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___
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$code.=<<___;
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add $TX[0]#b,$YY#b
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movl ($dat,$YY,4),$TY#d
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movl $TX[0]#d,($dat,$YY,4)
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movl `4*($i==7?-1:$i)`($dat,$XX[1],4),$TX[1]#d
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ror \$8,%r8 # ror is redundant when $i=0
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movl $TY#d,4*$i($dat,$XX[0],4)
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add $TX[0]#b,$TY#b
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movb ($dat,$TY,4),%r8b
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___
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push(@TX,shift(@TX)); #push(@XX,shift(@XX)); # "rotate" registers
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}
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$code.=<<___;
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add \$8,$XX[0]#b
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ror \$8,%r8
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sub \$8,$len
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xor ($inp),%r8
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mov %r8,($out,$inp)
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lea 8($inp),$inp
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test \$-8,$len
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jnz .Loop8
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cmp \$0,$len
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jne .Lloop1
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jmp .Lexit
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.align 16
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.Lintel:
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test \$-32,$len
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jz .Lloop1
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and \$15,$TX[1]
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jz .Loop16_is_hot
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sub $TX[1],$len
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.Loop16_warmup:
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add $TX[0]#b,$YY#b
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movl ($dat,$YY,4),$TY#d
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movl $TX[0]#d,($dat,$YY,4)
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movl $TY#d,($dat,$XX[0],4)
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add $TY#b,$TX[0]#b
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inc $XX[0]#b
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movl ($dat,$TX[0],4),$TY#d
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movl ($dat,$XX[0],4),$TX[0]#d
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xorb ($inp),$TY#b
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movb $TY#b,($out,$inp)
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lea 1($inp),$inp
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dec $TX[1]
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jnz .Loop16_warmup
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mov $YY,$TX[1]
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xor $YY,$YY
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mov $TX[1]#b,$YY#b
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.Loop16_is_hot:
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lea ($dat,$XX[0],4),$XX[1]
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___
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sub RC4_loop {
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my $i=shift;
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my $j=$i<0?0:$i;
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my $xmm="%xmm".($j&1);
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$code.=" add \$16,$XX[0]#b\n" if ($i==15);
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$code.=" movdqu ($inp),%xmm2\n" if ($i==15);
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$code.=" add $TX[0]#b,$YY#b\n" if ($i<=0);
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$code.=" movl ($dat,$YY,4),$TY#d\n";
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$code.=" pxor %xmm0,%xmm2\n" if ($i==0);
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$code.=" psllq \$8,%xmm1\n" if ($i==0);
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$code.=" pxor $xmm,$xmm\n" if ($i<=1);
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$code.=" movl $TX[0]#d,($dat,$YY,4)\n";
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$code.=" add $TY#b,$TX[0]#b\n";
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$code.=" movl `4*($j+1)`($XX[1]),$TX[1]#d\n" if ($i<15);
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$code.=" movz $TX[0]#b,$TX[0]#d\n";
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$code.=" movl $TY#d,4*$j($XX[1])\n";
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$code.=" pxor %xmm1,%xmm2\n" if ($i==0);
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$code.=" lea ($dat,$XX[0],4),$XX[1]\n" if ($i==15);
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$code.=" add $TX[1]#b,$YY#b\n" if ($i<15);
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$code.=" pinsrw \$`($j>>1)&7`,($dat,$TX[0],4),$xmm\n";
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$code.=" movdqu %xmm2,($out,$inp)\n" if ($i==0);
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$code.=" lea 16($inp),$inp\n" if ($i==0);
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$code.=" movl ($XX[1]),$TX[1]#d\n" if ($i==15);
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}
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RC4_loop(-1);
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$code.=<<___;
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jmp .Loop16_enter
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.align 16
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.Loop16:
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___
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for ($i=0;$i<16;$i++) {
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$code.=".Loop16_enter:\n" if ($i==1);
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RC4_loop($i);
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push(@TX,shift(@TX)); # "rotate" registers
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}
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$code.=<<___;
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mov $YY,$TX[1]
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xor $YY,$YY # keyword to partial register
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sub \$16,$len
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mov $TX[1]#b,$YY#b
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test \$-16,$len
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jnz .Loop16
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psllq \$8,%xmm1
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pxor %xmm0,%xmm2
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pxor %xmm1,%xmm2
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movdqu %xmm2,($out,$inp)
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lea 16($inp),$inp
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cmp \$0,$len
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jne .Lloop1
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jmp .Lexit
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.align 16
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.Lloop1:
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add $TX[0]#b,$YY#b
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movl ($dat,$YY,4),$TY#d
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movl $TX[0]#d,($dat,$YY,4)
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movl $TY#d,($dat,$XX[0],4)
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add $TY#b,$TX[0]#b
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inc $XX[0]#b
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movl ($dat,$TX[0],4),$TY#d
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movl ($dat,$XX[0],4),$TX[0]#d
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xorb ($inp),$TY#b
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movb $TY#b,($out,$inp)
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lea 1($inp),$inp
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dec $len
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jnz .Lloop1
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jmp .Lexit
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.align 16
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.LRC4_CHAR:
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add \$1,$XX[0]#b
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movzb ($dat,$XX[0]),$TX[0]#d
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test \$-8,$len
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jz .Lcloop1
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jmp .Lcloop8
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.align 16
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.Lcloop8:
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mov ($inp),%r8d
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mov 4($inp),%r9d
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___
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# unroll 2x4-wise, because 64-bit rotates kill Intel P4...
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for ($i=0;$i<4;$i++) {
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$code.=<<___;
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add $TX[0]#b,$YY#b
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lea 1($XX[0]),$XX[1]
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movzb ($dat,$YY),$TY#d
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movzb $XX[1]#b,$XX[1]#d
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movzb ($dat,$XX[1]),$TX[1]#d
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movb $TX[0]#b,($dat,$YY)
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cmp $XX[1],$YY
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movb $TY#b,($dat,$XX[0])
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jne .Lcmov$i # Intel cmov is sloooow...
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mov $TX[0],$TX[1]
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.Lcmov$i:
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add $TX[0]#b,$TY#b
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xor ($dat,$TY),%r8b
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ror \$8,%r8d
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___
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push(@TX,shift(@TX)); push(@XX,shift(@XX)); # "rotate" registers
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}
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for ($i=4;$i<8;$i++) {
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$code.=<<___;
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add $TX[0]#b,$YY#b
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lea 1($XX[0]),$XX[1]
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movzb ($dat,$YY),$TY#d
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movzb $XX[1]#b,$XX[1]#d
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movzb ($dat,$XX[1]),$TX[1]#d
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movb $TX[0]#b,($dat,$YY)
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cmp $XX[1],$YY
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movb $TY#b,($dat,$XX[0])
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jne .Lcmov$i # Intel cmov is sloooow...
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mov $TX[0],$TX[1]
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.Lcmov$i:
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add $TX[0]#b,$TY#b
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xor ($dat,$TY),%r9b
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ror \$8,%r9d
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___
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push(@TX,shift(@TX)); push(@XX,shift(@XX)); # "rotate" registers
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}
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$code.=<<___;
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lea -8($len),$len
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mov %r8d,($out)
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lea 8($inp),$inp
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mov %r9d,4($out)
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lea 8($out),$out
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test \$-8,$len
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jnz .Lcloop8
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cmp \$0,$len
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jne .Lcloop1
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jmp .Lexit
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___
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$code.=<<___;
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.align 16
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.Lcloop1:
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add $TX[0]#b,$YY#b
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movzb $YY#b,$YY#d
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movzb ($dat,$YY),$TY#d
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movb $TX[0]#b,($dat,$YY)
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movb $TY#b,($dat,$XX[0])
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add $TX[0]#b,$TY#b
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add \$1,$XX[0]#b
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movzb $TY#b,$TY#d
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movzb $XX[0]#b,$XX[0]#d
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movzb ($dat,$TY),$TY#d
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movzb ($dat,$XX[0]),$TX[0]#d
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xorb ($inp),$TY#b
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lea 1($inp),$inp
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movb $TY#b,($out)
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lea 1($out),$out
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sub \$1,$len
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jnz .Lcloop1
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jmp .Lexit
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.align 16
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.Lexit:
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sub \$1,$XX[0]#b
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movl $XX[0]#d,-8($dat)
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movl $YY#d,-4($dat)
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mov (%rsp),%r13
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mov 8(%rsp),%r12
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mov 16(%rsp),%rbx
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add \$24,%rsp
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.Lepilogue:
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ret
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.size asm_RC4,.-asm_RC4
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___
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}
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$idx="%r8";
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$ido="%r9";
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$code.=<<___;
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.globl asm_RC4_set_key
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.type asm_RC4_set_key,\@function,3
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.hidden asm_RC4_set_key
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.align 16
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asm_RC4_set_key:
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lea 8($dat),$dat
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lea ($inp,$len),$inp
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neg $len
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mov $len,%rcx
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xor %eax,%eax
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xor $ido,$ido
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xor %r10,%r10
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||
xor %r11,%r11
|
||
|
||
mov OPENSSL_ia32cap_P(%rip),$idx#d
|
||
bt \$20,$idx#d # RC4_CHAR?
|
||
jc .Lc1stloop
|
||
jmp .Lw1stloop
|
||
|
||
.align 16
|
||
.Lw1stloop:
|
||
mov %eax,($dat,%rax,4)
|
||
add \$1,%al
|
||
jnc .Lw1stloop
|
||
|
||
xor $ido,$ido
|
||
xor $idx,$idx
|
||
.align 16
|
||
.Lw2ndloop:
|
||
mov ($dat,$ido,4),%r10d
|
||
add ($inp,$len,1),$idx#b
|
||
add %r10b,$idx#b
|
||
add \$1,$len
|
||
mov ($dat,$idx,4),%r11d
|
||
cmovz %rcx,$len
|
||
mov %r10d,($dat,$idx,4)
|
||
mov %r11d,($dat,$ido,4)
|
||
add \$1,$ido#b
|
||
jnc .Lw2ndloop
|
||
jmp .Lexit_key
|
||
|
||
.align 16
|
||
.Lc1stloop:
|
||
mov %al,($dat,%rax)
|
||
add \$1,%al
|
||
jnc .Lc1stloop
|
||
|
||
xor $ido,$ido
|
||
xor $idx,$idx
|
||
.align 16
|
||
.Lc2ndloop:
|
||
mov ($dat,$ido),%r10b
|
||
add ($inp,$len),$idx#b
|
||
add %r10b,$idx#b
|
||
add \$1,$len
|
||
mov ($dat,$idx),%r11b
|
||
jnz .Lcnowrap
|
||
mov %rcx,$len
|
||
.Lcnowrap:
|
||
mov %r10b,($dat,$idx)
|
||
mov %r11b,($dat,$ido)
|
||
add \$1,$ido#b
|
||
jnc .Lc2ndloop
|
||
movl \$-1,256($dat)
|
||
|
||
.align 16
|
||
.Lexit_key:
|
||
xor %eax,%eax
|
||
mov %eax,-8($dat)
|
||
mov %eax,-4($dat)
|
||
ret
|
||
.size asm_RC4_set_key,.-asm_RC4_set_key
|
||
___
|
||
|
||
# EXCEPTION_DISPOSITION handler (EXCEPTION_RECORD *rec,ULONG64 frame,
|
||
# CONTEXT *context,DISPATCHER_CONTEXT *disp)
|
||
if ($win64) {
|
||
$rec="%rcx";
|
||
$frame="%rdx";
|
||
$context="%r8";
|
||
$disp="%r9";
|
||
|
||
$code.=<<___;
|
||
.extern __imp_RtlVirtualUnwind
|
||
.type stream_se_handler,\@abi-omnipotent
|
||
.align 16
|
||
stream_se_handler:
|
||
push %rsi
|
||
push %rdi
|
||
push %rbx
|
||
push %rbp
|
||
push %r12
|
||
push %r13
|
||
push %r14
|
||
push %r15
|
||
pushfq
|
||
sub \$64,%rsp
|
||
|
||
mov 120($context),%rax # pull context->Rax
|
||
mov 248($context),%rbx # pull context->Rip
|
||
|
||
lea .Lprologue(%rip),%r10
|
||
cmp %r10,%rbx # context->Rip<prologue label
|
||
jb .Lin_prologue
|
||
|
||
mov 152($context),%rax # pull context->Rsp
|
||
|
||
lea .Lepilogue(%rip),%r10
|
||
cmp %r10,%rbx # context->Rip>=epilogue label
|
||
jae .Lin_prologue
|
||
|
||
lea 24(%rax),%rax
|
||
|
||
mov -8(%rax),%rbx
|
||
mov -16(%rax),%r12
|
||
mov -24(%rax),%r13
|
||
mov %rbx,144($context) # restore context->Rbx
|
||
mov %r12,216($context) # restore context->R12
|
||
mov %r13,224($context) # restore context->R13
|
||
|
||
.Lin_prologue:
|
||
mov 8(%rax),%rdi
|
||
mov 16(%rax),%rsi
|
||
mov %rax,152($context) # restore context->Rsp
|
||
mov %rsi,168($context) # restore context->Rsi
|
||
mov %rdi,176($context) # restore context->Rdi
|
||
|
||
jmp .Lcommon_seh_exit
|
||
.size stream_se_handler,.-stream_se_handler
|
||
|
||
.type key_se_handler,\@abi-omnipotent
|
||
.align 16
|
||
key_se_handler:
|
||
push %rsi
|
||
push %rdi
|
||
push %rbx
|
||
push %rbp
|
||
push %r12
|
||
push %r13
|
||
push %r14
|
||
push %r15
|
||
pushfq
|
||
sub \$64,%rsp
|
||
|
||
mov 152($context),%rax # pull context->Rsp
|
||
mov 8(%rax),%rdi
|
||
mov 16(%rax),%rsi
|
||
mov %rsi,168($context) # restore context->Rsi
|
||
mov %rdi,176($context) # restore context->Rdi
|
||
|
||
.Lcommon_seh_exit:
|
||
|
||
mov 40($disp),%rdi # disp->ContextRecord
|
||
mov $context,%rsi # context
|
||
mov \$154,%ecx # sizeof(CONTEXT)
|
||
.long 0xa548f3fc # cld; rep movsq
|
||
|
||
mov $disp,%rsi
|
||
xor %rcx,%rcx # arg1, UNW_FLAG_NHANDLER
|
||
mov 8(%rsi),%rdx # arg2, disp->ImageBase
|
||
mov 0(%rsi),%r8 # arg3, disp->ControlPc
|
||
mov 16(%rsi),%r9 # arg4, disp->FunctionEntry
|
||
mov 40(%rsi),%r10 # disp->ContextRecord
|
||
lea 56(%rsi),%r11 # &disp->HandlerData
|
||
lea 24(%rsi),%r12 # &disp->EstablisherFrame
|
||
mov %r10,32(%rsp) # arg5
|
||
mov %r11,40(%rsp) # arg6
|
||
mov %r12,48(%rsp) # arg7
|
||
mov %rcx,56(%rsp) # arg8, (NULL)
|
||
call *__imp_RtlVirtualUnwind(%rip)
|
||
|
||
mov \$1,%eax # ExceptionContinueSearch
|
||
add \$64,%rsp
|
||
popfq
|
||
pop %r15
|
||
pop %r14
|
||
pop %r13
|
||
pop %r12
|
||
pop %rbp
|
||
pop %rbx
|
||
pop %rdi
|
||
pop %rsi
|
||
ret
|
||
.size key_se_handler,.-key_se_handler
|
||
|
||
.section .pdata
|
||
.align 4
|
||
.rva .LSEH_begin_asm_RC4
|
||
.rva .LSEH_end_asm_RC4
|
||
.rva .LSEH_info_asm_RC4
|
||
|
||
.rva .LSEH_begin_asm_RC4_set_key
|
||
.rva .LSEH_end_asm_RC4_set_key
|
||
.rva .LSEH_info_asm_RC4_set_key
|
||
|
||
.section .xdata
|
||
.align 8
|
||
.LSEH_info_asm_RC4:
|
||
.byte 9,0,0,0
|
||
.rva stream_se_handler
|
||
.LSEH_info_asm_RC4_set_key:
|
||
.byte 9,0,0,0
|
||
.rva key_se_handler
|
||
___
|
||
}
|
||
|
||
sub reg_part {
|
||
my ($reg,$conv)=@_;
|
||
if ($reg =~ /%r[0-9]+/) { $reg .= $conv; }
|
||
elsif ($conv eq "b") { $reg =~ s/%[er]([^x]+)x?/%$1l/; }
|
||
elsif ($conv eq "w") { $reg =~ s/%[er](.+)/%$1/; }
|
||
elsif ($conv eq "d") { $reg =~ s/%[er](.+)/%e$1/; }
|
||
return $reg;
|
||
}
|
||
|
||
$code =~ s/(%[a-z0-9]+)#([bwd])/reg_part($1,$2)/gem;
|
||
$code =~ s/\`([^\`]*)\`/eval $1/gem;
|
||
|
||
print $code;
|
||
|
||
close STDOUT;
|