72d9cba7cb
2ab24a2d40 added sections to ARM assembly
files. However, in cases where .align directives were not next to the
labels that they were intended to apply to, the section directives would
cause them to be ignored.
Change-Id: I32117f6747ff8545b80c70dd3b8effdc6e6f67e0
Reviewed-on: https://boringssl-review.googlesource.com/6050
Reviewed-by: David Benjamin <davidben@chromium.org>
Reviewed-by: Adam Langley <agl@google.com>
697 lines
18 KiB
Prolog
697 lines
18 KiB
Prolog
#!/usr/bin/env perl
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# ====================================================================
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# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
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# project. The module is, however, dual licensed under OpenSSL and
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# CRYPTOGAMS licenses depending on where you obtain it. For further
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# details see http://www.openssl.org/~appro/cryptogams/.
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# ====================================================================
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# January 2007.
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# Montgomery multiplication for ARMv4.
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#
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# Performance improvement naturally varies among CPU implementations
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# and compilers. The code was observed to provide +65-35% improvement
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# [depending on key length, less for longer keys] on ARM920T, and
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# +115-80% on Intel IXP425. This is compared to pre-bn_mul_mont code
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# base and compiler generated code with in-lined umull and even umlal
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# instructions. The latter means that this code didn't really have an
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# "advantage" of utilizing some "secret" instruction.
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#
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# The code is interoperable with Thumb ISA and is rather compact, less
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# than 1/2KB. Windows CE port would be trivial, as it's exclusively
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# about decorations, ABI and instruction syntax are identical.
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# November 2013
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#
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# Add NEON code path, which handles lengths divisible by 8. RSA/DSA
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# performance improvement on Cortex-A8 is ~45-100% depending on key
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# length, more for longer keys. On Cortex-A15 the span is ~10-105%.
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# On Snapdragon S4 improvement was measured to vary from ~70% to
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# incredible ~380%, yes, 4.8x faster, for RSA4096 sign. But this is
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# rather because original integer-only code seems to perform
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# suboptimally on S4. Situation on Cortex-A9 is unfortunately
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# different. It's being looked into, but the trouble is that
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# performance for vectors longer than 256 bits is actually couple
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# of percent worse than for integer-only code. The code is chosen
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# for execution on all NEON-capable processors, because gain on
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# others outweighs the marginal loss on Cortex-A9.
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$flavour = shift;
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if ($flavour=~/^\w[\w\-]*\.\w+$/) { $output=$flavour; undef $flavour; }
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else { while (($output=shift) && ($output!~/^\w[\w\-]*\.\w+$/)) {} }
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if ($flavour && $flavour ne "void") {
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$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
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( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or
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( $xlate="${dir}../../perlasm/arm-xlate.pl" and -f $xlate) or
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die "can't locate arm-xlate.pl";
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open STDOUT,"| \"$^X\" $xlate $flavour $output";
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} else {
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open STDOUT,">$output";
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}
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$num="r0"; # starts as num argument, but holds &tp[num-1]
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$ap="r1";
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$bp="r2"; $bi="r2"; $rp="r2";
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$np="r3";
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$tp="r4";
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$aj="r5";
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$nj="r6";
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$tj="r7";
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$n0="r8";
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########### # r9 is reserved by ELF as platform specific, e.g. TLS pointer
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$alo="r10"; # sl, gcc uses it to keep @GOT
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$ahi="r11"; # fp
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$nlo="r12"; # ip
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########### # r13 is stack pointer
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$nhi="r14"; # lr
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########### # r15 is program counter
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#### argument block layout relative to &tp[num-1], a.k.a. $num
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$_rp="$num,#12*4";
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# ap permanently resides in r1
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$_bp="$num,#13*4";
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# np permanently resides in r3
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$_n0="$num,#14*4";
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$_num="$num,#15*4"; $_bpend=$_num;
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$code=<<___;
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#include <openssl/arm_arch.h>
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.text
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.code 32
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#if __ARM_MAX_ARCH__>=7
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.pushsection .text.bn_mul_mont,"ax",%progbits
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.align 5
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.LOPENSSL_armcap:
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.word OPENSSL_armcap_P-.Lbn_mul_mont
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.popsection
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#endif
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.global bn_mul_mont
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.hidden bn_mul_mont
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.type bn_mul_mont,%function
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.align 5
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bn_mul_mont:
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.Lbn_mul_mont:
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ldr ip,[sp,#4] @ load num
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stmdb sp!,{r0,r2} @ sp points at argument block
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#if __ARM_MAX_ARCH__>=7
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tst ip,#7
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bne .Lialu
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adr r0,bn_mul_mont
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ldr r2,.LOPENSSL_armcap
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ldr r0,[r0,r2]
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#ifdef __APPLE__
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ldr r0,[r0]
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#endif
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tst r0,#1 @ NEON available?
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ldmia sp, {r0,r2}
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beq .Lialu
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add sp,sp,#8
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b bn_mul8x_mont_neon
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.align 4
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.Lialu:
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#endif
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cmp ip,#2
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mov $num,ip @ load num
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movlt r0,#0
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addlt sp,sp,#2*4
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blt .Labrt
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stmdb sp!,{r4-r12,lr} @ save 10 registers
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mov $num,$num,lsl#2 @ rescale $num for byte count
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sub sp,sp,$num @ alloca(4*num)
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sub sp,sp,#4 @ +extra dword
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sub $num,$num,#4 @ "num=num-1"
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add $tp,$bp,$num @ &bp[num-1]
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add $num,sp,$num @ $num to point at &tp[num-1]
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ldr $n0,[$_n0] @ &n0
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ldr $bi,[$bp] @ bp[0]
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ldr $aj,[$ap],#4 @ ap[0],ap++
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ldr $nj,[$np],#4 @ np[0],np++
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ldr $n0,[$n0] @ *n0
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str $tp,[$_bpend] @ save &bp[num]
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umull $alo,$ahi,$aj,$bi @ ap[0]*bp[0]
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str $n0,[$_n0] @ save n0 value
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mul $n0,$alo,$n0 @ "tp[0]"*n0
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mov $nlo,#0
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umlal $alo,$nlo,$nj,$n0 @ np[0]*n0+"t[0]"
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mov $tp,sp
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.L1st:
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ldr $aj,[$ap],#4 @ ap[j],ap++
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mov $alo,$ahi
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ldr $nj,[$np],#4 @ np[j],np++
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mov $ahi,#0
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umlal $alo,$ahi,$aj,$bi @ ap[j]*bp[0]
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mov $nhi,#0
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umlal $nlo,$nhi,$nj,$n0 @ np[j]*n0
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adds $nlo,$nlo,$alo
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str $nlo,[$tp],#4 @ tp[j-1]=,tp++
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adc $nlo,$nhi,#0
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cmp $tp,$num
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bne .L1st
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adds $nlo,$nlo,$ahi
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ldr $tp,[$_bp] @ restore bp
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mov $nhi,#0
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ldr $n0,[$_n0] @ restore n0
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adc $nhi,$nhi,#0
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str $nlo,[$num] @ tp[num-1]=
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str $nhi,[$num,#4] @ tp[num]=
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.Louter:
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sub $tj,$num,sp @ "original" $num-1 value
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sub $ap,$ap,$tj @ "rewind" ap to &ap[1]
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ldr $bi,[$tp,#4]! @ *(++bp)
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sub $np,$np,$tj @ "rewind" np to &np[1]
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ldr $aj,[$ap,#-4] @ ap[0]
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ldr $alo,[sp] @ tp[0]
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ldr $nj,[$np,#-4] @ np[0]
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ldr $tj,[sp,#4] @ tp[1]
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mov $ahi,#0
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umlal $alo,$ahi,$aj,$bi @ ap[0]*bp[i]+tp[0]
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str $tp,[$_bp] @ save bp
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mul $n0,$alo,$n0
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mov $nlo,#0
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umlal $alo,$nlo,$nj,$n0 @ np[0]*n0+"tp[0]"
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mov $tp,sp
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.Linner:
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ldr $aj,[$ap],#4 @ ap[j],ap++
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adds $alo,$ahi,$tj @ +=tp[j]
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ldr $nj,[$np],#4 @ np[j],np++
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mov $ahi,#0
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umlal $alo,$ahi,$aj,$bi @ ap[j]*bp[i]
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mov $nhi,#0
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umlal $nlo,$nhi,$nj,$n0 @ np[j]*n0
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adc $ahi,$ahi,#0
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ldr $tj,[$tp,#8] @ tp[j+1]
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adds $nlo,$nlo,$alo
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str $nlo,[$tp],#4 @ tp[j-1]=,tp++
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adc $nlo,$nhi,#0
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cmp $tp,$num
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bne .Linner
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adds $nlo,$nlo,$ahi
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mov $nhi,#0
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ldr $tp,[$_bp] @ restore bp
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adc $nhi,$nhi,#0
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ldr $n0,[$_n0] @ restore n0
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adds $nlo,$nlo,$tj
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ldr $tj,[$_bpend] @ restore &bp[num]
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adc $nhi,$nhi,#0
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str $nlo,[$num] @ tp[num-1]=
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str $nhi,[$num,#4] @ tp[num]=
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cmp $tp,$tj
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bne .Louter
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ldr $rp,[$_rp] @ pull rp
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add $num,$num,#4 @ $num to point at &tp[num]
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sub $aj,$num,sp @ "original" num value
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mov $tp,sp @ "rewind" $tp
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mov $ap,$tp @ "borrow" $ap
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sub $np,$np,$aj @ "rewind" $np to &np[0]
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subs $tj,$tj,$tj @ "clear" carry flag
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.Lsub: ldr $tj,[$tp],#4
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ldr $nj,[$np],#4
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sbcs $tj,$tj,$nj @ tp[j]-np[j]
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str $tj,[$rp],#4 @ rp[j]=
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teq $tp,$num @ preserve carry
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bne .Lsub
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sbcs $nhi,$nhi,#0 @ upmost carry
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mov $tp,sp @ "rewind" $tp
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sub $rp,$rp,$aj @ "rewind" $rp
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and $ap,$tp,$nhi
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bic $np,$rp,$nhi
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orr $ap,$ap,$np @ ap=borrow?tp:rp
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.Lcopy: ldr $tj,[$ap],#4 @ copy or in-place refresh
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str sp,[$tp],#4 @ zap tp
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str $tj,[$rp],#4
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cmp $tp,$num
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bne .Lcopy
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add sp,$num,#4 @ skip over tp[num+1]
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ldmia sp!,{r4-r12,lr} @ restore registers
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add sp,sp,#2*4 @ skip over {r0,r2}
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mov r0,#1
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.Labrt:
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#if __ARM_ARCH__>=5
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ret @ bx lr
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#else
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tst lr,#1
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moveq pc,lr @ be binary compatible with V4, yet
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bx lr @ interoperable with Thumb ISA:-)
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#endif
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.size bn_mul_mont,.-bn_mul_mont
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___
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{
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sub Dlo() { shift=~m|q([1]?[0-9])|?"d".($1*2):""; }
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sub Dhi() { shift=~m|q([1]?[0-9])|?"d".($1*2+1):""; }
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my ($A0,$A1,$A2,$A3)=map("d$_",(0..3));
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my ($N0,$N1,$N2,$N3)=map("d$_",(4..7));
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my ($Z,$Temp)=("q4","q5");
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my ($A0xB,$A1xB,$A2xB,$A3xB,$A4xB,$A5xB,$A6xB,$A7xB)=map("q$_",(6..13));
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my ($Bi,$Ni,$M0)=map("d$_",(28..31));
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my $zero=&Dlo($Z);
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my $temp=&Dlo($Temp);
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my ($rptr,$aptr,$bptr,$nptr,$n0,$num)=map("r$_",(0..5));
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my ($tinptr,$toutptr,$inner,$outer)=map("r$_",(6..9));
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$code.=<<___;
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#if __ARM_MAX_ARCH__>=7
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.arch armv7-a
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.fpu neon
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.type bn_mul8x_mont_neon,%function
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.align 5
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bn_mul8x_mont_neon:
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mov ip,sp
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stmdb sp!,{r4-r11}
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vstmdb sp!,{d8-d15} @ ABI specification says so
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ldmia ip,{r4-r5} @ load rest of parameter block
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sub $toutptr,sp,#16
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vld1.32 {${Bi}[0]}, [$bptr,:32]!
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sub $toutptr,$toutptr,$num,lsl#4
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vld1.32 {$A0-$A3}, [$aptr]! @ can't specify :32 :-(
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and $toutptr,$toutptr,#-64
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vld1.32 {${M0}[0]}, [$n0,:32]
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mov sp,$toutptr @ alloca
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veor $zero,$zero,$zero
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subs $inner,$num,#8
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vzip.16 $Bi,$zero
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vmull.u32 $A0xB,$Bi,${A0}[0]
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vmull.u32 $A1xB,$Bi,${A0}[1]
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vmull.u32 $A2xB,$Bi,${A1}[0]
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vshl.i64 $temp,`&Dhi("$A0xB")`,#16
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vmull.u32 $A3xB,$Bi,${A1}[1]
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vadd.u64 $temp,$temp,`&Dlo("$A0xB")`
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veor $zero,$zero,$zero
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vmul.u32 $Ni,$temp,$M0
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vmull.u32 $A4xB,$Bi,${A2}[0]
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vld1.32 {$N0-$N3}, [$nptr]!
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vmull.u32 $A5xB,$Bi,${A2}[1]
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vmull.u32 $A6xB,$Bi,${A3}[0]
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vzip.16 $Ni,$zero
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vmull.u32 $A7xB,$Bi,${A3}[1]
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bne .LNEON_1st
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@ special case for num=8, everything is in register bank...
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vmlal.u32 $A0xB,$Ni,${N0}[0]
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sub $outer,$num,#1
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vmlal.u32 $A1xB,$Ni,${N0}[1]
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vmlal.u32 $A2xB,$Ni,${N1}[0]
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vmlal.u32 $A3xB,$Ni,${N1}[1]
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vmlal.u32 $A4xB,$Ni,${N2}[0]
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vmov $Temp,$A0xB
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vmlal.u32 $A5xB,$Ni,${N2}[1]
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vmov $A0xB,$A1xB
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vmlal.u32 $A6xB,$Ni,${N3}[0]
|
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vmov $A1xB,$A2xB
|
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vmlal.u32 $A7xB,$Ni,${N3}[1]
|
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vmov $A2xB,$A3xB
|
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vmov $A3xB,$A4xB
|
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vshr.u64 $temp,$temp,#16
|
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vmov $A4xB,$A5xB
|
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vmov $A5xB,$A6xB
|
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vadd.u64 $temp,$temp,`&Dhi("$Temp")`
|
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vmov $A6xB,$A7xB
|
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veor $A7xB,$A7xB
|
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vshr.u64 $temp,$temp,#16
|
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|
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b .LNEON_outer8
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|
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.align 4
|
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.LNEON_outer8:
|
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vld1.32 {${Bi}[0]}, [$bptr,:32]!
|
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veor $zero,$zero,$zero
|
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vzip.16 $Bi,$zero
|
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vadd.u64 `&Dlo("$A0xB")`,`&Dlo("$A0xB")`,$temp
|
||
|
||
vmlal.u32 $A0xB,$Bi,${A0}[0]
|
||
vmlal.u32 $A1xB,$Bi,${A0}[1]
|
||
vmlal.u32 $A2xB,$Bi,${A1}[0]
|
||
vshl.i64 $temp,`&Dhi("$A0xB")`,#16
|
||
vmlal.u32 $A3xB,$Bi,${A1}[1]
|
||
|
||
vadd.u64 $temp,$temp,`&Dlo("$A0xB")`
|
||
veor $zero,$zero,$zero
|
||
subs $outer,$outer,#1
|
||
vmul.u32 $Ni,$temp,$M0
|
||
|
||
vmlal.u32 $A4xB,$Bi,${A2}[0]
|
||
vmlal.u32 $A5xB,$Bi,${A2}[1]
|
||
vmlal.u32 $A6xB,$Bi,${A3}[0]
|
||
vzip.16 $Ni,$zero
|
||
vmlal.u32 $A7xB,$Bi,${A3}[1]
|
||
|
||
vmlal.u32 $A0xB,$Ni,${N0}[0]
|
||
vmlal.u32 $A1xB,$Ni,${N0}[1]
|
||
vmlal.u32 $A2xB,$Ni,${N1}[0]
|
||
vmlal.u32 $A3xB,$Ni,${N1}[1]
|
||
|
||
vmlal.u32 $A4xB,$Ni,${N2}[0]
|
||
vmov $Temp,$A0xB
|
||
vmlal.u32 $A5xB,$Ni,${N2}[1]
|
||
vmov $A0xB,$A1xB
|
||
vmlal.u32 $A6xB,$Ni,${N3}[0]
|
||
vmov $A1xB,$A2xB
|
||
vmlal.u32 $A7xB,$Ni,${N3}[1]
|
||
vmov $A2xB,$A3xB
|
||
vmov $A3xB,$A4xB
|
||
vshr.u64 $temp,$temp,#16
|
||
vmov $A4xB,$A5xB
|
||
vmov $A5xB,$A6xB
|
||
vadd.u64 $temp,$temp,`&Dhi("$Temp")`
|
||
vmov $A6xB,$A7xB
|
||
veor $A7xB,$A7xB
|
||
vshr.u64 $temp,$temp,#16
|
||
|
||
bne .LNEON_outer8
|
||
|
||
vadd.u64 `&Dlo("$A0xB")`,`&Dlo("$A0xB")`,$temp
|
||
mov $toutptr,sp
|
||
vshr.u64 $temp,`&Dlo("$A0xB")`,#16
|
||
mov $inner,$num
|
||
vadd.u64 `&Dhi("$A0xB")`,`&Dhi("$A0xB")`,$temp
|
||
add $tinptr,sp,#16
|
||
vshr.u64 $temp,`&Dhi("$A0xB")`,#16
|
||
vzip.16 `&Dlo("$A0xB")`,`&Dhi("$A0xB")`
|
||
|
||
b .LNEON_tail2
|
||
|
||
.align 4
|
||
.LNEON_1st:
|
||
vmlal.u32 $A0xB,$Ni,${N0}[0]
|
||
vld1.32 {$A0-$A3}, [$aptr]!
|
||
vmlal.u32 $A1xB,$Ni,${N0}[1]
|
||
subs $inner,$inner,#8
|
||
vmlal.u32 $A2xB,$Ni,${N1}[0]
|
||
vmlal.u32 $A3xB,$Ni,${N1}[1]
|
||
|
||
vmlal.u32 $A4xB,$Ni,${N2}[0]
|
||
vld1.32 {$N0-$N1}, [$nptr]!
|
||
vmlal.u32 $A5xB,$Ni,${N2}[1]
|
||
vst1.64 {$A0xB-$A1xB}, [$toutptr,:256]!
|
||
vmlal.u32 $A6xB,$Ni,${N3}[0]
|
||
vmlal.u32 $A7xB,$Ni,${N3}[1]
|
||
vst1.64 {$A2xB-$A3xB}, [$toutptr,:256]!
|
||
|
||
vmull.u32 $A0xB,$Bi,${A0}[0]
|
||
vld1.32 {$N2-$N3}, [$nptr]!
|
||
vmull.u32 $A1xB,$Bi,${A0}[1]
|
||
vst1.64 {$A4xB-$A5xB}, [$toutptr,:256]!
|
||
vmull.u32 $A2xB,$Bi,${A1}[0]
|
||
vmull.u32 $A3xB,$Bi,${A1}[1]
|
||
vst1.64 {$A6xB-$A7xB}, [$toutptr,:256]!
|
||
|
||
vmull.u32 $A4xB,$Bi,${A2}[0]
|
||
vmull.u32 $A5xB,$Bi,${A2}[1]
|
||
vmull.u32 $A6xB,$Bi,${A3}[0]
|
||
vmull.u32 $A7xB,$Bi,${A3}[1]
|
||
|
||
bne .LNEON_1st
|
||
|
||
vmlal.u32 $A0xB,$Ni,${N0}[0]
|
||
add $tinptr,sp,#16
|
||
vmlal.u32 $A1xB,$Ni,${N0}[1]
|
||
sub $aptr,$aptr,$num,lsl#2 @ rewind $aptr
|
||
vmlal.u32 $A2xB,$Ni,${N1}[0]
|
||
vld1.64 {$Temp}, [sp,:128]
|
||
vmlal.u32 $A3xB,$Ni,${N1}[1]
|
||
sub $outer,$num,#1
|
||
|
||
vmlal.u32 $A4xB,$Ni,${N2}[0]
|
||
vst1.64 {$A0xB-$A1xB}, [$toutptr,:256]!
|
||
vmlal.u32 $A5xB,$Ni,${N2}[1]
|
||
vshr.u64 $temp,$temp,#16
|
||
vld1.64 {$A0xB}, [$tinptr, :128]!
|
||
vmlal.u32 $A6xB,$Ni,${N3}[0]
|
||
vst1.64 {$A2xB-$A3xB}, [$toutptr,:256]!
|
||
vmlal.u32 $A7xB,$Ni,${N3}[1]
|
||
|
||
vst1.64 {$A4xB-$A5xB}, [$toutptr,:256]!
|
||
vadd.u64 $temp,$temp,`&Dhi("$Temp")`
|
||
veor $Z,$Z,$Z
|
||
vst1.64 {$A6xB-$A7xB}, [$toutptr,:256]!
|
||
vld1.64 {$A1xB-$A2xB}, [$tinptr, :256]!
|
||
vst1.64 {$Z}, [$toutptr,:128]
|
||
vshr.u64 $temp,$temp,#16
|
||
|
||
b .LNEON_outer
|
||
|
||
.align 4
|
||
.LNEON_outer:
|
||
vld1.32 {${Bi}[0]}, [$bptr,:32]!
|
||
sub $nptr,$nptr,$num,lsl#2 @ rewind $nptr
|
||
vld1.32 {$A0-$A3}, [$aptr]!
|
||
veor $zero,$zero,$zero
|
||
mov $toutptr,sp
|
||
vzip.16 $Bi,$zero
|
||
sub $inner,$num,#8
|
||
vadd.u64 `&Dlo("$A0xB")`,`&Dlo("$A0xB")`,$temp
|
||
|
||
vmlal.u32 $A0xB,$Bi,${A0}[0]
|
||
vld1.64 {$A3xB-$A4xB},[$tinptr,:256]!
|
||
vmlal.u32 $A1xB,$Bi,${A0}[1]
|
||
vmlal.u32 $A2xB,$Bi,${A1}[0]
|
||
vld1.64 {$A5xB-$A6xB},[$tinptr,:256]!
|
||
vmlal.u32 $A3xB,$Bi,${A1}[1]
|
||
|
||
vshl.i64 $temp,`&Dhi("$A0xB")`,#16
|
||
veor $zero,$zero,$zero
|
||
vadd.u64 $temp,$temp,`&Dlo("$A0xB")`
|
||
vld1.64 {$A7xB},[$tinptr,:128]!
|
||
vmul.u32 $Ni,$temp,$M0
|
||
|
||
vmlal.u32 $A4xB,$Bi,${A2}[0]
|
||
vld1.32 {$N0-$N3}, [$nptr]!
|
||
vmlal.u32 $A5xB,$Bi,${A2}[1]
|
||
vmlal.u32 $A6xB,$Bi,${A3}[0]
|
||
vzip.16 $Ni,$zero
|
||
vmlal.u32 $A7xB,$Bi,${A3}[1]
|
||
|
||
.LNEON_inner:
|
||
vmlal.u32 $A0xB,$Ni,${N0}[0]
|
||
vld1.32 {$A0-$A3}, [$aptr]!
|
||
vmlal.u32 $A1xB,$Ni,${N0}[1]
|
||
subs $inner,$inner,#8
|
||
vmlal.u32 $A2xB,$Ni,${N1}[0]
|
||
vmlal.u32 $A3xB,$Ni,${N1}[1]
|
||
vst1.64 {$A0xB-$A1xB}, [$toutptr,:256]!
|
||
|
||
vmlal.u32 $A4xB,$Ni,${N2}[0]
|
||
vld1.64 {$A0xB}, [$tinptr, :128]!
|
||
vmlal.u32 $A5xB,$Ni,${N2}[1]
|
||
vst1.64 {$A2xB-$A3xB}, [$toutptr,:256]!
|
||
vmlal.u32 $A6xB,$Ni,${N3}[0]
|
||
vld1.64 {$A1xB-$A2xB}, [$tinptr, :256]!
|
||
vmlal.u32 $A7xB,$Ni,${N3}[1]
|
||
vst1.64 {$A4xB-$A5xB}, [$toutptr,:256]!
|
||
|
||
vmlal.u32 $A0xB,$Bi,${A0}[0]
|
||
vld1.64 {$A3xB-$A4xB}, [$tinptr, :256]!
|
||
vmlal.u32 $A1xB,$Bi,${A0}[1]
|
||
vst1.64 {$A6xB-$A7xB}, [$toutptr,:256]!
|
||
vmlal.u32 $A2xB,$Bi,${A1}[0]
|
||
vld1.64 {$A5xB-$A6xB}, [$tinptr, :256]!
|
||
vmlal.u32 $A3xB,$Bi,${A1}[1]
|
||
vld1.32 {$N0-$N3}, [$nptr]!
|
||
|
||
vmlal.u32 $A4xB,$Bi,${A2}[0]
|
||
vld1.64 {$A7xB}, [$tinptr, :128]!
|
||
vmlal.u32 $A5xB,$Bi,${A2}[1]
|
||
vmlal.u32 $A6xB,$Bi,${A3}[0]
|
||
vmlal.u32 $A7xB,$Bi,${A3}[1]
|
||
|
||
bne .LNEON_inner
|
||
|
||
vmlal.u32 $A0xB,$Ni,${N0}[0]
|
||
add $tinptr,sp,#16
|
||
vmlal.u32 $A1xB,$Ni,${N0}[1]
|
||
sub $aptr,$aptr,$num,lsl#2 @ rewind $aptr
|
||
vmlal.u32 $A2xB,$Ni,${N1}[0]
|
||
vld1.64 {$Temp}, [sp,:128]
|
||
vmlal.u32 $A3xB,$Ni,${N1}[1]
|
||
subs $outer,$outer,#1
|
||
|
||
vmlal.u32 $A4xB,$Ni,${N2}[0]
|
||
vst1.64 {$A0xB-$A1xB}, [$toutptr,:256]!
|
||
vmlal.u32 $A5xB,$Ni,${N2}[1]
|
||
vld1.64 {$A0xB}, [$tinptr, :128]!
|
||
vshr.u64 $temp,$temp,#16
|
||
vst1.64 {$A2xB-$A3xB}, [$toutptr,:256]!
|
||
vmlal.u32 $A6xB,$Ni,${N3}[0]
|
||
vld1.64 {$A1xB-$A2xB}, [$tinptr, :256]!
|
||
vmlal.u32 $A7xB,$Ni,${N3}[1]
|
||
|
||
vst1.64 {$A4xB-$A5xB}, [$toutptr,:256]!
|
||
vadd.u64 $temp,$temp,`&Dhi("$Temp")`
|
||
vst1.64 {$A6xB-$A7xB}, [$toutptr,:256]!
|
||
vshr.u64 $temp,$temp,#16
|
||
|
||
bne .LNEON_outer
|
||
|
||
mov $toutptr,sp
|
||
mov $inner,$num
|
||
|
||
.LNEON_tail:
|
||
vadd.u64 `&Dlo("$A0xB")`,`&Dlo("$A0xB")`,$temp
|
||
vld1.64 {$A3xB-$A4xB}, [$tinptr, :256]!
|
||
vshr.u64 $temp,`&Dlo("$A0xB")`,#16
|
||
vadd.u64 `&Dhi("$A0xB")`,`&Dhi("$A0xB")`,$temp
|
||
vld1.64 {$A5xB-$A6xB}, [$tinptr, :256]!
|
||
vshr.u64 $temp,`&Dhi("$A0xB")`,#16
|
||
vld1.64 {$A7xB}, [$tinptr, :128]!
|
||
vzip.16 `&Dlo("$A0xB")`,`&Dhi("$A0xB")`
|
||
|
||
.LNEON_tail2:
|
||
vadd.u64 `&Dlo("$A1xB")`,`&Dlo("$A1xB")`,$temp
|
||
vst1.32 {`&Dlo("$A0xB")`[0]}, [$toutptr, :32]!
|
||
vshr.u64 $temp,`&Dlo("$A1xB")`,#16
|
||
vadd.u64 `&Dhi("$A1xB")`,`&Dhi("$A1xB")`,$temp
|
||
vshr.u64 $temp,`&Dhi("$A1xB")`,#16
|
||
vzip.16 `&Dlo("$A1xB")`,`&Dhi("$A1xB")`
|
||
|
||
vadd.u64 `&Dlo("$A2xB")`,`&Dlo("$A2xB")`,$temp
|
||
vst1.32 {`&Dlo("$A1xB")`[0]}, [$toutptr, :32]!
|
||
vshr.u64 $temp,`&Dlo("$A2xB")`,#16
|
||
vadd.u64 `&Dhi("$A2xB")`,`&Dhi("$A2xB")`,$temp
|
||
vshr.u64 $temp,`&Dhi("$A2xB")`,#16
|
||
vzip.16 `&Dlo("$A2xB")`,`&Dhi("$A2xB")`
|
||
|
||
vadd.u64 `&Dlo("$A3xB")`,`&Dlo("$A3xB")`,$temp
|
||
vst1.32 {`&Dlo("$A2xB")`[0]}, [$toutptr, :32]!
|
||
vshr.u64 $temp,`&Dlo("$A3xB")`,#16
|
||
vadd.u64 `&Dhi("$A3xB")`,`&Dhi("$A3xB")`,$temp
|
||
vshr.u64 $temp,`&Dhi("$A3xB")`,#16
|
||
vzip.16 `&Dlo("$A3xB")`,`&Dhi("$A3xB")`
|
||
|
||
vadd.u64 `&Dlo("$A4xB")`,`&Dlo("$A4xB")`,$temp
|
||
vst1.32 {`&Dlo("$A3xB")`[0]}, [$toutptr, :32]!
|
||
vshr.u64 $temp,`&Dlo("$A4xB")`,#16
|
||
vadd.u64 `&Dhi("$A4xB")`,`&Dhi("$A4xB")`,$temp
|
||
vshr.u64 $temp,`&Dhi("$A4xB")`,#16
|
||
vzip.16 `&Dlo("$A4xB")`,`&Dhi("$A4xB")`
|
||
|
||
vadd.u64 `&Dlo("$A5xB")`,`&Dlo("$A5xB")`,$temp
|
||
vst1.32 {`&Dlo("$A4xB")`[0]}, [$toutptr, :32]!
|
||
vshr.u64 $temp,`&Dlo("$A5xB")`,#16
|
||
vadd.u64 `&Dhi("$A5xB")`,`&Dhi("$A5xB")`,$temp
|
||
vshr.u64 $temp,`&Dhi("$A5xB")`,#16
|
||
vzip.16 `&Dlo("$A5xB")`,`&Dhi("$A5xB")`
|
||
|
||
vadd.u64 `&Dlo("$A6xB")`,`&Dlo("$A6xB")`,$temp
|
||
vst1.32 {`&Dlo("$A5xB")`[0]}, [$toutptr, :32]!
|
||
vshr.u64 $temp,`&Dlo("$A6xB")`,#16
|
||
vadd.u64 `&Dhi("$A6xB")`,`&Dhi("$A6xB")`,$temp
|
||
vld1.64 {$A0xB}, [$tinptr, :128]!
|
||
vshr.u64 $temp,`&Dhi("$A6xB")`,#16
|
||
vzip.16 `&Dlo("$A6xB")`,`&Dhi("$A6xB")`
|
||
|
||
vadd.u64 `&Dlo("$A7xB")`,`&Dlo("$A7xB")`,$temp
|
||
vst1.32 {`&Dlo("$A6xB")`[0]}, [$toutptr, :32]!
|
||
vshr.u64 $temp,`&Dlo("$A7xB")`,#16
|
||
vadd.u64 `&Dhi("$A7xB")`,`&Dhi("$A7xB")`,$temp
|
||
vld1.64 {$A1xB-$A2xB}, [$tinptr, :256]!
|
||
vshr.u64 $temp,`&Dhi("$A7xB")`,#16
|
||
vzip.16 `&Dlo("$A7xB")`,`&Dhi("$A7xB")`
|
||
subs $inner,$inner,#8
|
||
vst1.32 {`&Dlo("$A7xB")`[0]}, [$toutptr, :32]!
|
||
|
||
bne .LNEON_tail
|
||
|
||
vst1.32 {${temp}[0]}, [$toutptr, :32] @ top-most bit
|
||
sub $nptr,$nptr,$num,lsl#2 @ rewind $nptr
|
||
subs $aptr,sp,#0 @ clear carry flag
|
||
add $bptr,sp,$num,lsl#2
|
||
|
||
.LNEON_sub:
|
||
ldmia $aptr!, {r4-r7}
|
||
ldmia $nptr!, {r8-r11}
|
||
sbcs r8, r4,r8
|
||
sbcs r9, r5,r9
|
||
sbcs r10,r6,r10
|
||
sbcs r11,r7,r11
|
||
teq $aptr,$bptr @ preserves carry
|
||
stmia $rptr!, {r8-r11}
|
||
bne .LNEON_sub
|
||
|
||
ldr r10, [$aptr] @ load top-most bit
|
||
veor q0,q0,q0
|
||
sub r11,$bptr,sp @ this is num*4
|
||
veor q1,q1,q1
|
||
mov $aptr,sp
|
||
sub $rptr,$rptr,r11 @ rewind $rptr
|
||
mov $nptr,$bptr @ second 3/4th of frame
|
||
sbcs r10,r10,#0 @ result is carry flag
|
||
|
||
.LNEON_copy_n_zap:
|
||
ldmia $aptr!, {r4-r7}
|
||
ldmia $rptr, {r8-r11}
|
||
movcc r8, r4
|
||
vst1.64 {q0-q1}, [$nptr,:256]! @ wipe
|
||
movcc r9, r5
|
||
movcc r10,r6
|
||
vst1.64 {q0-q1}, [$nptr,:256]! @ wipe
|
||
movcc r11,r7
|
||
ldmia $aptr, {r4-r7}
|
||
stmia $rptr!, {r8-r11}
|
||
sub $aptr,$aptr,#16
|
||
ldmia $rptr, {r8-r11}
|
||
movcc r8, r4
|
||
vst1.64 {q0-q1}, [$aptr,:256]! @ wipe
|
||
movcc r9, r5
|
||
movcc r10,r6
|
||
vst1.64 {q0-q1}, [$nptr,:256]! @ wipe
|
||
movcc r11,r7
|
||
teq $aptr,$bptr @ preserves carry
|
||
stmia $rptr!, {r8-r11}
|
||
bne .LNEON_copy_n_zap
|
||
|
||
sub sp,ip,#96
|
||
vldmia sp!,{d8-d15}
|
||
ldmia sp!,{r4-r11}
|
||
ret @ bx lr
|
||
.size bn_mul8x_mont_neon,.-bn_mul8x_mont_neon
|
||
#endif
|
||
___
|
||
}
|
||
$code.=<<___;
|
||
.asciz "Montgomery multiplication for ARMv4/NEON, CRYPTOGAMS by <appro\@openssl.org>"
|
||
.align 2
|
||
#if __ARM_MAX_ARCH__>=7
|
||
.comm OPENSSL_armcap_P,4,4
|
||
.hidden OPENSSL_armcap_P
|
||
#endif
|
||
___
|
||
|
||
$code =~ s/\`([^\`]*)\`/eval $1/gem;
|
||
$code =~ s/\bbx\s+lr\b/.word\t0xe12fff1e/gm; # make it possible to compile with -march=armv4
|
||
$code =~ s/\bret\b/bx lr/gm;
|
||
print $code;
|
||
close STDOUT;
|