74f79b601d
ARM has optimized Cortex-A5x pipeline to favour pairs of complementary AES instructions. While modified code improves performance of post-r0p0 Cortex-A53 performance by >40% (for CBC decrypt and CTR), it hurts original r0p0. We favour later revisions, because one can't prevent future from coming. Improvement on post-r0p0 Cortex-A57 exceeds 50%, while new code is not slower on r0p0, or Apple A7 for that matter. [Update even SHA results for latest Cortex-A53.] (Imported from upstream's 94376cccb4ed5b376220bffe0739140ea9dad8c8) Change-Id: I581c65b566116b1f4211fb1bd5a1a54479889d70 Reviewed-on: https://boringssl-review.googlesource.com/4481 Reviewed-by: Adam Langley <agl@google.com> |
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aes-586.pl | ||
aes-armv4.pl | ||
aes-x86_64.pl | ||
aesni-x86_64.pl | ||
aesni-x86.pl | ||
aesv8-armx.pl | ||
bsaes-armv7.pl | ||
bsaes-x86_64.pl | ||
vpaes-x86_64.pl | ||
vpaes-x86.pl |