8da59555c6
(Imported from upstream's a285992763f3961f69a8d86bf7dfff020a08cef9.) Change-Id: I59df0b567e8e80befe5c399f817d6410ddafc577 Reviewed-on: https://boringssl-review.googlesource.com/17110 Reviewed-by: Adam Langley <agl@google.com>
546 lines
14 KiB
Prolog
546 lines
14 KiB
Prolog
#!/usr/bin/env perl
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#
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# ====================================================================
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# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
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# project. The module is, however, dual licensed under OpenSSL and
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# CRYPTOGAMS licenses depending on where you obtain it. For further
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# details see http://www.openssl.org/~appro/cryptogams/.
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# ====================================================================
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#
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# April 2010
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#
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# The module implements "4-bit" GCM GHASH function and underlying
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# single multiplication operation in GF(2^128). "4-bit" means that it
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# uses 256 bytes per-key table [+32 bytes shared table]. There is no
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# experimental performance data available yet. The only approximation
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# that can be made at this point is based on code size. Inner loop is
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# 32 instructions long and on single-issue core should execute in <40
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# cycles. Having verified that gcc 3.4 didn't unroll corresponding
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# loop, this assembler loop body was found to be ~3x smaller than
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# compiler-generated one...
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#
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# July 2010
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#
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# Rescheduling for dual-issue pipeline resulted in 8.5% improvement on
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# Cortex A8 core and ~25 cycles per processed byte (which was observed
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# to be ~3 times faster than gcc-generated code:-)
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#
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# February 2011
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#
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# Profiler-assisted and platform-specific optimization resulted in 7%
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# improvement on Cortex A8 core and ~23.5 cycles per byte.
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#
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# March 2011
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#
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# Add NEON implementation featuring polynomial multiplication, i.e. no
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# lookup tables involved. On Cortex A8 it was measured to process one
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# byte in 15 cycles or 55% faster than integer-only code.
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#
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# April 2014
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#
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# Switch to multiplication algorithm suggested in paper referred
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# below and combine it with reduction algorithm from x86 module.
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# Performance improvement over previous version varies from 65% on
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# Snapdragon S4 to 110% on Cortex A9. In absolute terms Cortex A8
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# processes one byte in 8.45 cycles, A9 - in 10.2, A15 - in 7.63,
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# Snapdragon S4 - in 9.33.
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#
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# Câmara, D.; Gouvêa, C. P. L.; López, J. & Dahab, R.: Fast Software
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# Polynomial Multiplication on ARM Processors using the NEON Engine.
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#
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# http://conradoplg.cryptoland.net/files/2010/12/mocrysen13.pdf
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# ====================================================================
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# Note about "528B" variant. In ARM case it makes lesser sense to
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# implement it for following reasons:
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#
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# - performance improvement won't be anywhere near 50%, because 128-
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# bit shift operation is neatly fused with 128-bit xor here, and
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# "538B" variant would eliminate only 4-5 instructions out of 32
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# in the inner loop (meaning that estimated improvement is ~15%);
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# - ARM-based systems are often embedded ones and extra memory
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# consumption might be unappreciated (for so little improvement);
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#
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# Byte order [in]dependence. =========================================
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#
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# Caller is expected to maintain specific *dword* order in Htable,
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# namely with *least* significant dword of 128-bit value at *lower*
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# address. This differs completely from C code and has everything to
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# do with ldm instruction and order in which dwords are "consumed" by
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# algorithm. *Byte* order within these dwords in turn is whatever
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# *native* byte order on current platform. See gcm128.c for working
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# example...
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$flavour = shift;
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if ($flavour=~/\w[\w\-]*\.\w+$/) { $output=$flavour; undef $flavour; }
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else { while (($output=shift) && ($output!~/\w[\w\-]*\.\w+$/)) {} }
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if ($flavour && $flavour ne "void") {
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$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
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( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or
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( $xlate="${dir}../../../perlasm/arm-xlate.pl" and -f $xlate) or
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die "can't locate arm-xlate.pl";
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open STDOUT,"| \"$^X\" $xlate $flavour $output";
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} else {
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open STDOUT,">$output";
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}
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$Xi="r0"; # argument block
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$Htbl="r1";
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$inp="r2";
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$len="r3";
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$Zll="r4"; # variables
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$Zlh="r5";
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$Zhl="r6";
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$Zhh="r7";
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$Tll="r8";
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$Tlh="r9";
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$Thl="r10";
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$Thh="r11";
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$nlo="r12";
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################# r13 is stack pointer
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$nhi="r14";
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################# r15 is program counter
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$rem_4bit=$inp; # used in gcm_gmult_4bit
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$cnt=$len;
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sub Zsmash() {
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my $i=12;
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my @args=@_;
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for ($Zll,$Zlh,$Zhl,$Zhh) {
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$code.=<<___;
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#if __ARM_ARCH__>=7 && defined(__ARMEL__)
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rev $_,$_
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str $_,[$Xi,#$i]
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#elif defined(__ARMEB__)
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str $_,[$Xi,#$i]
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#else
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mov $Tlh,$_,lsr#8
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strb $_,[$Xi,#$i+3]
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mov $Thl,$_,lsr#16
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strb $Tlh,[$Xi,#$i+2]
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mov $Thh,$_,lsr#24
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strb $Thl,[$Xi,#$i+1]
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strb $Thh,[$Xi,#$i]
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#endif
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___
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$code.="\t".shift(@args)."\n";
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$i-=4;
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}
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}
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$code=<<___;
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#include <openssl/arm_arch.h>
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.text
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#if defined(__thumb2__)
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.syntax unified
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.thumb
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#else
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.code 32
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#endif
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#ifdef __clang__
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#define ldrplb ldrbpl
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#define ldrneb ldrbne
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#endif
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.type rem_4bit,%object
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.align 5
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rem_4bit:
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.short 0x0000,0x1C20,0x3840,0x2460
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.short 0x7080,0x6CA0,0x48C0,0x54E0
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.short 0xE100,0xFD20,0xD940,0xC560
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.short 0x9180,0x8DA0,0xA9C0,0xB5E0
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.size rem_4bit,.-rem_4bit
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.type rem_4bit_get,%function
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rem_4bit_get:
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#if defined(__thumb2__)
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adr $rem_4bit,rem_4bit
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#else
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sub $rem_4bit,pc,#8+32 @ &rem_4bit
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#endif
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b .Lrem_4bit_got
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nop
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nop
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.size rem_4bit_get,.-rem_4bit_get
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.global gcm_ghash_4bit
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.type gcm_ghash_4bit,%function
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.align 4
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gcm_ghash_4bit:
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#if defined(__thumb2__)
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adr r12,rem_4bit
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#else
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sub r12,pc,#8+48 @ &rem_4bit
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#endif
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add $len,$inp,$len @ $len to point at the end
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stmdb sp!,{r3-r11,lr} @ save $len/end too
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ldmia r12,{r4-r11} @ copy rem_4bit ...
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stmdb sp!,{r4-r11} @ ... to stack
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ldrb $nlo,[$inp,#15]
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ldrb $nhi,[$Xi,#15]
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.Louter:
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eor $nlo,$nlo,$nhi
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and $nhi,$nlo,#0xf0
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and $nlo,$nlo,#0x0f
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mov $cnt,#14
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add $Zhh,$Htbl,$nlo,lsl#4
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ldmia $Zhh,{$Zll-$Zhh} @ load Htbl[nlo]
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add $Thh,$Htbl,$nhi
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ldrb $nlo,[$inp,#14]
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and $nhi,$Zll,#0xf @ rem
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ldmia $Thh,{$Tll-$Thh} @ load Htbl[nhi]
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add $nhi,$nhi,$nhi
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eor $Zll,$Tll,$Zll,lsr#4
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ldrh $Tll,[sp,$nhi] @ rem_4bit[rem]
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eor $Zll,$Zll,$Zlh,lsl#28
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ldrb $nhi,[$Xi,#14]
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eor $Zlh,$Tlh,$Zlh,lsr#4
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eor $Zlh,$Zlh,$Zhl,lsl#28
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eor $Zhl,$Thl,$Zhl,lsr#4
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eor $Zhl,$Zhl,$Zhh,lsl#28
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eor $Zhh,$Thh,$Zhh,lsr#4
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eor $nlo,$nlo,$nhi
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and $nhi,$nlo,#0xf0
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and $nlo,$nlo,#0x0f
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eor $Zhh,$Zhh,$Tll,lsl#16
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.Linner:
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add $Thh,$Htbl,$nlo,lsl#4
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and $nlo,$Zll,#0xf @ rem
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subs $cnt,$cnt,#1
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add $nlo,$nlo,$nlo
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ldmia $Thh,{$Tll-$Thh} @ load Htbl[nlo]
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eor $Zll,$Tll,$Zll,lsr#4
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eor $Zll,$Zll,$Zlh,lsl#28
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eor $Zlh,$Tlh,$Zlh,lsr#4
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eor $Zlh,$Zlh,$Zhl,lsl#28
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ldrh $Tll,[sp,$nlo] @ rem_4bit[rem]
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eor $Zhl,$Thl,$Zhl,lsr#4
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#ifdef __thumb2__
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it pl
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#endif
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ldrplb $nlo,[$inp,$cnt]
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eor $Zhl,$Zhl,$Zhh,lsl#28
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eor $Zhh,$Thh,$Zhh,lsr#4
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add $Thh,$Htbl,$nhi
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and $nhi,$Zll,#0xf @ rem
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eor $Zhh,$Zhh,$Tll,lsl#16 @ ^= rem_4bit[rem]
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add $nhi,$nhi,$nhi
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ldmia $Thh,{$Tll-$Thh} @ load Htbl[nhi]
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eor $Zll,$Tll,$Zll,lsr#4
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#ifdef __thumb2__
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it pl
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#endif
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ldrplb $Tll,[$Xi,$cnt]
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eor $Zll,$Zll,$Zlh,lsl#28
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eor $Zlh,$Tlh,$Zlh,lsr#4
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ldrh $Tlh,[sp,$nhi]
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eor $Zlh,$Zlh,$Zhl,lsl#28
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eor $Zhl,$Thl,$Zhl,lsr#4
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eor $Zhl,$Zhl,$Zhh,lsl#28
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#ifdef __thumb2__
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it pl
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#endif
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eorpl $nlo,$nlo,$Tll
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eor $Zhh,$Thh,$Zhh,lsr#4
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#ifdef __thumb2__
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itt pl
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#endif
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andpl $nhi,$nlo,#0xf0
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andpl $nlo,$nlo,#0x0f
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eor $Zhh,$Zhh,$Tlh,lsl#16 @ ^= rem_4bit[rem]
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bpl .Linner
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ldr $len,[sp,#32] @ re-load $len/end
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add $inp,$inp,#16
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mov $nhi,$Zll
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___
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&Zsmash("cmp\t$inp,$len","\n".
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"#ifdef __thumb2__\n".
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" it ne\n".
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"#endif\n".
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" ldrneb $nlo,[$inp,#15]");
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$code.=<<___;
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bne .Louter
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add sp,sp,#36
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#if __ARM_ARCH__>=5
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ldmia sp!,{r4-r11,pc}
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#else
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ldmia sp!,{r4-r11,lr}
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tst lr,#1
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moveq pc,lr @ be binary compatible with V4, yet
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bx lr @ interoperable with Thumb ISA:-)
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#endif
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.size gcm_ghash_4bit,.-gcm_ghash_4bit
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.global gcm_gmult_4bit
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.type gcm_gmult_4bit,%function
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gcm_gmult_4bit:
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stmdb sp!,{r4-r11,lr}
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ldrb $nlo,[$Xi,#15]
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b rem_4bit_get
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.Lrem_4bit_got:
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and $nhi,$nlo,#0xf0
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and $nlo,$nlo,#0x0f
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mov $cnt,#14
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add $Zhh,$Htbl,$nlo,lsl#4
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ldmia $Zhh,{$Zll-$Zhh} @ load Htbl[nlo]
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ldrb $nlo,[$Xi,#14]
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add $Thh,$Htbl,$nhi
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and $nhi,$Zll,#0xf @ rem
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ldmia $Thh,{$Tll-$Thh} @ load Htbl[nhi]
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add $nhi,$nhi,$nhi
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eor $Zll,$Tll,$Zll,lsr#4
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ldrh $Tll,[$rem_4bit,$nhi] @ rem_4bit[rem]
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eor $Zll,$Zll,$Zlh,lsl#28
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eor $Zlh,$Tlh,$Zlh,lsr#4
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eor $Zlh,$Zlh,$Zhl,lsl#28
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eor $Zhl,$Thl,$Zhl,lsr#4
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eor $Zhl,$Zhl,$Zhh,lsl#28
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eor $Zhh,$Thh,$Zhh,lsr#4
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and $nhi,$nlo,#0xf0
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eor $Zhh,$Zhh,$Tll,lsl#16
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and $nlo,$nlo,#0x0f
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.Loop:
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add $Thh,$Htbl,$nlo,lsl#4
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and $nlo,$Zll,#0xf @ rem
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subs $cnt,$cnt,#1
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add $nlo,$nlo,$nlo
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ldmia $Thh,{$Tll-$Thh} @ load Htbl[nlo]
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eor $Zll,$Tll,$Zll,lsr#4
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eor $Zll,$Zll,$Zlh,lsl#28
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eor $Zlh,$Tlh,$Zlh,lsr#4
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eor $Zlh,$Zlh,$Zhl,lsl#28
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ldrh $Tll,[$rem_4bit,$nlo] @ rem_4bit[rem]
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eor $Zhl,$Thl,$Zhl,lsr#4
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#ifdef __thumb2__
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it pl
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#endif
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ldrplb $nlo,[$Xi,$cnt]
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eor $Zhl,$Zhl,$Zhh,lsl#28
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eor $Zhh,$Thh,$Zhh,lsr#4
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add $Thh,$Htbl,$nhi
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and $nhi,$Zll,#0xf @ rem
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eor $Zhh,$Zhh,$Tll,lsl#16 @ ^= rem_4bit[rem]
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add $nhi,$nhi,$nhi
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ldmia $Thh,{$Tll-$Thh} @ load Htbl[nhi]
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eor $Zll,$Tll,$Zll,lsr#4
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eor $Zll,$Zll,$Zlh,lsl#28
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eor $Zlh,$Tlh,$Zlh,lsr#4
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ldrh $Tll,[$rem_4bit,$nhi] @ rem_4bit[rem]
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eor $Zlh,$Zlh,$Zhl,lsl#28
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eor $Zhl,$Thl,$Zhl,lsr#4
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eor $Zhl,$Zhl,$Zhh,lsl#28
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eor $Zhh,$Thh,$Zhh,lsr#4
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#ifdef __thumb2__
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itt pl
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#endif
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andpl $nhi,$nlo,#0xf0
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andpl $nlo,$nlo,#0x0f
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eor $Zhh,$Zhh,$Tll,lsl#16 @ ^= rem_4bit[rem]
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bpl .Loop
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___
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&Zsmash();
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$code.=<<___;
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#if __ARM_ARCH__>=5
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ldmia sp!,{r4-r11,pc}
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#else
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ldmia sp!,{r4-r11,lr}
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tst lr,#1
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moveq pc,lr @ be binary compatible with V4, yet
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bx lr @ interoperable with Thumb ISA:-)
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#endif
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.size gcm_gmult_4bit,.-gcm_gmult_4bit
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___
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{
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my ($Xl,$Xm,$Xh,$IN)=map("q$_",(0..3));
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my ($t0,$t1,$t2,$t3)=map("q$_",(8..12));
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my ($Hlo,$Hhi,$Hhl,$k48,$k32,$k16)=map("d$_",(26..31));
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sub clmul64x64 {
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my ($r,$a,$b)=@_;
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$code.=<<___;
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vext.8 $t0#lo, $a, $a, #1 @ A1
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vmull.p8 $t0, $t0#lo, $b @ F = A1*B
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vext.8 $r#lo, $b, $b, #1 @ B1
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vmull.p8 $r, $a, $r#lo @ E = A*B1
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vext.8 $t1#lo, $a, $a, #2 @ A2
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vmull.p8 $t1, $t1#lo, $b @ H = A2*B
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vext.8 $t3#lo, $b, $b, #2 @ B2
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vmull.p8 $t3, $a, $t3#lo @ G = A*B2
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vext.8 $t2#lo, $a, $a, #3 @ A3
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veor $t0, $t0, $r @ L = E + F
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vmull.p8 $t2, $t2#lo, $b @ J = A3*B
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vext.8 $r#lo, $b, $b, #3 @ B3
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veor $t1, $t1, $t3 @ M = G + H
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vmull.p8 $r, $a, $r#lo @ I = A*B3
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veor $t0#lo, $t0#lo, $t0#hi @ t0 = (L) (P0 + P1) << 8
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vand $t0#hi, $t0#hi, $k48
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vext.8 $t3#lo, $b, $b, #4 @ B4
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veor $t1#lo, $t1#lo, $t1#hi @ t1 = (M) (P2 + P3) << 16
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vand $t1#hi, $t1#hi, $k32
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vmull.p8 $t3, $a, $t3#lo @ K = A*B4
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veor $t2, $t2, $r @ N = I + J
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veor $t0#lo, $t0#lo, $t0#hi
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veor $t1#lo, $t1#lo, $t1#hi
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veor $t2#lo, $t2#lo, $t2#hi @ t2 = (N) (P4 + P5) << 24
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vand $t2#hi, $t2#hi, $k16
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vext.8 $t0, $t0, $t0, #15
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veor $t3#lo, $t3#lo, $t3#hi @ t3 = (K) (P6 + P7) << 32
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vmov.i64 $t3#hi, #0
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vext.8 $t1, $t1, $t1, #14
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veor $t2#lo, $t2#lo, $t2#hi
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vmull.p8 $r, $a, $b @ D = A*B
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vext.8 $t3, $t3, $t3, #12
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vext.8 $t2, $t2, $t2, #13
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veor $t0, $t0, $t1
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veor $t2, $t2, $t3
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veor $r, $r, $t0
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veor $r, $r, $t2
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___
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}
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$code.=<<___;
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#if __ARM_MAX_ARCH__>=7
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.arch armv7-a
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.fpu neon
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.global gcm_init_neon
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.type gcm_init_neon,%function
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.align 4
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gcm_init_neon:
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vld1.64 $IN#hi,[r1]! @ load H
|
|
vmov.i8 $t0,#0xe1
|
|
vld1.64 $IN#lo,[r1]
|
|
vshl.i64 $t0#hi,#57
|
|
vshr.u64 $t0#lo,#63 @ t0=0xc2....01
|
|
vdup.8 $t1,$IN#hi[7]
|
|
vshr.u64 $Hlo,$IN#lo,#63
|
|
vshr.s8 $t1,#7 @ broadcast carry bit
|
|
vshl.i64 $IN,$IN,#1
|
|
vand $t0,$t0,$t1
|
|
vorr $IN#hi,$Hlo @ H<<<=1
|
|
veor $IN,$IN,$t0 @ twisted H
|
|
vstmia r0,{$IN}
|
|
|
|
ret @ bx lr
|
|
.size gcm_init_neon,.-gcm_init_neon
|
|
|
|
.global gcm_gmult_neon
|
|
.type gcm_gmult_neon,%function
|
|
.align 4
|
|
gcm_gmult_neon:
|
|
vld1.64 $IN#hi,[$Xi]! @ load Xi
|
|
vld1.64 $IN#lo,[$Xi]!
|
|
vmov.i64 $k48,#0x0000ffffffffffff
|
|
vldmia $Htbl,{$Hlo-$Hhi} @ load twisted H
|
|
vmov.i64 $k32,#0x00000000ffffffff
|
|
#ifdef __ARMEL__
|
|
vrev64.8 $IN,$IN
|
|
#endif
|
|
vmov.i64 $k16,#0x000000000000ffff
|
|
veor $Hhl,$Hlo,$Hhi @ Karatsuba pre-processing
|
|
mov $len,#16
|
|
b .Lgmult_neon
|
|
.size gcm_gmult_neon,.-gcm_gmult_neon
|
|
|
|
.global gcm_ghash_neon
|
|
.type gcm_ghash_neon,%function
|
|
.align 4
|
|
gcm_ghash_neon:
|
|
vld1.64 $Xl#hi,[$Xi]! @ load Xi
|
|
vld1.64 $Xl#lo,[$Xi]!
|
|
vmov.i64 $k48,#0x0000ffffffffffff
|
|
vldmia $Htbl,{$Hlo-$Hhi} @ load twisted H
|
|
vmov.i64 $k32,#0x00000000ffffffff
|
|
#ifdef __ARMEL__
|
|
vrev64.8 $Xl,$Xl
|
|
#endif
|
|
vmov.i64 $k16,#0x000000000000ffff
|
|
veor $Hhl,$Hlo,$Hhi @ Karatsuba pre-processing
|
|
|
|
.Loop_neon:
|
|
vld1.64 $IN#hi,[$inp]! @ load inp
|
|
vld1.64 $IN#lo,[$inp]!
|
|
#ifdef __ARMEL__
|
|
vrev64.8 $IN,$IN
|
|
#endif
|
|
veor $IN,$Xl @ inp^=Xi
|
|
.Lgmult_neon:
|
|
___
|
|
&clmul64x64 ($Xl,$Hlo,"$IN#lo"); # H.lo·Xi.lo
|
|
$code.=<<___;
|
|
veor $IN#lo,$IN#lo,$IN#hi @ Karatsuba pre-processing
|
|
___
|
|
&clmul64x64 ($Xm,$Hhl,"$IN#lo"); # (H.lo+H.hi)·(Xi.lo+Xi.hi)
|
|
&clmul64x64 ($Xh,$Hhi,"$IN#hi"); # H.hi·Xi.hi
|
|
$code.=<<___;
|
|
veor $Xm,$Xm,$Xl @ Karatsuba post-processing
|
|
veor $Xm,$Xm,$Xh
|
|
veor $Xl#hi,$Xl#hi,$Xm#lo
|
|
veor $Xh#lo,$Xh#lo,$Xm#hi @ Xh|Xl - 256-bit result
|
|
|
|
@ equivalent of reduction_avx from ghash-x86_64.pl
|
|
vshl.i64 $t1,$Xl,#57 @ 1st phase
|
|
vshl.i64 $t2,$Xl,#62
|
|
veor $t2,$t2,$t1 @
|
|
vshl.i64 $t1,$Xl,#63
|
|
veor $t2, $t2, $t1 @
|
|
veor $Xl#hi,$Xl#hi,$t2#lo @
|
|
veor $Xh#lo,$Xh#lo,$t2#hi
|
|
|
|
vshr.u64 $t2,$Xl,#1 @ 2nd phase
|
|
veor $Xh,$Xh,$Xl
|
|
veor $Xl,$Xl,$t2 @
|
|
vshr.u64 $t2,$t2,#6
|
|
vshr.u64 $Xl,$Xl,#1 @
|
|
veor $Xl,$Xl,$Xh @
|
|
veor $Xl,$Xl,$t2 @
|
|
|
|
subs $len,#16
|
|
bne .Loop_neon
|
|
|
|
#ifdef __ARMEL__
|
|
vrev64.8 $Xl,$Xl
|
|
#endif
|
|
sub $Xi,#16
|
|
vst1.64 $Xl#hi,[$Xi]! @ write out Xi
|
|
vst1.64 $Xl#lo,[$Xi]
|
|
|
|
ret @ bx lr
|
|
.size gcm_ghash_neon,.-gcm_ghash_neon
|
|
#endif
|
|
___
|
|
}
|
|
$code.=<<___;
|
|
.asciz "GHASH for ARMv4/NEON, CRYPTOGAMS by <appro\@openssl.org>"
|
|
.align 2
|
|
___
|
|
|
|
foreach (split("\n",$code)) {
|
|
s/\`([^\`]*)\`/eval $1/geo;
|
|
|
|
s/\bq([0-9]+)#(lo|hi)/sprintf "d%d",2*$1+($2 eq "hi")/geo or
|
|
s/\bret\b/bx lr/go or
|
|
s/\bbx\s+lr\b/.word\t0xe12fff1e/go; # make it possible to compile with -march=armv4
|
|
|
|
print $_,"\n";
|
|
}
|
|
close STDOUT; # enforce flush
|