4467e59bc8
This change adds AES and GHASH assembly from upstream, with the aim of speeding up AES-GCM. The PPC64LE assembly matches the interface of the ARMv8 assembly so I've changed the prefix of both sets of asm functions to be the same ("aes_hw_"). Otherwise, the new assmebly files and Perlasm match exactly those from upstream's c536b6be1a (from their master branch). Before: Did 1879000 AES-128-GCM (16 bytes) seal operations in 1000428us (1878196.1 ops/sec): 30.1 MB/s Did 61000 AES-128-GCM (1350 bytes) seal operations in 1006660us (60596.4 ops/sec): 81.8 MB/s Did 11000 AES-128-GCM (8192 bytes) seal operations in 1072649us (10255.0 ops/sec): 84.0 MB/s Did 1665000 AES-256-GCM (16 bytes) seal operations in 1000591us (1664016.6 ops/sec): 26.6 MB/s Did 52000 AES-256-GCM (1350 bytes) seal operations in 1006971us (51640.0 ops/sec): 69.7 MB/s Did 8840 AES-256-GCM (8192 bytes) seal operations in 1013294us (8724.0 ops/sec): 71.5 MB/s After: Did 4994000 AES-128-GCM (16 bytes) seal operations in 1000017us (4993915.1 ops/sec): 79.9 MB/s Did 1389000 AES-128-GCM (1350 bytes) seal operations in 1000073us (1388898.6 ops/sec): 1875.0 MB/s Did 319000 AES-128-GCM (8192 bytes) seal operations in 1000101us (318967.8 ops/sec): 2613.0 MB/s Did 4668000 AES-256-GCM (16 bytes) seal operations in 1000149us (4667304.6 ops/sec): 74.7 MB/s Did 1202000 AES-256-GCM (1350 bytes) seal operations in 1000646us (1201224.0 ops/sec): 1621.7 MB/s Did 269000 AES-256-GCM (8192 bytes) seal operations in 1002804us (268247.8 ops/sec): 2197.5 MB/s Change-Id: Id848562bd4e1aa79a4683012501dfa5e6c08cfcc Reviewed-on: https://boringssl-review.googlesource.com/11262 Reviewed-by: Adam Langley <agl@google.com> Commit-Queue: Adam Langley <agl@google.com> CQ-Verified: CQ bot account: commit-bot@chromium.org <commit-bot@chromium.org>
182 lines
6.6 KiB
C
182 lines
6.6 KiB
C
/* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
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* All rights reserved.
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*
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* This package is an SSL implementation written
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* by Eric Young (eay@cryptsoft.com).
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* The implementation was written so as to conform with Netscapes SSL.
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*
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* This library is free for commercial and non-commercial use as long as
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* the following conditions are aheared to. The following conditions
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* apply to all code found in this distribution, be it the RC4, RSA,
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* lhash, DES, etc., code; not just the SSL code. The SSL documentation
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* included with this distribution is covered by the same copyright terms
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* except that the holder is Tim Hudson (tjh@cryptsoft.com).
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*
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* Copyright remains Eric Young's, and as such any Copyright notices in
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* the code are not to be removed.
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* If this package is used in a product, Eric Young should be given attribution
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* as the author of the parts of the library used.
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* This can be in the form of a textual message at program startup or
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* in documentation (online or textual) provided with the package.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* "This product includes cryptographic software written by
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* Eric Young (eay@cryptsoft.com)"
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* The word 'cryptographic' can be left out if the rouines from the library
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* being used are not cryptographic related :-).
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* 4. If you include any Windows specific code (or a derivative thereof) from
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* the apps directory (application code) you must include an acknowledgement:
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* "This product includes software written by Tim Hudson (tjh@cryptsoft.com)"
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*
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* THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* The licence and distribution terms for any publically available version or
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* derivative of this code cannot be changed. i.e. this code cannot simply be
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* copied and put under another distribution licence
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* [including the GNU Public Licence.]
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*
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* This product includes cryptographic software written by Eric Young
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* (eay@cryptsoft.com). This product includes software written by Tim
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* Hudson (tjh@cryptsoft.com). */
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#ifndef OPENSSL_HEADER_CPU_H
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#define OPENSSL_HEADER_CPU_H
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#include <openssl/base.h>
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/* Runtime CPU feature support */
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#if defined(OPENSSL_X86) || defined(OPENSSL_X86_64)
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/* OPENSSL_ia32cap_P contains the Intel CPUID bits when running on an x86 or
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* x86-64 system.
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*
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* Index 0:
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* EDX for CPUID where EAX = 1
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* Bit 20 is always zero
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* Bit 28 is adjusted to reflect whether the data cache is shared between
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* multiple logical cores
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* Bit 30 is used to indicate an Intel CPU
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* Index 1:
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* ECX for CPUID where EAX = 1
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* Bit 11 is used to indicate AMD XOP support, not SDBG
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* Index 2:
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* EBX for CPUID where EAX = 7
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* Index 3 is set to zero.
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*
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* Note: the CPUID bits are pre-adjusted for the OSXSAVE bit and the YMM and XMM
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* bits in XCR0, so it is not necessary to check those. */
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extern uint32_t OPENSSL_ia32cap_P[4];
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#endif
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#if defined(OPENSSL_ARM) || defined(OPENSSL_AARCH64)
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#if defined(OPENSSL_APPLE)
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/* iOS builds use the static ARM configuration. */
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#define OPENSSL_STATIC_ARMCAP
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#endif
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#if !defined(OPENSSL_STATIC_ARMCAP)
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/* CRYPTO_is_NEON_capable_at_runtime returns true if the current CPU has a NEON
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* unit. Note that |OPENSSL_armcap_P| also exists and contains the same
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* information in a form that's easier for assembly to use. */
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OPENSSL_EXPORT char CRYPTO_is_NEON_capable_at_runtime(void);
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/* CRYPTO_is_NEON_capable returns true if the current CPU has a NEON unit. If
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* this is known statically then it returns one immediately. */
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static inline int CRYPTO_is_NEON_capable(void) {
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/* Only statically skip the runtime lookup on aarch64. On arm, one CPU is
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* known to have a broken NEON unit which is known to fail with on some
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* hand-written NEON assembly. For now, continue to apply the workaround even
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* when the compiler is instructed to freely emit NEON code. See
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* https://crbug.com/341598 and https://crbug.com/606629. */
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#if defined(__ARM_NEON__) && !defined(OPENSSL_ARM)
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return 1;
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#else
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return CRYPTO_is_NEON_capable_at_runtime();
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#endif
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}
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#if defined(OPENSSL_ARM)
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/* CRYPTO_has_broken_NEON returns one if the current CPU is known to have a
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* broken NEON unit. See https://crbug.com/341598. */
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OPENSSL_EXPORT int CRYPTO_has_broken_NEON(void);
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#endif
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/* CRYPTO_is_ARMv8_AES_capable returns true if the current CPU supports the
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* ARMv8 AES instruction. */
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int CRYPTO_is_ARMv8_AES_capable(void);
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/* CRYPTO_is_ARMv8_PMULL_capable returns true if the current CPU supports the
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* ARMv8 PMULL instruction. */
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int CRYPTO_is_ARMv8_PMULL_capable(void);
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#else
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static inline int CRYPTO_is_NEON_capable(void) {
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#if defined(OPENSSL_STATIC_ARMCAP_NEON) || defined(__ARM_NEON__)
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return 1;
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#else
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return 0;
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#endif
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}
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static inline int CRYPTO_is_ARMv8_AES_capable(void) {
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#if defined(OPENSSL_STATIC_ARMCAP_AES)
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return 1;
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#else
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return 0;
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#endif
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}
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static inline int CRYPTO_is_ARMv8_PMULL_capable(void) {
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#if defined(OPENSSL_STATIC_ARMCAP_PMULL)
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return 1;
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#else
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return 0;
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#endif
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}
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#endif /* OPENSSL_STATIC_ARMCAP */
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#endif /* OPENSSL_ARM || OPENSSL_AARCH64 */
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#if defined(OPENSSL_PPC64LE)
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/* CRYPTO_is_PPC64LE_vcrypto_capable returns true iff the current CPU supports
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* the Vector.AES category of instructions. */
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int CRYPTO_is_PPC64LE_vcrypto_capable(void);
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#endif /* OPENSSL_PPC64LE */
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#if defined(__cplusplus)
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} /* extern C */
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#endif
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#endif /* OPENSSL_HEADER_CPU_H */
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