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  1. #!/usr/bin/env perl
  2. $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
  3. push(@INC, "${dir}perlasm", "perlasm");
  4. require "x86asm.pl";
  5. &asm_init($ARGV[0],"crypto/cpu-x86-asm");
  6. for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); }
  7. &function_begin("OPENSSL_ia32_cpuid");
  8. &xor ("edx","edx");
  9. &pushf ();
  10. &pop ("eax");
  11. &mov ("ecx","eax");
  12. &xor ("eax",1<<21);
  13. &push ("eax");
  14. &popf ();
  15. &pushf ();
  16. &pop ("eax");
  17. &xor ("ecx","eax");
  18. &xor ("eax","eax");
  19. &bt ("ecx",21);
  20. &jnc (&label("nocpuid"));
  21. &mov ("esi",&wparam(0));
  22. &mov (&DWP(8,"esi"),"eax"); # clear 3rd word
  23. &cpuid ();
  24. &mov ("edi","eax"); # max value for standard query level
  25. &xor ("eax","eax");
  26. &cmp ("ebx",0x756e6547); # "Genu"
  27. &setne (&LB("eax"));
  28. &mov ("ebp","eax");
  29. &cmp ("edx",0x49656e69); # "ineI"
  30. &setne (&LB("eax"));
  31. &or ("ebp","eax");
  32. &cmp ("ecx",0x6c65746e); # "ntel"
  33. &setne (&LB("eax"));
  34. &or ("ebp","eax"); # 0 indicates Intel CPU
  35. &jz (&label("intel"));
  36. &cmp ("ebx",0x68747541); # "Auth"
  37. &setne (&LB("eax"));
  38. &mov ("esi","eax");
  39. &cmp ("edx",0x69746E65); # "enti"
  40. &setne (&LB("eax"));
  41. &or ("esi","eax");
  42. &cmp ("ecx",0x444D4163); # "cAMD"
  43. &setne (&LB("eax"));
  44. &or ("esi","eax"); # 0 indicates AMD CPU
  45. &jnz (&label("intel"));
  46. # AMD specific
  47. &mov ("eax",0x80000000);
  48. &cpuid ();
  49. &cmp ("eax",0x80000001);
  50. &jb (&label("intel"));
  51. &mov ("esi","eax");
  52. &mov ("eax",0x80000001);
  53. &cpuid ();
  54. &or ("ebp","ecx");
  55. &and ("ebp",1<<11|1); # isolate XOP bit
  56. &cmp ("esi",0x80000008);
  57. &jb (&label("intel"));
  58. &mov ("eax",0x80000008);
  59. &cpuid ();
  60. &movz ("esi",&LB("ecx")); # number of cores - 1
  61. &inc ("esi"); # number of cores
  62. &mov ("eax",1);
  63. &xor ("ecx","ecx");
  64. &cpuid ();
  65. &bt ("edx",28);
  66. &jnc (&label("generic"));
  67. &shr ("ebx",16);
  68. &and ("ebx",0xff);
  69. &cmp ("ebx","esi");
  70. &ja (&label("generic"));
  71. &and ("edx",0xefffffff); # clear hyper-threading bit
  72. &jmp (&label("generic"));
  73. &set_label("intel");
  74. &cmp ("edi",7);
  75. &jb (&label("cacheinfo"));
  76. &mov ("esi",&wparam(0));
  77. &mov ("eax",7);
  78. &xor ("ecx","ecx");
  79. &cpuid ();
  80. &mov (&DWP(8,"esi"),"ebx");
  81. &set_label("cacheinfo");
  82. &cmp ("edi",4);
  83. &mov ("edi",-1);
  84. &jb (&label("nocacheinfo"));
  85. &mov ("eax",4);
  86. &mov ("ecx",0); # query L1D
  87. &cpuid ();
  88. &mov ("edi","eax");
  89. &shr ("edi",14);
  90. &and ("edi",0xfff); # number of cores -1 per L1D
  91. &set_label("nocacheinfo");
  92. &mov ("eax",1);
  93. &xor ("ecx","ecx");
  94. &cpuid ();
  95. &and ("edx",0xbfefffff); # force reserved bits #20, #30 to 0
  96. &cmp ("ebp",0);
  97. &jne (&label("notintel"));
  98. &or ("edx",1<<30); # set reserved bit#30 on Intel CPUs
  99. &set_label("notintel");
  100. &bt ("edx",28); # test hyper-threading bit
  101. &jnc (&label("generic"));
  102. &and ("edx",0xefffffff);
  103. &cmp ("edi",0);
  104. &je (&label("generic"));
  105. &or ("edx",0x10000000);
  106. &shr ("ebx",16);
  107. &cmp (&LB("ebx"),1);
  108. &ja (&label("generic"));
  109. &and ("edx",0xefffffff); # clear hyper-threading bit if not
  110. &set_label("generic");
  111. &and ("ebp",1<<11); # isolate AMD XOP flag
  112. &and ("ecx",0xfffff7ff); # force 11th bit to 0
  113. &mov ("esi","edx");
  114. &or ("ebp","ecx"); # merge AMD XOP flag
  115. &bt ("ecx",27); # check OSXSAVE bit
  116. &jnc (&label("clear_avx"));
  117. &xor ("ecx","ecx");
  118. &data_byte(0x0f,0x01,0xd0); # xgetbv
  119. &and ("eax",6);
  120. &cmp ("eax",6);
  121. &je (&label("done"));
  122. &cmp ("eax",2);
  123. &je (&label("clear_avx"));
  124. &set_label("clear_xmm");
  125. &and ("ebp",0xfdfffffd); # clear AESNI and PCLMULQDQ bits
  126. &and ("esi",0xfeffffff); # clear FXSR
  127. &set_label("clear_avx");
  128. &and ("ebp",0xefffe7ff); # clear AVX, FMA and AMD XOP bits
  129. &mov ("edi",&wparam(0));
  130. &and (&DWP(8,"edi"),0xffffffdf); # clear AVX2
  131. &set_label("done");
  132. &mov ("eax","esi");
  133. &mov ("edx","ebp");
  134. &set_label("nocpuid");
  135. &function_end("OPENSSL_ia32_cpuid");
  136. &external_label("OPENSSL_ia32cap_P");
  137. &function_begin_B("OPENSSL_rdtsc","EXTRN\t_OPENSSL_ia32cap_P:DWORD");
  138. &xor ("eax","eax");
  139. &xor ("edx","edx");
  140. &picmeup("ecx","OPENSSL_ia32cap_P");
  141. &bt (&DWP(0,"ecx"),4);
  142. &jnc (&label("notsc"));
  143. &rdtsc ();
  144. &set_label("notsc");
  145. &ret ();
  146. &function_end_B("OPENSSL_rdtsc");
  147. # This works in Ring 0 only [read DJGPP+MS-DOS+privileged DPMI host],
  148. # but it's safe to call it on any [supported] 32-bit platform...
  149. # Just check for [non-]zero return value...
  150. &function_begin_B("OPENSSL_instrument_halt","EXTRN\t_OPENSSL_ia32cap_P:DWORD");
  151. &picmeup("ecx","OPENSSL_ia32cap_P");
  152. &bt (&DWP(0,"ecx"),4);
  153. &jnc (&label("nohalt")); # no TSC
  154. &data_word(0x9058900e); # push %cs; pop %eax
  155. &and ("eax",3);
  156. &jnz (&label("nohalt")); # not enough privileges
  157. &pushf ();
  158. &pop ("eax");
  159. &bt ("eax",9);
  160. &jnc (&label("nohalt")); # interrupts are disabled
  161. &rdtsc ();
  162. &push ("edx");
  163. &push ("eax");
  164. &halt ();
  165. &rdtsc ();
  166. &sub ("eax",&DWP(0,"esp"));
  167. &sbb ("edx",&DWP(4,"esp"));
  168. &add ("esp",8);
  169. &ret ();
  170. &set_label("nohalt");
  171. &xor ("eax","eax");
  172. &xor ("edx","edx");
  173. &ret ();
  174. &function_end_B("OPENSSL_instrument_halt");
  175. # Essentially there is only one use for this function. Under DJGPP:
  176. #
  177. # #include <go32.h>
  178. # ...
  179. # i=OPENSSL_far_spin(_dos_ds,0x46c);
  180. # ...
  181. # to obtain the number of spins till closest timer interrupt.
  182. &function_begin_B("OPENSSL_far_spin");
  183. &pushf ();
  184. &pop ("eax");
  185. &bt ("eax",9);
  186. &jnc (&label("nospin")); # interrupts are disabled
  187. &mov ("eax",&DWP(4,"esp"));
  188. &mov ("ecx",&DWP(8,"esp"));
  189. &data_word (0x90d88e1e); # push %ds, mov %eax,%ds
  190. &xor ("eax","eax");
  191. &mov ("edx",&DWP(0,"ecx"));
  192. &jmp (&label("spin"));
  193. &align (16);
  194. &set_label("spin");
  195. &inc ("eax");
  196. &cmp ("edx",&DWP(0,"ecx"));
  197. &je (&label("spin"));
  198. &data_word (0x1f909090); # pop %ds
  199. &ret ();
  200. &set_label("nospin");
  201. &xor ("eax","eax");
  202. &xor ("edx","edx");
  203. &ret ();
  204. &function_end_B("OPENSSL_far_spin");
  205. &function_begin_B("OPENSSL_wipe_cpu","EXTRN\t_OPENSSL_ia32cap_P:DWORD");
  206. &xor ("eax","eax");
  207. &xor ("edx","edx");
  208. &picmeup("ecx","OPENSSL_ia32cap_P");
  209. &mov ("ecx",&DWP(0,"ecx"));
  210. &bt (&DWP(0,"ecx"),1);
  211. &jnc (&label("no_x87"));
  212. if ($sse2) {
  213. &and ("ecx",1<<26|1<<24); # check SSE2 and FXSR bits
  214. &cmp ("ecx",1<<26|1<<24);
  215. &jne (&label("no_sse2"));
  216. &pxor ("xmm0","xmm0");
  217. &pxor ("xmm1","xmm1");
  218. &pxor ("xmm2","xmm2");
  219. &pxor ("xmm3","xmm3");
  220. &pxor ("xmm4","xmm4");
  221. &pxor ("xmm5","xmm5");
  222. &pxor ("xmm6","xmm6");
  223. &pxor ("xmm7","xmm7");
  224. &set_label("no_sse2");
  225. }
  226. # just a bunch of fldz to zap the fp/mm bank followed by finit...
  227. &data_word(0xeed9eed9,0xeed9eed9,0xeed9eed9,0xeed9eed9,0x90e3db9b);
  228. &set_label("no_x87");
  229. &lea ("eax",&DWP(4,"esp"));
  230. &ret ();
  231. &function_end_B("OPENSSL_wipe_cpu");
  232. &function_begin_B("OPENSSL_atomic_add");
  233. &mov ("edx",&DWP(4,"esp")); # fetch the pointer, 1st arg
  234. &mov ("ecx",&DWP(8,"esp")); # fetch the increment, 2nd arg
  235. &push ("ebx");
  236. &nop ();
  237. &mov ("eax",&DWP(0,"edx"));
  238. &set_label("spin");
  239. &lea ("ebx",&DWP(0,"eax","ecx"));
  240. &nop ();
  241. &data_word(0x1ab10ff0); # lock; cmpxchg %ebx,(%edx) # %eax is envolved and is always reloaded
  242. &jne (&label("spin"));
  243. &mov ("eax","ebx"); # OpenSSL expects the new value
  244. &pop ("ebx");
  245. &ret ();
  246. &function_end_B("OPENSSL_atomic_add");
  247. # This function can become handy under Win32 in situations when
  248. # we don't know which calling convention, __stdcall or __cdecl(*),
  249. # indirect callee is using. In C it can be deployed as
  250. #
  251. #ifdef OPENSSL_CPUID_OBJ
  252. # type OPENSSL_indirect_call(void *f,...);
  253. # ...
  254. # OPENSSL_indirect_call(func,[up to $max arguments]);
  255. #endif
  256. #
  257. # (*) it's designed to work even for __fastcall if number of
  258. # arguments is 1 or 2!
  259. &function_begin_B("OPENSSL_indirect_call");
  260. {
  261. my ($max,$i)=(7,); # $max has to be chosen as 4*n-1
  262. # in order to preserve eventual
  263. # stack alignment
  264. &push ("ebp");
  265. &mov ("ebp","esp");
  266. &sub ("esp",$max*4);
  267. &mov ("ecx",&DWP(12,"ebp"));
  268. &mov (&DWP(0,"esp"),"ecx");
  269. &mov ("edx",&DWP(16,"ebp"));
  270. &mov (&DWP(4,"esp"),"edx");
  271. for($i=2;$i<$max;$i++)
  272. {
  273. # Some copies will be redundant/bogus...
  274. &mov ("eax",&DWP(12+$i*4,"ebp"));
  275. &mov (&DWP(0+$i*4,"esp"),"eax");
  276. }
  277. &call_ptr (&DWP(8,"ebp"));# make the call...
  278. &mov ("esp","ebp"); # ... and just restore the stack pointer
  279. # without paying attention to what we called,
  280. # (__cdecl *func) or (__stdcall *one).
  281. &pop ("ebp");
  282. &ret ();
  283. }
  284. &function_end_B("OPENSSL_indirect_call");
  285. &function_begin_B("OPENSSL_ia32_rdrand");
  286. &mov ("ecx",8);
  287. &set_label("loop");
  288. &rdrand ("eax");
  289. &jc (&label("break"));
  290. &loop (&label("loop"));
  291. &set_label("break");
  292. &cmp ("eax",0);
  293. &cmove ("eax","ecx");
  294. &ret ();
  295. &function_end_B("OPENSSL_ia32_rdrand");
  296. &hidden("OPENSSL_ia32cap_P");
  297. &asm_finish();