207 lines
6.1 KiB
C
207 lines
6.1 KiB
C
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/** @addtogroup adc_file ADC peripheral API
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* @ingroup peripheral_apis
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*
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* @author @htmlonly © @endhtmlonly 2019 Guillaume Revaillot <g.revaillot@gmail.com>
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*
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* @date 10 January 2019
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/stm32/adc.h>
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#include <libopencm3/cm3/assert.h>
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/** @brief ADC Set Clock Source
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*
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* @param[in] adc ADC base address (@ref adc_reg_base)
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* @param[in] source Source (@ref adc_cfgr2_ckmode)
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*/
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void adc_set_clk_source(uint32_t adc, uint32_t source)
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{
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uint32_t reg32 = ADC_CFGR2(adc);
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reg32 &= ~(ADC_CFGR2_CKMODE_MASK << ADC_CFGR2_CKMODE_SHIFT);
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ADC_CFGR2(adc) = (reg32 | (source << ADC_CFGR2_CKMODE_SHIFT));
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}
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/** @brief ADC Set Clock Prescale
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*
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* @param[in] adc ADC base address (@ref adc_reg_base)
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* @param[in] prescale Prescale value for ADC Async Clock (@ref adc_ccr_presc)
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*/
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void adc_set_clk_prescale(uint32_t adc, uint32_t prescale)
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{
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uint32_t reg32 = ADC_CCR(adc);
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reg32 &= ~(ADC_CCR_PRESC_MASK << ADC_CCR_PRESC_SHIFT);
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ADC_CCR(adc) = (reg32 | (prescale << ADC_CCR_PRESC_SHIFT));
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}
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/** @brief ADC Set the Sample Time for All Channels
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*
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* Setup all ADC channels to use a single ADC sampling time.
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*
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* @param[in] adc ADC base address (@ref adc_reg_base)
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* @param[in] time ADC Sampling Time (@ref adc_api_smptime)
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*/
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void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time)
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{
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uint32_t reg32;
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reg32 = ADC_SMPR1(adc);
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/* set all channels on ADC_SMPR_SMPSEL_SMP1 first @ref adc_smpr_smpsel sample time selection, and clear its value */
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reg32 &= ~((ADC_SMPR_SMPSEL_MASK << ADC_SMPR_SMP1_SHIFT) | (ADC_SMPR_SMP1_MASK << ADC_SMPR_SMP1_SHIFT));
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/* setup ADC_SMPR_SMPSEL_SMP1 sample time */
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reg32 |= (time << ADC_SMPR_SMP1_SHIFT);
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ADC_SMPR1(adc) = reg32;
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}
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/** @brief ADC Set the Sample Time Selection for a Single Channel
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*
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* @param[in] adc ADC base address (@ref adc_reg_base)
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* @param[in] channel ADC Channel (0..18 or @ref adc_channel)
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* @param[in] selection Sampling time selection (@ref adc_smpr_smpsel)
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*/
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void adc_set_channel_sample_time_selection(uint32_t adc, uint8_t channel, uint8_t selection)
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{
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uint32_t reg32;
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reg32 = ADC_SMPR1(adc);
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reg32 &= ~(ADC_SMPR_SMPSEL_CHANNEL_MASK << ADC_SMPR_SMPSEL_CHANNEL_SHIFT(channel));
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reg32 |= (selection << ADC_SMPR_SMPSEL_CHANNEL_SHIFT(channel));
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ADC_SMPR1(adc) = reg32;
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}
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/** @brief ADC Set the Sample Time for Given Selection.
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*
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* @param[in] adc ADC base address (@ref adc_reg_base)
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* @param[in] selection Sampling Time Selection (@ref adc_smpr_smpsel)
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* @param[in] time Sampling Time (@ref adc_smpr_smp)
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*/
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void adc_set_selection_sample_time(uint32_t adc, uint8_t selection, uint8_t time)
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{
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uint32_t reg32;
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reg32 = ADC_SMPR1(adc);
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switch (selection) {
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case ADC_SMPR_SMPSEL_SMP1:
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reg32 &= ~(ADC_SMPR_SMP1_MASK << ADC_SMPR_SMP1_SHIFT);
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reg32 |= (time << ADC_SMPR_SMP1_SHIFT);
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break;
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case ADC_SMPR_SMPSEL_SMP2:
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reg32 &= ~(ADC_SMPR_SMP2_MASK << ADC_SMPR_SMP2_SHIFT);
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reg32 |= (time << ADC_SMPR_SMP2_SHIFT);
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break;
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}
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ADC_SMPR1(adc) = reg32;
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}
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/** @brief ADC Set a Regular Channel Conversion Sequence
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*
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* Define a simple sequence of channels to be converted.
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* ADCSTART must be de-asserted before sequence setup.
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*
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* @param[in] adc ADC base address (@ref adc_reg_base)
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* @param[in] length Number of channels in the group, range 0..18
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* @param[in] channel Set of channels in sequence (0..18 or @ref adc_channel)
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*/
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void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
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{
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uint32_t reg32 = 0;
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bool stepup = false, stepdn = false;
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if (length > ADC_CHSELR_MAX_CHANNELS) {
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return;
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}
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if (length == 0) {
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ADC_CHSELR(adc) = 0;
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return;
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}
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reg32 |= (1 << channel[0]);
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for (uint8_t i = 1; i < length; i++) {
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reg32 |= ADC_CHSELR_CHSEL(channel[i]);
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stepup |= channel[i-1] < channel[i];
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stepdn |= channel[i-1] > channel[i];
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}
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/* Check if the channel list is in order */
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if (stepup && stepdn) {
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cm3_assert_not_reached();
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}
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/* Each modification to ADC_CFGR1's SCANDIR or CHSELRMOD bits or
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ADC_CHSELR register must be done after previous configuration change
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being properly applied: We have to clear ccrdy bit before and poll for
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it being assert back after, before going on. We also need to wait for
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configuration applied before starting conversion, or start will be
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ignored. */
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/* Setup scandir, if needed, waiting for configuration be applied.. */
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if (stepdn && (!(ADC_CFGR1(adc) & ADC_CFGR1_SCANDIR))) {
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ADC_ISR(adc) &= ~ADC_ISR_CCRDY;
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ADC_CFGR1(adc) |= ADC_CFGR1_SCANDIR;
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while (!(ADC_ISR(adc) & ADC_ISR_CCRDY));
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} else if (stepup && ((ADC_CFGR1(adc) & ADC_CFGR1_SCANDIR))) {
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ADC_ISR(adc) &= ~ADC_ISR_CCRDY;
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ADC_CFGR1(adc) &= ~ADC_CFGR1_SCANDIR;
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while (!(ADC_ISR(adc) & ADC_ISR_CCRDY));
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}
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/* Setup ADC in simple, not configurable, mode, if needed. */
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if ((ADC_CFGR1(adc) & ADC_CFGR1_CHSELRMOD)) {
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ADC_ISR(adc) &= ~ADC_ISR_CCRDY;
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ADC_CFGR1(adc) &= ~ADC_CFGR1_CHSELRMOD;
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while (!(ADC_ISR(adc) & ADC_ISR_CCRDY));
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}
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if (ADC_CHSELR(adc) != reg32) {
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ADC_ISR(adc) &= ~ADC_ISR_CCRDY;
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ADC_CHSELR(adc) = reg32;
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while (!(ADC_ISR(adc) & ADC_ISR_CCRDY));
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}
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}
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/**
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* @brief Enable the ADC Voltage regulator
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*
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* @param[in] adc ADC base address (@ref adc_reg_base)
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*/
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void adc_enable_regulator(uint32_t adc)
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{
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ADC_CR(adc) |= ADC_CR_ADVREGEN;
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}
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/**
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* @brief Disable the ADC Voltage regulator
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*
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* @param[in] adc ADC base address (@ref adc_reg_base)
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*/
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void adc_disable_regulator(uint32_t adc)
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{
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ADC_CR(adc) &= ~ADC_CR_ADVREGEN;
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}
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/**@}*/
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