431 lines
11 KiB
C
431 lines
11 KiB
C
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/** @addtogroup adc_file ADC peripheral API
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@ingroup peripheral_apis
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@author @htmlonly © @endhtmlonly
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2015 Karl Palsson <karlp@tweak.net.au>
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This library supports one style of the Analog to Digital Conversion System in
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the STM32 series of ARM Cortex Microcontrollers by ST Microelectronics.
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The style of ADC Peripheral supported by this code is found in the F0, L0 and
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F30x series devices (at the time of writing)
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2015 Karl Palsson <karlp@tweak.net.au>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/stm32/adc.h>
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/** @brief ADC Read the End-of-Conversion Flag
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*
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* This flag is set by hardware at the end of each regular conversion of a
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* channel when a new data is available in the ADCx_DR register.
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*
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* @param[in] adc Unsigned int32. ADC block register address base
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* @ref adc_reg_base
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* @returns bool. End of conversion flag.
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*/
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bool adc_eoc(uint32_t adc)
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{
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return ADC_ISR(adc) & ADC_ISR_EOC;
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}
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/** @brief ADC Read the End-of-Sequence Flag for Regular Conversions
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*
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* This flag is set after all channels of an regular group have been
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* converted.
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*
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* @param[in] adc Unsigned int32. ADC block register address base
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* @ref adc_reg_base
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* @returns bool. End of conversion flag.
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*/
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bool adc_eos(uint32_t adc)
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{
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return ADC_ISR(adc) & ADC_ISR_EOS;
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}
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/**
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* Turn on the ADC (async)
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* @sa adc_wait_power_on
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* @param adc ADC Block register address base @ref adc_reg_base
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*/
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void adc_power_on_async(uint32_t adc)
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{
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ADC_CR(adc) |= ADC_CR_ADEN;
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}
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/**
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* Is the ADC powered up and ready?
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* @sa adc_power_on_async
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* @param adc ADC Block register address base @ref adc_reg_base
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* @return true if adc is ready for use
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*/
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bool adc_is_power_on(uint32_t adc)
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{
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return ADC_ISR(adc) & ADC_ISR_ADRDY;
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}
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/**
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* Turn on the ADC
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* @sa adc_power_on_async
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* @param adc ADC Block register address base @ref adc_reg_base
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*/
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void adc_power_on(uint32_t adc)
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{
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adc_power_on_async(adc);
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while (!adc_is_power_on(adc));
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}
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/**
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* Turn off the ADC (async)
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* This will actually block if it needs to turn off a currently running
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* conversion, as per ref man. (Handles injected on hardware that supports
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* injected conversions.
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* @sa adc_wait_power_off
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* @param adc ADC Block register address base @ref adc_reg_base
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*/
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void adc_power_off_async(uint32_t adc)
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{
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if (adc_is_power_off(adc)) {
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return;
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}
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uint32_t checks = ADC_CR_ADSTART;
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uint32_t stops = ADC_CR_ADSTP;
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#if defined(ADC_CR_JADSTART)
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checks |= ADC_CR_JADSTART;
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stops |= ADC_CR_JADSTP;
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#endif
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if (ADC_CR(adc) & checks) {
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ADC_CR(adc) |= stops;
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while (ADC_CR(adc) & checks);
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}
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ADC_CR(adc) |= ADC_CR_ADDIS;
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}
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/**
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* Is the ADC powered down?
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* @sa adc_power_off_async
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* @param adc ADC Block register address base @ref adc_reg_base
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*/
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bool adc_is_power_off(uint32_t adc)
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{
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return !(ADC_CR(adc) & ADC_CR_ADEN);
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}
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/**
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* Turn off the ADC
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* This will actually block if it needs to turn off a currently running
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* conversion, as per ref man.
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* @sa adc_power_off_async
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* @param adc ADC Block register address base @ref adc_reg_base
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*/
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void adc_power_off(uint32_t adc)
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{
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adc_power_off_async(adc);
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while (!adc_is_power_off(adc));
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}
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/**
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* Start the ADC calibration and immediately return.
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* @sa adc_calibrate
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* @sa adc_is_calibrating
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* @param adc ADC Block register address base @ref adc_reg_base
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*/
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void adc_calibrate_async(uint32_t adc)
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{
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ADC_CR(adc) |= ADC_CR_ADCAL;
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}
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/**
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* Is the ADC Calibrating?
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* @param adc ADC Block register address base @ref adc_reg_base
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* @return true if the adc is currently calibrating
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*/
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bool adc_is_calibrating(uint32_t adc)
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{
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return ADC_CR(adc) & ADC_CR_ADCAL;
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}
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/**
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* Start ADC calibration and wait for it to finish
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* @param adc ADC Block register address base @ref adc_reg_base
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*/
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void adc_calibrate(uint32_t adc)
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{
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adc_calibrate_async(adc);
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while (adc_is_calibrating(adc));
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}
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/**
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* Enable Continuous Conversion Mode
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* In this mode the ADC starts a new conversion of a single channel or a channel
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* group immediately following completion of the previous channel group
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* conversion.
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*
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* @param[in] adc ADC block register address base @ref adc_reg_base
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*/
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void adc_set_continuous_conversion_mode(uint32_t adc)
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{
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ADC_CFGR1(adc) |= ADC_CFGR1_CONT;
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}
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/**
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* Enable Single Conversion Mode
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* In this mode the ADC performs a conversion of one channel or a channel group
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* and stops.
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*
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* @param[in] adc ADC block register address base @ref adc_reg_base
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*/
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void adc_set_single_conversion_mode(uint32_t adc)
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{
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ADC_CFGR1(adc) &= ~ADC_CFGR1_CONT;
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}
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/** @brief ADC Set Resolution
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*
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* ADC Resolution can be reduced from 12 bits to 10, 8 or 6 bits for a
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* corresponding reduction in conversion time.
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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* @param[in] resolution Unsigned int16. Resolution value (@ref adc_api_res)
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*/
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void adc_set_resolution(uint32_t adc, uint16_t resolution)
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{
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ADC_CFGR1(adc) = (ADC_CFGR1(adc) & ~ADC_CFGR1_RES_MASK) | resolution;
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}
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/** @brief ADC Set the Data as Left Aligned
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_set_left_aligned(uint32_t adc)
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{
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ADC_CFGR1(adc) |= ADC_CFGR1_ALIGN;
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}
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/** @brief ADC Set the Data as Right Aligned
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_set_right_aligned(uint32_t adc)
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{
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ADC_CFGR1(adc) &= ~ADC_CFGR1_ALIGN;
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}
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/** @brief ADC Enable DMA Transfers
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_enable_dma(uint32_t adc)
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{
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ADC_CFGR1(adc) |= ADC_CFGR1_DMAEN;
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}
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/** @brief ADC Disable DMA Transfers
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_disable_dma(uint32_t adc)
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{
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ADC_CFGR1(adc) &= ~ADC_CFGR1_DMAEN;
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}
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/** @brief ADC Enable the Overrun Interrupt
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*
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* The overrun interrupt is generated when data is not read from a result
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* register before the next conversion is written. If DMA is enabled, all
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* transfers are terminated and any conversion sequence is aborted.
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_enable_overrun_interrupt(uint32_t adc)
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{
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ADC_IER(adc) |= ADC_IER_OVRIE;
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}
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/** @brief ADC Disable the Overrun Interrupt
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_disable_overrun_interrupt(uint32_t adc)
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{
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ADC_IER(adc) &= ~ADC_IER_OVRIE;
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}
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/** @brief ADC Read the Overrun Flag
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*
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* The overrun flag is set when data is not read from a result register before
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* the next conversion is written. If DMA is enabled, all transfers are
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* terminated and any conversion sequence is aborted.
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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bool adc_get_overrun_flag(uint32_t adc)
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{
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return ADC_ISR(adc) & ADC_ISR_OVR;
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}
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/** @brief ADC Clear Overrun Flags
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*
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* The overrun flag is cleared. Note that if an overrun occurs, DMA is
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* terminated.
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* The flag must be cleared and the DMA stream and ADC reinitialised to resume
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* conversions (see the reference manual).
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_clear_overrun_flag(uint32_t adc)
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{
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ADC_ISR(adc) = ADC_ISR_OVR;
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}
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/** @brief ADC Enable Regular End-Of-Conversion Interrupt
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_enable_eoc_interrupt(uint32_t adc)
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{
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ADC_IER(adc) |= ADC_IER_EOCIE;
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}
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/** @brief ADC Disable Regular End-Of-Conversion Interrupt
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_disable_eoc_interrupt(uint32_t adc)
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{
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ADC_IER(adc) &= ~ADC_IER_EOCIE;
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}
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/** @brief ADC Read from the Regular Conversion Result Register
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*
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* The result read back is 12 bits, right or left aligned within the first
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* 16 bits.
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*
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* @param[in] adc Unsigned int32. ADC block register address base
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* @ref adc_reg_base
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* @returns Unsigned int32 conversion result.
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*/
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uint32_t adc_read_regular(uint32_t adc)
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{
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return ADC_DR(adc);
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}
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/**
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* Enable the temperature sensor (only)
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* The channel this is available on is unfortunately not
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* consistent, even though the bit used to enable it is.
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* @sa adc_disable_temperature_sensor
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*/
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void adc_enable_temperature_sensor(void)
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{
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ADC_CCR(ADC1) |= ADC_CCR_TSEN;
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}
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/**
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* Disable the temperature sensor (only)
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* @sa adc_enable_temperature_sensor
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*/
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void adc_disable_temperature_sensor(void)
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{
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ADC_CCR(ADC1) &= ~ADC_CCR_TSEN;
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}
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/**
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* Enable the internal voltage reference (only)
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* The channel this is available on is unfortunately not
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* consistent, even though the bit used to enable it is.
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* FIXME - on f3, you can actually have it on ADC34 as well!
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* @sa adc_disable_vrefint
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*/
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void adc_enable_vrefint(void)
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{
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ADC_CCR(ADC1) |= ADC_CCR_VREFEN;
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}
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/**
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* Disable the internal voltage reference (only)
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* @sa adc_enable_vrefint
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*/
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void adc_disable_vrefint(void)
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{
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ADC_CCR(ADC1) &= ~ADC_CCR_VREFEN;
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}
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||
|
|
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/** @brief ADC Software Triggered Conversion on Regular Channels
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|
*
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||
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|
* This starts conversion on a set of defined regular channels.
|
||
|
|
* Depending on the configuration bits EXTEN, a conversion will start
|
||
|
|
* immediately (software trigger configuration) or once a regular hardware
|
||
|
|
* trigger event occurs (hardware trigger configuration)
|
||
|
|
*
|
||
|
|
* @param[in] adc ADC block register address base @ref adc_reg_base
|
||
|
|
*/
|
||
|
|
void adc_start_conversion_regular(uint32_t adc)
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||
|
|
{
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||
|
|
/* Start conversion on regular channels. */
|
||
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|
ADC_CR(adc) |= ADC_CR_ADSTART;
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||
|
|
}
|
||
|
|
|
||
|
|
/** @brief Enable circular mode for DMA transfers
|
||
|
|
*
|
||
|
|
* For this to work it needs to be ebabled on the DMA side as well.
|
||
|
|
*
|
||
|
|
* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
|
||
|
|
*/
|
||
|
|
void adc_enable_dma_circular_mode(uint32_t adc)
|
||
|
|
{
|
||
|
|
ADC_CFGR1(adc) |= ADC_CFGR1_DMACFG;
|
||
|
|
}
|
||
|
|
|
||
|
|
/** @brief Disable circular mode for DMA transfers
|
||
|
|
*
|
||
|
|
* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
|
||
|
|
*/
|
||
|
|
void adc_disable_dma_circular_mode(uint32_t adc)
|
||
|
|
{
|
||
|
|
ADC_CFGR1(adc) &= ~ADC_CFGR1_DMACFG;
|
||
|
|
}
|
||
|
|
|
||
|
|
/** Enable Delayed Conversion Mode.
|
||
|
|
*
|
||
|
|
* @param[in] adc ADC block register address base @ref adc_reg_base
|
||
|
|
*/
|
||
|
|
void adc_enable_delayed_conversion_mode(uint32_t adc)
|
||
|
|
{
|
||
|
|
ADC_CFGR1(adc) |= ADC_CFGR1_AUTDLY;
|
||
|
|
}
|
||
|
|
|
||
|
|
/** Enable Delayed Conversion Mode.
|
||
|
|
*
|
||
|
|
* @param[in] adc ADC block register address base @ref adc_reg_base
|
||
|
|
*/
|
||
|
|
void adc_disable_delayed_conversion_mode(uint32_t adc)
|
||
|
|
{
|
||
|
|
ADC_CFGR1(adc) &= ~ADC_CFGR1_AUTDLY;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**@}*/
|