66 lines
2.2 KiB
C
66 lines
2.2 KiB
C
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/**
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* @brief <b>libopencm3 STM32H7xx Power Control</b>
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*
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* @version 1.0.0
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*
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* @date 16 December, 2019
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*
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* This library supports the power control system for the
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* STM32H7 series of ARM Cortex Microcontrollers by ST Microelectronics.
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com>
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* Copyright (C) 2017 Matthew Lai <m@matthewlai.ca>
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* Copyright (C) 2019 Brian Viele <vielster@allocor.tech>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/stm32/pwr.h>
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#include <libopencm3/stm32/rcc.h>
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#include <libopencm3/stm32/syscfg.h>
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void pwr_set_mode_ldo(void) {
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const uint32_t ldo_mask = (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS);
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PWR_CR3 = (PWR_CR3 & ~ldo_mask) | (PWR_CR3_SCUEN | PWR_CR3_LDOEN);
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while (!(PWR_CSR1 & PWR_CSR1_ACTVOSRDY));
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}
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void pwr_set_svos_scale(enum pwr_svos_scale scale)
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{
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uint32_t pwr_cr1_reg = PWR_CR1;
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pwr_cr1_reg = (pwr_cr1_reg & ~(PWR_CR1_SVOS_MASK << PWR_CR1_SVOS_SHIFT));
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PWR_CR1 = pwr_cr1_reg | scale;
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}
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void pwr_set_vos_scale(enum pwr_vos_scale scale) {
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rcc_periph_clock_enable(RCC_SYSCFG); /* Ensure we can access ODEN. */
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uint32_t d3cr_masked = PWR_D3CR & ~(PWR_D3CR_VOS_MASK << PWR_D3CR_VOS_SHIFT);
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/* Per the manual, VOS0 is implemented as VOS1 + ODEN. Handle this case. */
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if (scale == PWR_VOS_SCALE_0) {
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PWR_D3CR = d3cr_masked | PWR_VOS_SCALE_1;
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SYSCFG_PWRCR |= SYSCFG_PWRCR_ODEN;
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} else {
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SYSCFG_PWRCR &= ~SYSCFG_PWRCR_ODEN;
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PWR_D3CR = d3cr_masked | scale;
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}
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while (!(PWR_D3CR & PWR_D3CR_VOSRDY));
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}
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