780 lines
24 KiB
C
780 lines
24 KiB
C
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/** @addtogroup adc_file ADC peripheral API
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@ingroup peripheral_apis
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@author @htmlonly © @endhtmlonly
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2009 Edward Cheeseman <evbuilder@users.sourceforge.net>
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@author @htmlonly © @endhtmlonly
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2012 Ken Sarkies <ksarkies@internode.on.net>
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@author @htmlonly © @endhtmlonly
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2014 Karl Palsson <karlp@tweak.net.au>
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This library supports one style of the Analog to Digital Conversion System in
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the STM32 series of ARM Cortex Microcontrollers by ST Microelectronics.
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The style of ADC Peripheral supported by this code is found in the F1, F2,
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F37x, F38x, F4, and L1 series devices (at the time of writing) but is quite
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different to the style found on the F0 and F30x and F31x.
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Devices can have up to three A/D converters each with their own set of
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registers.
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However all the A/D converters share a common clock. On most devices, this is
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prescaled from the APB2 clock by default by a minimum factor of 2 to a maximum
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of 8, though on the L1 this is always a divider from the HSI. (And therefore HSI
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_must_ be enabled before attempting to enable the ADC)
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Each A/D converter has up to ADC_MAX_CHANNELS channels:
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@li On ADC1 the analog channels 16 and 17 are internally connected to the
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temperature sensor and V<sub>REFINT</sub>, respectively.
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@li On ADC2 (if available) the analog channels 16 and 17 are internally
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connected to V<sub>SS</sub>.
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@li On ADC3 (if available) the analog channels 9, 14, 15, 16 and 17 are
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internally connected to V<sub>SS</sub>.
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The conversions can occur as a one-off conversion whereby the process stops once
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conversion is complete. The conversions can also be continuous wherein a new
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conversion starts immediately the previous conversion has ended.
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Conversion can occur as a single channel conversion or a scan of a group of
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channels in either continuous or one-off mode. If more than one channel is
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converted in a scan group, DMA must be used to transfer the data as there is
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only one result register available. An interrupt can be set to occur at the end
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of conversion, which occurs after all channels have been scanned.
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A discontinuous mode allows a subgroup of group of a channels to be converted in
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bursts of a given length.
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Injected conversions allow a second group of channels to be converted separately
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from the regular group. An interrupt can be set to occur at the end of
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conversion, which occurs after all channels have been scanned.
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@section adc_api_ex Basic ADC Handling API.
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Example 1: Simple single channel conversion polled. Enable the peripheral clock
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and ADC, reset ADC and set the prescaler divider. Set dual mode to independent
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(default). Enable triggering for a software trigger.
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@code
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rcc_periph_clock_enable(RCC_ADC1);
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adc_power_off(ADC1);
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rcc_periph_reset_pulse(RST_ADC1);
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rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2);
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adc_set_dual_mode(ADC_CR1_DUALMOD_IND);
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adc_disable_scan_mode(ADC1);
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adc_set_single_conversion_mode(ADC1);
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adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR1_SMP_1DOT5CYC);
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adc_enable_trigger(ADC1, ADC_CR2_EXTSEL_SWSTART);
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adc_power_on(ADC1);
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adc_reset_calibration(ADC1);
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adc_calibration(ADC1);
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adc_start_conversion_regular(ADC1);
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while (! adc_eoc(ADC1));
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reg16 = adc_read_regular(ADC1);
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@endcode
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2014 Karl Palsson <karlp@tweak.net.au>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/stm32/adc.h>
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Off
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Turn off the ADC to reduce power consumption to a few microamps.
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@param[in] adc Unsigned int32. ADC block register address base @ref
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adc_reg_base.
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*/
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void adc_power_off(uint32_t adc)
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{
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ADC_CR2(adc) &= ~ADC_CR2_ADON;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Enable Analog Watchdog for Regular Conversions
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The analog watchdog allows the monitoring of an analog signal between two
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threshold levels. The thresholds must be preset.
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@param[in] adc Unsigned int32. ADC block register address base @ref
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adc_reg_base.
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*/
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void adc_enable_analog_watchdog_regular(uint32_t adc)
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{
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ADC_CR1(adc) |= ADC_CR1_AWDEN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Disable Analog Watchdog for Regular Conversions
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@param[in] adc Unsigned int32. ADC block register address base @ref
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adc_reg_base.
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*/
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void adc_disable_analog_watchdog_regular(uint32_t adc)
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{
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ADC_CR1(adc) &= ~ADC_CR1_AWDEN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Enable Analog Watchdog for Injected Conversions
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The analog watchdog allows the monitoring of an analog signal between two
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threshold levels. The thresholds must be preset. Comparison is done before data
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alignment takes place, so the thresholds are left-aligned.
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@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
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*/
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void adc_enable_analog_watchdog_injected(uint32_t adc)
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{
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ADC_CR1(adc) |= ADC_CR1_JAWDEN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Disable Analog Watchdog for Injected Conversions
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@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
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*/
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void adc_disable_analog_watchdog_injected(uint32_t adc)
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{
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ADC_CR1(adc) &= ~ADC_CR1_JAWDEN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Enable Discontinuous Mode for Regular Conversions
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In this mode the ADC converts, on each trigger, a subgroup of up to 8 of the
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defined regular channel group. The subgroup is defined by the number of
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consecutive channels to be converted. After a subgroup has been converted
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the next trigger will start conversion of the immediately following subgroup
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of the same length or until the whole group has all been converted. When the
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the whole group has been converted, the next trigger will restart conversion
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of the subgroup at the beginning of the whole group.
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@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
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@param[in] length Unsigned int8. Number of channels in the group @ref
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adc_cr1_discnum
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*/
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void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length)
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{
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if ((length-1) > 7) {
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return;
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}
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ADC_CR1(adc) |= ADC_CR1_DISCEN;
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ADC_CR1(adc) |= ((length-1) << ADC_CR1_DISCNUM_SHIFT);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Disable Discontinuous Mode for Regular Conversions
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@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
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*/
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void adc_disable_discontinuous_mode_regular(uint32_t adc)
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{
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ADC_CR1(adc) &= ~ADC_CR1_DISCEN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Enable Discontinuous Mode for Injected Conversions
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In this mode the ADC converts sequentially one channel of the defined group of
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injected channels, cycling back to the first channel in the group once the
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entire group has been converted.
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@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
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*/
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void adc_enable_discontinuous_mode_injected(uint32_t adc)
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{
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ADC_CR1(adc) |= ADC_CR1_JDISCEN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Disable Discontinuous Mode for Injected Conversions
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@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
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*/
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void adc_disable_discontinuous_mode_injected(uint32_t adc)
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{
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ADC_CR1(adc) &= ~ADC_CR1_JDISCEN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Enable Automatic Injected Conversions
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The ADC converts a defined injected group of channels immediately after the
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regular channels have been converted. The external trigger on the injected
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channels is disabled as required.
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@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
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*/
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void adc_enable_automatic_injected_group_conversion(uint32_t adc)
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{
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adc_disable_external_trigger_injected(adc);
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ADC_CR1(adc) |= ADC_CR1_JAUTO;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Disable Automatic Injected Conversions
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@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
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*/
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void adc_disable_automatic_injected_group_conversion(uint32_t adc)
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{
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ADC_CR1(adc) &= ~ADC_CR1_JAUTO;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Enable Analog Watchdog for All Regular and/or Injected Channels
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The analog watchdog allows the monitoring of an analog signal between two
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threshold levels. The thresholds must be preset. Comparison is done before data
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alignment takes place, so the thresholds are left-aligned.
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@note The analog watchdog must be enabled for either or both of the regular or
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injected channels. If neither are enabled, the analog watchdog feature will be
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disabled.
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@ref adc_enable_analog_watchdog_injected, @ref
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adc_enable_analog_watchdog_regular.
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@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
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*/
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void adc_enable_analog_watchdog_on_all_channels(uint32_t adc)
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{
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ADC_CR1(adc) &= ~ADC_CR1_AWDSGL;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Enable Analog Watchdog for a Selected Channel
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The analog watchdog allows the monitoring of an analog signal between two
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threshold levels. The thresholds must be preset. Comparison is done before data
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alignment takes place, so the thresholds are left-aligned.
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@note The analog watchdog must be enabled for either or both of the regular or
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injected channels. If neither are enabled, the analog watchdog feature will be
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disabled. If both are enabled, the same channel number is monitored.
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@ref adc_enable_analog_watchdog_injected, @ref
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adc_enable_analog_watchdog_regular.
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@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
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@param[in] channel Unsigned int8. ADC channel number @ref adc_watchdog_channel
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*/
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void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc,
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uint8_t channel)
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{
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uint32_t reg32;
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reg32 = (ADC_CR1(adc) & ~ADC_CR1_AWDCH_MASK); /* Clear bits [4:0]. */
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if (channel <= ADC_CR1_AWDCH_MAX) {
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reg32 |= channel;
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}
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ADC_CR1(adc) = reg32;
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ADC_CR1(adc) |= ADC_CR1_AWDSGL;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Set Scan Mode
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In this mode a conversion consists of a scan of the predefined set of channels,
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regular and injected, each channel conversion immediately following the
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previous one. It can use single, continuous or discontinuous mode.
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@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
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*/
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void adc_enable_scan_mode(uint32_t adc)
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{
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ADC_CR1(adc) |= ADC_CR1_SCAN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Disable Scan Mode
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@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
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*/
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void adc_disable_scan_mode(uint32_t adc)
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{
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ADC_CR1(adc) &= ~ADC_CR1_SCAN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Enable Injected End-Of-Conversion Interrupt
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@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
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*/
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void adc_enable_eoc_interrupt_injected(uint32_t adc)
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{
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ADC_CR1(adc) |= ADC_CR1_JEOCIE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Disable Injected End-Of-Conversion Interrupt
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@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
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*/
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void adc_disable_eoc_interrupt_injected(uint32_t adc)
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{
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ADC_CR1(adc) &= ~ADC_CR1_JEOCIE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Enable Analog Watchdog Interrupt
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@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
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*/
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void adc_enable_awd_interrupt(uint32_t adc)
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{
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|
|
ADC_CR1(adc) |= ADC_CR1_AWDIE;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** @brief ADC Disable Analog Watchdog Interrupt
|
||
|
|
|
||
|
|
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||
|
|
*/
|
||
|
|
|
||
|
|
void adc_disable_awd_interrupt(uint32_t adc)
|
||
|
|
{
|
||
|
|
ADC_CR1(adc) &= ~ADC_CR1_AWDIE;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** @brief ADC Enable Regular End-Of-Conversion Interrupt
|
||
|
|
|
||
|
|
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||
|
|
*/
|
||
|
|
|
||
|
|
void adc_enable_eoc_interrupt(uint32_t adc)
|
||
|
|
{
|
||
|
|
ADC_CR1(adc) |= ADC_CR1_EOCIE;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** @brief ADC Disable Regular End-Of-Conversion Interrupt
|
||
|
|
|
||
|
|
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||
|
|
*/
|
||
|
|
|
||
|
|
void adc_disable_eoc_interrupt(uint32_t adc)
|
||
|
|
{
|
||
|
|
ADC_CR1(adc) &= ~ADC_CR1_EOCIE;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** @brief ADC Set the Data as Left Aligned
|
||
|
|
|
||
|
|
@param[in] adc Unsigned int32. ADC block register address base @ref
|
||
|
|
adc_reg_base.
|
||
|
|
*/
|
||
|
|
|
||
|
|
void adc_set_left_aligned(uint32_t adc)
|
||
|
|
{
|
||
|
|
ADC_CR2(adc) |= ADC_CR2_ALIGN;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** @brief ADC Set the Data as Right Aligned
|
||
|
|
|
||
|
|
@param[in] adc Unsigned int32. ADC block register address base @ref
|
||
|
|
adc_reg_base.
|
||
|
|
*/
|
||
|
|
|
||
|
|
void adc_set_right_aligned(uint32_t adc)
|
||
|
|
{
|
||
|
|
ADC_CR2(adc) &= ~ADC_CR2_ALIGN;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** @brief ADC Read the End-of-Conversion Flag
|
||
|
|
|
||
|
|
This flag is set after all channels of a regular or injected group have been
|
||
|
|
converted.
|
||
|
|
|
||
|
|
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||
|
|
@returns bool. End of conversion flag.
|
||
|
|
*/
|
||
|
|
|
||
|
|
bool adc_eoc(uint32_t adc)
|
||
|
|
{
|
||
|
|
return (ADC_SR(adc) & ADC_SR_EOC) != 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** @brief ADC Read the End-of-Conversion Flag for Injected Conversion
|
||
|
|
|
||
|
|
This flag is set after all channels of an injected group have been converted.
|
||
|
|
|
||
|
|
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||
|
|
@returns bool. End of conversion flag.
|
||
|
|
*/
|
||
|
|
|
||
|
|
bool adc_eoc_injected(uint32_t adc)
|
||
|
|
{
|
||
|
|
return (ADC_SR(adc) & ADC_SR_JEOC) != 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** @brief ADC Read from the Regular Conversion Result Register
|
||
|
|
|
||
|
|
The result read back is 12 bits, right or left aligned within the first 16 bits.
|
||
|
|
For ADC1 only, the higher 16 bits will hold the result from ADC2 if
|
||
|
|
an appropriate dual mode has been set @see adc_set_dual_mode.
|
||
|
|
|
||
|
|
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||
|
|
@returns Unsigned int32 conversion result.
|
||
|
|
*/
|
||
|
|
|
||
|
|
uint32_t adc_read_regular(uint32_t adc)
|
||
|
|
{
|
||
|
|
return ADC_DR(adc);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** @brief ADC Read from an Injected Conversion Result Register
|
||
|
|
|
||
|
|
The result read back from the selected injected result register (one of four)
|
||
|
|
is 12 bits, right or left aligned within the first 16 bits. The result can have
|
||
|
|
a negative value if the injected channel offset has been set @see
|
||
|
|
adc_set_injected_offset.
|
||
|
|
|
||
|
|
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||
|
|
@param[in] reg Unsigned int8. Register number (1 ... 4).
|
||
|
|
@returns Unsigned int32 conversion result.
|
||
|
|
*/
|
||
|
|
|
||
|
|
uint32_t adc_read_injected(uint32_t adc, uint8_t reg)
|
||
|
|
{
|
||
|
|
switch (reg) {
|
||
|
|
case 1:
|
||
|
|
return ADC_JDR1(adc);
|
||
|
|
case 2:
|
||
|
|
return ADC_JDR2(adc);
|
||
|
|
case 3:
|
||
|
|
return ADC_JDR3(adc);
|
||
|
|
case 4:
|
||
|
|
return ADC_JDR4(adc);
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** @brief ADC Enable Continuous Conversion Mode
|
||
|
|
|
||
|
|
In this mode the ADC starts a new conversion of a single channel or a channel
|
||
|
|
group immediately following completion of the previous channel group conversion.
|
||
|
|
|
||
|
|
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||
|
|
*/
|
||
|
|
|
||
|
|
void adc_set_continuous_conversion_mode(uint32_t adc)
|
||
|
|
{
|
||
|
|
ADC_CR2(adc) |= ADC_CR2_CONT;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** @brief ADC Enable Single Conversion Mode
|
||
|
|
|
||
|
|
In this mode the ADC performs a conversion of one channel or a channel group
|
||
|
|
and stops.
|
||
|
|
|
||
|
|
@param[in] adc Unsigned int32. ADC block register address base @ref
|
||
|
|
adc_reg_base.
|
||
|
|
*/
|
||
|
|
|
||
|
|
void adc_set_single_conversion_mode(uint32_t adc)
|
||
|
|
{
|
||
|
|
ADC_CR2(adc) &= ~ADC_CR2_CONT;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** @brief ADC Set Analog Watchdog Upper Threshold
|
||
|
|
|
||
|
|
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||
|
|
@param[in] threshold Upper threshold value, 12bit right aligned.
|
||
|
|
*/
|
||
|
|
|
||
|
|
void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold)
|
||
|
|
{
|
||
|
|
uint32_t reg32 = 0;
|
||
|
|
|
||
|
|
reg32 = (uint32_t)threshold;
|
||
|
|
reg32 &= ADC_HT_MSK;
|
||
|
|
ADC_HTR(adc) = reg32;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** @brief ADC Set Analog Watchdog Lower Threshold
|
||
|
|
|
||
|
|
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||
|
|
@param[in] threshold Lower threshold value, 12bit right aligned.
|
||
|
|
*/
|
||
|
|
|
||
|
|
void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold)
|
||
|
|
{
|
||
|
|
uint32_t reg32 = 0;
|
||
|
|
|
||
|
|
reg32 = (uint32_t)threshold;
|
||
|
|
reg32 &= ADC_LT_MSK;
|
||
|
|
ADC_LTR(adc) = reg32;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
|
||
|
|
/** @brief ADC Set a Regular Channel Conversion Sequence
|
||
|
|
|
||
|
|
Define a sequence of channels to be converted as a regular group with a length
|
||
|
|
from 1 to ADC_REGULAR_SEQUENCE_MAX channels. If this is called during
|
||
|
|
conversion, the current conversion is reset and conversion begins again with
|
||
|
|
the newly defined group.
|
||
|
|
|
||
|
|
@param[in] adc Unsigned int32. ADC block base address @ref adc_reg_base.
|
||
|
|
@param[in] length Unsigned int8. Number of channels in the group.
|
||
|
|
@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..31.
|
||
|
|
*/
|
||
|
|
|
||
|
|
void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
|
||
|
|
{
|
||
|
|
uint32_t fifth6 = 0;
|
||
|
|
uint32_t fourth6 = 0;
|
||
|
|
uint32_t third6 = 0;
|
||
|
|
uint32_t second6 = 0;
|
||
|
|
uint32_t first6 = 0;
|
||
|
|
uint8_t i = 0;
|
||
|
|
|
||
|
|
if (length > ADC_SQR_MAX_CHANNELS_REGULAR) {
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
for (i = 1; i <= length; i++) {
|
||
|
|
if (i <= 6) {
|
||
|
|
first6 |= (channel[i - 1] << ((i - 1) * 5));
|
||
|
|
}
|
||
|
|
if ((i > 6) && (i <= 12)) {
|
||
|
|
second6 |= (channel[i - 1] << ((i - 6 - 1) * 5));
|
||
|
|
}
|
||
|
|
if ((i > 12) && (i <= 18)) {
|
||
|
|
third6 |= (channel[i - 1] << ((i - 12 - 1) * 5));
|
||
|
|
}
|
||
|
|
if ((i > 18) && (i <= 24)) {
|
||
|
|
fourth6 |= (channel[i - 1] << ((i - 18 - 1) * 5));
|
||
|
|
}
|
||
|
|
if ((i > 24) && (i <= 28)) {
|
||
|
|
fifth6 |= (channel[i - 1] << ((i - 24 - 1) * 5));
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#if defined(ADC_SQR5)
|
||
|
|
ADC_SQR1(adc) = fifth6 | ((length - 1) << ADC_SQR1_L_LSB);
|
||
|
|
ADC_SQR2(adc) = fourth6;
|
||
|
|
ADC_SQR3(adc) = third6;
|
||
|
|
ADC_SQR4(adc) = second6;
|
||
|
|
ADC_SQR5(adc) = first6;
|
||
|
|
#else
|
||
|
|
ADC_SQR1(adc) = third6 | ((length - 1) << ADC_SQR1_L_LSB);
|
||
|
|
ADC_SQR2(adc) = second6;
|
||
|
|
ADC_SQR3(adc) = first6;
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** @brief ADC Set an Injected Channel Conversion Sequence
|
||
|
|
|
||
|
|
Defines a sequence of channels to be converted as an injected group with a
|
||
|
|
length from 1 to 4 channels. If this is called during conversion, the current
|
||
|
|
conversion is reset and conversion begins again with the newly defined group.
|
||
|
|
|
||
|
|
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||
|
|
@param[in] length Unsigned int8. Number of channels in the group.
|
||
|
|
@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18
|
||
|
|
*/
|
||
|
|
|
||
|
|
void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
|
||
|
|
{
|
||
|
|
uint32_t reg32 = 0;
|
||
|
|
uint8_t i = 0;
|
||
|
|
|
||
|
|
/* Maximum sequence length is 4 channels. Minimum sequence is 1.*/
|
||
|
|
if ((length - 1) > 3) {
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
for (i = 0; i < length; i++) {
|
||
|
|
reg32 |= ADC_JSQR_JSQ_VAL(4 - i, channel[length - i - 1]);
|
||
|
|
}
|
||
|
|
|
||
|
|
reg32 |= ADC_JSQR_JL_VAL(length);
|
||
|
|
|
||
|
|
ADC_JSQR(adc) = reg32;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/*----------------------------------------------------------------------------*/
|
||
|
|
/** @brief ADC Set the Injected Channel Data Offset
|
||
|
|
|
||
|
|
This value is subtracted from the injected channel results after conversion is
|
||
|
|
complete, and can result in negative results. A separate value can be specified
|
||
|
|
for each injected data register.
|
||
|
|
|
||
|
|
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||
|
|
@param[in] reg Unsigned int8. Register number (1 ... 4).
|
||
|
|
@param[in] offset Unsigned int32.
|
||
|
|
*/
|
||
|
|
|
||
|
|
void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset)
|
||
|
|
{
|
||
|
|
switch (reg) {
|
||
|
|
case 1:
|
||
|
|
ADC_JOFR1(adc) = offset;
|
||
|
|
break;
|
||
|
|
case 2:
|
||
|
|
ADC_JOFR2(adc) = offset;
|
||
|
|
break;
|
||
|
|
case 3:
|
||
|
|
ADC_JOFR3(adc) = offset;
|
||
|
|
break;
|
||
|
|
case 4:
|
||
|
|
ADC_JOFR4(adc) = offset;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** @brief ADC Software Triggered Conversion on Regular Channels
|
||
|
|
|
||
|
|
This starts conversion on a set of defined regular channels if the ADC trigger
|
||
|
|
is set to be a software trigger. It is cleared by hardware once conversion
|
||
|
|
starts.
|
||
|
|
|
||
|
|
Special F1 Note this is a software trigger and requires triggering to be
|
||
|
|
enabled and the trigger source to be set appropriately otherwise conversion
|
||
|
|
will not start. This is not the same as the ADC start conversion operation.
|
||
|
|
|
||
|
|
@param[in] adc Unsigned int32. ADC block register address base @ref
|
||
|
|
adc_reg_base.
|
||
|
|
*/
|
||
|
|
|
||
|
|
void adc_start_conversion_regular(uint32_t adc)
|
||
|
|
{
|
||
|
|
/* Start conversion on regular channels. */
|
||
|
|
ADC_CR2(adc) |= ADC_CR2_SWSTART;
|
||
|
|
|
||
|
|
/* Wait until the ADC starts the conversion. */
|
||
|
|
while (ADC_CR2(adc) & ADC_CR2_SWSTART);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** @brief ADC Software Triggered Conversion on Injected Channels
|
||
|
|
|
||
|
|
This starts conversion on a set of defined injected channels if the ADC trigger
|
||
|
|
is set to be a software trigger. It is cleared by hardware once conversion
|
||
|
|
starts.
|
||
|
|
|
||
|
|
Special F1 Note this is a software trigger and requires triggering to be
|
||
|
|
enabled and the trigger source to be set appropriately otherwise conversion
|
||
|
|
will not start. This is not the same as the ADC start conversion operation.
|
||
|
|
|
||
|
|
@param[in] adc Unsigned int32. ADC block register address base @ref
|
||
|
|
adc_reg_base.
|
||
|
|
*/
|
||
|
|
|
||
|
|
void adc_start_conversion_injected(uint32_t adc)
|
||
|
|
{
|
||
|
|
/* Start conversion on injected channels. */
|
||
|
|
ADC_CR2(adc) |= ADC_CR2_JSWSTART;
|
||
|
|
|
||
|
|
/* Wait until the ADC starts the conversion. */
|
||
|
|
while (ADC_CR2(adc) & ADC_CR2_JSWSTART);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** @brief ADC Enable DMA Transfers
|
||
|
|
|
||
|
|
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||
|
|
*/
|
||
|
|
|
||
|
|
void adc_enable_dma(uint32_t adc)
|
||
|
|
{
|
||
|
|
ADC_CR2(adc) |= ADC_CR2_DMA;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** @brief ADC Disable DMA Transfers
|
||
|
|
|
||
|
|
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||
|
|
*/
|
||
|
|
|
||
|
|
void adc_disable_dma(uint32_t adc)
|
||
|
|
{
|
||
|
|
ADC_CR2(adc) &= ~ADC_CR2_DMA;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** @brief Read a Status Flag.
|
||
|
|
|
||
|
|
@param[in] adc Unsigned int32. ADC register address base @ref adc_reg_base
|
||
|
|
@param[in] flag Unsigned int32. Status register flag @ref adc_sr_values.
|
||
|
|
@returns boolean: flag set.
|
||
|
|
*/
|
||
|
|
|
||
|
|
bool adc_get_flag(uint32_t adc, uint32_t flag)
|
||
|
|
{
|
||
|
|
return ADC_SR(adc) & flag;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** @brief Clear a Status Flag.
|
||
|
|
|
||
|
|
@param[in] adc Unsigned int32. ADC register address base @ref adc_reg_base
|
||
|
|
@param[in] flag Unsigned int32. Status register flag @ref adc_sr_values.
|
||
|
|
*/
|
||
|
|
|
||
|
|
void adc_clear_flag(uint32_t adc, uint32_t flag)
|
||
|
|
{
|
||
|
|
/* All defined bits are 'r' or 'rc_w0' */
|
||
|
|
ADC_SR(adc) = ~flag;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
|
||
|
|
/**@}*/
|