93 lines
2.8 KiB
C
93 lines
2.8 KiB
C
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h>
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/stm32/tools.h>
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#include <libopencm3/stm32/rcc.h>
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#include <libopencm3/usb/usbd.h>
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#include <libopencm3/usb/dwc/otg_hs.h>
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#include "usb_private.h"
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#include "usb_dwc_common.h"
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/* Receive FIFO size in 32-bit words. */
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#define RX_FIFO_SIZE 512
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static usbd_device *stm32f207_usbd_init(void);
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static struct _usbd_device usbd_dev;
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const struct _usbd_driver stm32f207_usb_driver = {
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.init = stm32f207_usbd_init,
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.set_address = dwc_set_address,
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.ep_setup = dwc_ep_setup,
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.ep_reset = dwc_endpoints_reset,
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.ep_stall_set = dwc_ep_stall_set,
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.ep_stall_get = dwc_ep_stall_get,
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.ep_nak_set = dwc_ep_nak_set,
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.ep_write_packet = dwc_ep_write_packet,
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.ep_read_packet = dwc_ep_read_packet,
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.poll = dwc_poll,
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.disconnect = dwc_disconnect,
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.base_address = USB_OTG_HS_BASE,
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.set_address_before_status = 1,
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.rx_fifo_size = RX_FIFO_SIZE,
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};
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/** Initialize the USB device controller hardware of the STM32. */
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static usbd_device *stm32f207_usbd_init(void)
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{
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rcc_periph_clock_enable(RCC_OTGHS);
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OTG_HS_GINTSTS = OTG_GINTSTS_MMIS;
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OTG_HS_GUSBCFG |= OTG_GUSBCFG_PHYSEL;
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/* Enable VBUS sensing in device mode and power down the PHY. */
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OTG_HS_GCCFG |= OTG_GCCFG_VBUSBSEN | OTG_GCCFG_PWRDWN;
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/* Wait for AHB idle. */
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while (!(OTG_HS_GRSTCTL & OTG_GRSTCTL_AHBIDL));
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/* Do core soft reset. */
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OTG_HS_GRSTCTL |= OTG_GRSTCTL_CSRST;
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while (OTG_HS_GRSTCTL & OTG_GRSTCTL_CSRST);
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/* Force peripheral only mode. */
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OTG_HS_GUSBCFG |= OTG_GUSBCFG_FDMOD | OTG_GUSBCFG_TRDT_MASK;
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/* Full speed device. */
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OTG_HS_DCFG |= OTG_DCFG_DSPD;
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/* Restart the PHY clock. */
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OTG_HS_PCGCCTL = 0;
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OTG_HS_GRXFSIZ = stm32f207_usb_driver.rx_fifo_size;
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usbd_dev.fifo_mem_top = stm32f207_usb_driver.rx_fifo_size;
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/* Unmask interrupts for TX and RX. */
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OTG_HS_GAHBCFG |= OTG_GAHBCFG_GINT;
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OTG_HS_GINTMSK = OTG_GINTMSK_ENUMDNEM |
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OTG_GINTMSK_RXFLVLM |
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OTG_GINTMSK_IEPINT |
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OTG_GINTMSK_USBSUSPM |
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OTG_GINTMSK_WUIM;
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OTG_HS_DAINTMSK = 0xF;
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OTG_HS_DIEPMSK = OTG_DIEPMSK_XFRCM;
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return &usbd_dev;
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}
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