|
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445 |
- !!omap
- - SSP0_CR0:
- fields: !!omap
- - DSS:
- access: rw
- description: Data Size Select
- lsb: 0
- reset_value: '0'
- width: 4
- - FRF:
- access: rw
- description: Frame Format
- lsb: 4
- reset_value: '0'
- width: 2
- - CPOL:
- access: rw
- description: Clock Out Polarity
- lsb: 6
- reset_value: '0'
- width: 1
- - CPHA:
- access: rw
- description: Clock Out Phase
- lsb: 7
- reset_value: '0'
- width: 1
- - SCR:
- access: rw
- description: Serial Clock Rate
- lsb: 8
- reset_value: '0'
- width: 8
- - SSP1_CR0:
- fields: !!omap
- - DSS:
- access: rw
- description: Data Size Select
- lsb: 0
- reset_value: '0'
- width: 4
- - FRF:
- access: rw
- description: Frame Format
- lsb: 4
- reset_value: '0'
- width: 2
- - CPOL:
- access: rw
- description: Clock Out Polarity
- lsb: 6
- reset_value: '0'
- width: 1
- - CPHA:
- access: rw
- description: Clock Out Phase
- lsb: 7
- reset_value: '0'
- width: 1
- - SCR:
- access: rw
- description: Serial Clock Rate
- lsb: 8
- reset_value: '0'
- width: 8
- - SSP0_CR1:
- fields: !!omap
- - LBM:
- access: rw
- description: Loop Back Mode
- lsb: 0
- reset_value: '0'
- width: 1
- - SSE:
- access: rw
- description: SSP Enable
- lsb: 1
- reset_value: '0'
- width: 1
- - MS:
- access: rw
- description: Master/Slave Mode
- lsb: 2
- reset_value: '0'
- width: 1
- - SOD:
- access: rw
- description: Slave Output Disable
- lsb: 3
- reset_value: '0'
- width: 1
- - SSP1_CR1:
- fields: !!omap
- - SSE:
- access: rw
- description: SSP Enable
- lsb: 1
- reset_value: '0'
- width: 1
- - MS:
- access: rw
- description: Master/Slave Mode
- lsb: 2
- reset_value: '0'
- width: 1
- - SOD:
- access: rw
- description: Slave Output Disable
- lsb: 3
- reset_value: '0'
- width: 1
- - SSP0_DR:
- fields: !!omap
- - DATA:
- access: rw
- description: Software can write data to be transmitted to this register, and
- read data that has been
- lsb: 0
- reset_value: '0'
- width: 16
- - SSP1_DR:
- fields: !!omap
- - DATA:
- access: rw
- description: Software can write data to be transmitted to this register, and
- read data that has been
- lsb: 0
- reset_value: '0'
- width: 16
- - SSP0_SR:
- fields: !!omap
- - TFE:
- access: r
- description: Transmit FIFO Empty
- lsb: 0
- reset_value: '1'
- width: 1
- - TNF:
- access: r
- description: Transmit FIFO Not Full
- lsb: 1
- reset_value: '1'
- width: 1
- - RNE:
- access: r
- description: Receive FIFO Not Empty
- lsb: 2
- reset_value: '0'
- width: 1
- - RFF:
- access: r
- description: Receive FIFO Full
- lsb: 3
- reset_value: '0'
- width: 1
- - BSY:
- access: r
- description: Busy.
- lsb: 4
- reset_value: '0'
- width: 1
- - SSP1_SR:
- fields: !!omap
- - TFE:
- access: r
- description: Transmit FIFO Empty
- lsb: 0
- reset_value: '1'
- width: 1
- - TNF:
- access: r
- description: Transmit FIFO Not Full
- lsb: 1
- reset_value: '1'
- width: 1
- - RNE:
- access: r
- description: Receive FIFO Not Empty
- lsb: 2
- reset_value: '0'
- width: 1
- - RFF:
- access: r
- description: Receive FIFO Full
- lsb: 3
- reset_value: '0'
- width: 1
- - BSY:
- access: r
- description: Busy.
- lsb: 4
- reset_value: '0'
- width: 1
- - SSP0_CPSR:
- fields: !!omap
- - CPSDVSR:
- access: rw
- description: SSP Clock Prescale Register
- lsb: 0
- reset_value: '0'
- width: 8
- - SSP1_CPSR:
- fields: !!omap
- - CPSDVSR:
- access: rw
- description: SSP Clock Prescale Register
- lsb: 0
- reset_value: '0'
- width: 8
- - SSP0_IMSC:
- fields: !!omap
- - RORIM:
- access: rw
- description: Software should set this bit to enable interrupt when a Receive
- Overrun occurs
- lsb: 0
- reset_value: '0'
- width: 1
- - RTIM:
- access: rw
- description: Software should set this bit to enable interrupt when a Receive
- Time-out condition occurs
- lsb: 1
- reset_value: '0'
- width: 1
- - RXIM:
- access: rw
- description: Software should set this bit to enable interrupt when the Rx
- FIFO is at least half full
- lsb: 2
- reset_value: '0'
- width: 1
- - TXIM:
- access: rw
- description: Software should set this bit to enable interrupt when the Tx
- FIFO is at least half empty
- lsb: 3
- reset_value: '0'
- width: 1
- - SSP1_IMSC:
- fields: !!omap
- - RORIM:
- access: rw
- description: Software should set this bit to enable interrupt when a Receive
- Overrun occurs
- lsb: 0
- reset_value: '0'
- width: 1
- - RTIM:
- access: rw
- description: Software should set this bit to enable interrupt when a Receive
- Time-out condition occurs
- lsb: 1
- reset_value: '0'
- width: 1
- - RXIM:
- access: rw
- description: Software should set this bit to enable interrupt when the Rx
- FIFO is at least half full
- lsb: 2
- reset_value: '0'
- width: 1
- - TXIM:
- access: rw
- description: Software should set this bit to enable interrupt when the Tx
- FIFO is at least half empty
- lsb: 3
- reset_value: '0'
- width: 1
- - SSP0_RIS:
- fields: !!omap
- - RORRIS:
- access: r
- description: This bit is 1 if another frame was completely received while
- the RxFIFO was full
- lsb: 0
- reset_value: '0'
- width: 1
- - RTRIS:
- access: r
- description: This bit is 1 if the Rx FIFO is not empty, and has not been read
- for a time-out period
- lsb: 1
- reset_value: '0'
- width: 1
- - RXRIS:
- access: r
- description: This bit is 1 if the Rx FIFO is at least half full
- lsb: 2
- reset_value: '0'
- width: 1
- - TXRIS:
- access: r
- description: This bit is 1 if the Tx FIFO is at least half empty
- lsb: 3
- reset_value: '1'
- width: 1
- - SSP1_RIS:
- fields: !!omap
- - RORRIS:
- access: r
- description: This bit is 1 if another frame was completely received while
- the RxFIFO was full
- lsb: 0
- reset_value: '0'
- width: 1
- - RTRIS:
- access: r
- description: This bit is 1 if the Rx FIFO is not empty, and has not been read
- for a time-out period
- lsb: 1
- reset_value: '0'
- width: 1
- - RXRIS:
- access: r
- description: This bit is 1 if the Rx FIFO is at least half full
- lsb: 2
- reset_value: '0'
- width: 1
- - TXRIS:
- access: r
- description: This bit is 1 if the Tx FIFO is at least half empty
- lsb: 3
- reset_value: '1'
- width: 1
- - SSP0_MIS:
- fields: !!omap
- - RORMIS:
- access: r
- description: This bit is 1 if another frame was completely received while
- the RxFIFO was full, and this interrupt is enabled
- lsb: 0
- reset_value: '0'
- width: 1
- - RTMIS:
- access: r
- description: This bit is 1 if the Rx FIFO is not empty, has not been read
- for a time-out period, and this interrupt is enabled
- lsb: 1
- reset_value: '0'
- width: 1
- - RXMIS:
- access: r
- description: This bit is 1 if the Rx FIFO is at least half full, and this
- interrupt is enabled
- lsb: 2
- reset_value: '0'
- width: 1
- - TXMIS:
- access: r
- description: This bit is 1 if the Tx FIFO is at least half empty, and this
- interrupt is enabled
- lsb: 3
- reset_value: '0'
- width: 1
- - SSP1_MIS:
- fields: !!omap
- - RORMIS:
- access: r
- description: This bit is 1 if another frame was completely received while
- the RxFIFO was full, and this interrupt is enabled
- lsb: 0
- reset_value: '0'
- width: 1
- - RTMIS:
- access: r
- description: This bit is 1 if the Rx FIFO is not empty, has not been read
- for a time-out period, and this interrupt is enabled
- lsb: 1
- reset_value: '0'
- width: 1
- - RXMIS:
- access: r
- description: This bit is 1 if the Rx FIFO is at least half full, and this
- interrupt is enabled
- lsb: 2
- reset_value: '0'
- width: 1
- - TXMIS:
- access: r
- description: This bit is 1 if the Tx FIFO is at least half empty, and this
- interrupt is enabled
- lsb: 3
- reset_value: '0'
- width: 1
- - SSP0_ICR:
- fields: !!omap
- - RORIC:
- access: w
- description: Writing a 1 to this bit clears the 'frame was received when RxFIFO
- was full' interrupt
- lsb: 0
- reset_value: ''
- width: 1
- - RTIC:
- access: w
- description: Writing a 1 to this bit clears the Rx FIFO was not empty and
- has not been read for a time-out period interrupt
- lsb: 1
- reset_value: ''
- width: 1
- - SSP1_ICR:
- fields: !!omap
- - RORIC:
- access: w
- description: Writing a 1 to this bit clears the 'frame was received when RxFIFO
- was full' interrupt
- lsb: 0
- reset_value: ''
- width: 1
- - RTIC:
- access: w
- description: Writing a 1 to this bit clears the Rx FIFO was not empty and
- has not been read for a time-out period interrupt
- lsb: 1
- reset_value: ''
- width: 1
- - SSP0_DMACR:
- fields: !!omap
- - RXDMAE:
- access: rw
- description: Receive DMA Enable
- lsb: 0
- reset_value: '0'
- width: 1
- - TXDMAE:
- access: rw
- description: Transmit DMA Enable
- lsb: 1
- reset_value: '0'
- width: 1
- - SSP1_DMACR:
- fields: !!omap
- - RXDMAE:
- access: rw
- description: Receive DMA Enable
- lsb: 0
- reset_value: '0'
- width: 1
- - TXDMAE:
- access: rw
- description: Transmit DMA Enable
- lsb: 1
- reset_value: '0'
- width: 1
|