Init

3rd/libopencm3/.gitignore

@@ -0,0 +1,68 @@
+*.d
+*.o
+*.bin
+*.hex
+*.list
+*.srec
+*.a
+*.elf
+lib/*.ld
+# (except this one!)
+!lib/cortex-m-generic.ld
+*.stylecheck
+*.swp
+\#*
+.\#*
+*~
+*.map
+*.log
+*.pyc
+html/
+latex/
+*.pdf
+*.tag
+.DS_Store
+# These are generated
+include/libopencm3/**/nvic.h
+include/libopencm3/**/**/nvic.h
+# (not these three though...)
+!include/libopencm3/cm3/nvic.h
+!include/libopencm3/dispatch/nvic.h
+!include/libopencm3/lm4f/nvic.h
+lib/**/vector_nvic.c
+lib/**/**/vector_nvic.c
+# (not this one either)
+!lib/dispatch/vector_nvic.c
+DoxygenLayout.xml
+doc/*/Doxyfile
+doc/*/DoxygenLayout_*.xml
+# (annnd, not these two templates either)
+!doc/templates/DoxygenLayout_Device.xml
+!doc/templates/DoxygenLayout_Root.xml
+doc/*/doxy.sourcelist
+include/libopencmsis/efm32/
+include/libopencmsis/gd32/
+include/libopencmsis/lm3s/
+include/libopencmsis/lpc13xx/
+include/libopencmsis/lpc17xx/
+include/libopencmsis/lpc43xx/
+include/libopencmsis/msp432/
+include/libopencmsis/pac55xx/
+include/libopencmsis/sam/
+include/libopencmsis/stm32/
+include/libopencmsis/swm050/
+include/libopencmsis/vf6xx/
+
+# Editor/IDE config files
+nbproject/
+.idea/
+.project
+locm3.sublime-workspace
+.cproject
+.settings
+
+# cscope databases
+cscope.out
+
+# build droppings
+.stamp_failure*

3rd/libopencm3/.travis.yml

@@ -0,0 +1,17 @@
+language: c
+script:
+  - make
+  - make -C tests/gadget-zero
+
+addons:
+  apt:
+    sources:
+    - sourceline: 'ppa:team-gcc-arm-embedded/ppa'
+    packages:
+    - gcc-arm-embedded
+
+notifications:
+  irc:
+    channels:
+      - "chat.freenode.net#libopencm3"
+    use_notice: true

3rd/libopencm3/COPYING.GPL3

@@ -0,0 +1,676 @@
+
+		    GNU GENERAL PUBLIC LICENSE
+		       Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
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+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License.  If you cannot convey a
+covered work so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you may
+not convey it at all.  For example, if you agree to terms that obligate you
+to collect a royalty for further conveying from those to whom you convey
+the Program, the only way you could satisfy both those terms and this
+License would be to refrain entirely from conveying the Program.
+
+  13. Use with the GNU Affero General Public License.
+
+  Notwithstanding any other provision of this License, you have
+permission to link or combine any covered work with a work licensed
+under version 3 of the GNU Affero General Public License into a single
+combined work, and to convey the resulting work.  The terms of this
+License will continue to apply to the part which is the covered work,
+but the special requirements of the GNU Affero General Public License,
+section 13, concerning interaction through a network will apply to the
+combination as such.
+
+  14. Revised Versions of this License.
+
+  The Free Software Foundation may publish revised and/or new versions of
+the GNU General Public License from time to time.  Such new versions will
+be similar in spirit to the present version, but may differ in detail to
+address new problems or concerns.
+
+  Each version is given a distinguishing version number.  If the
+Program specifies that a certain numbered version of the GNU General
+Public License "or any later version" applies to it, you have the
+option of following the terms and conditions either of that numbered
+version or of any later version published by the Free Software
+Foundation.  If the Program does not specify a version number of the
+GNU General Public License, you may choose any version ever published
+by the Free Software Foundation.
+
+  If the Program specifies that a proxy can decide which future
+versions of the GNU General Public License can be used, that proxy's
+public statement of acceptance of a version permanently authorizes you
+to choose that version for the Program.
+
+  Later license versions may give you additional or different
+permissions.  However, no additional obligations are imposed on any
+author or copyright holder as a result of your choosing to follow a
+later version.
+
+  15. Disclaimer of Warranty.
+
+  THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
+APPLICABLE LAW.  EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
+HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
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+THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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+IS WITH YOU.  SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
+ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
+
+  16. Limitation of Liability.
+
+  IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
+THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
+GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
+USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
+DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
+PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
+EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
+SUCH DAMAGES.
+
+  17. Interpretation of Sections 15 and 16.
+
+  If the disclaimer of warranty and limitation of liability provided
+above cannot be given local legal effect according to their terms,
+reviewing courts shall apply local law that most closely approximates
+an absolute waiver of all civil liability in connection with the
+Program, unless a warranty or assumption of liability accompanies a
+copy of the Program in return for a fee.
+
+		     END OF TERMS AND CONDITIONS
+
+	    How to Apply These Terms to Your New Programs
+
+  If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+  To do so, attach the following notices to the program.  It is safest
+to attach them to the start of each source file to most effectively
+state the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+    <one line to give the program's name and a brief idea of what it does.>
+    Copyright (C) <year>  <name of author>
+
+    This program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+Also add information on how to contact you by electronic and paper mail.
+
+  If the program does terminal interaction, make it output a short
+notice like this when it starts in an interactive mode:
+
+    <program>  Copyright (C) <year>  <name of author>
+    This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+    This is free software, and you are welcome to redistribute it
+    under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License.  Of course, your program's commands
+might be different; for a GUI interface, you would use an "about box".
+
+  You should also get your employer (if you work as a programmer) or school,
+if any, to sign a "copyright disclaimer" for the program, if necessary.
+For more information on this, and how to apply and follow the GNU GPL, see
+<http://www.gnu.org/licenses/>.
+
+  The GNU General Public License does not permit incorporating your program
+into proprietary programs.  If your program is a subroutine library, you
+may consider it more useful to permit linking proprietary applications with
+the library.  If this is what you want to do, use the GNU Lesser General
+Public License instead of this License.  But first, please read
+<http://www.gnu.org/philosophy/why-not-lgpl.html>.
+

3rd/libopencm3/COPYING.LGPL3

@@ -0,0 +1,165 @@
+                   GNU LESSER GENERAL PUBLIC LICENSE
+                       Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+
+  This version of the GNU Lesser General Public License incorporates
+the terms and conditions of version 3 of the GNU General Public
+License, supplemented by the additional permissions listed below.
+
+  0. Additional Definitions.
+
+  As used herein, "this License" refers to version 3 of the GNU Lesser
+General Public License, and the "GNU GPL" refers to version 3 of the GNU
+General Public License.
+
+  "The Library" refers to a covered work governed by this License,
+other than an Application or a Combined Work as defined below.
+
+  An "Application" is any work that makes use of an interface provided
+by the Library, but which is not otherwise based on the Library.
+Defining a subclass of a class defined by the Library is deemed a mode
+of using an interface provided by the Library.
+
+  A "Combined Work" is a work produced by combining or linking an
+Application with the Library.  The particular version of the Library
+with which the Combined Work was made is also called the "Linked
+Version".
+
+  The "Minimal Corresponding Source" for a Combined Work means the
+Corresponding Source for the Combined Work, excluding any source code
+for portions of the Combined Work that, considered in isolation, are
+based on the Application, and not on the Linked Version.
+
+  The "Corresponding Application Code" for a Combined Work means the
+object code and/or source code for the Application, including any data
+and utility programs needed for reproducing the Combined Work from the
+Application, but excluding the System Libraries of the Combined Work.
+
+  1. Exception to Section 3 of the GNU GPL.
+
+  You may convey a covered work under sections 3 and 4 of this License
+without being bound by section 3 of the GNU GPL.
+
+  2. Conveying Modified Versions.
+
+  If you modify a copy of the Library, and, in your modifications, a
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+
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+   function or data, the facility still operates, and performs
+   whatever part of its purpose remains meaningful, or
+
+   b) under the GNU GPL, with none of the additional permissions of
+   this License applicable to that copy.
+
+  3. Object Code Incorporating Material from Library Header Files.
+
+  The object code form of an Application may incorporate material from
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+(ten or fewer lines in length), you do both of the following:
+
+   a) Give prominent notice with each copy of the object code that the
+   Library is used in it and that the Library and its use are
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+
+   b) Accompany the object code with a copy of the GNU GPL and this license
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+
+  4. Combined Works.
+
+  You may convey a Combined Work under terms of your choice that,
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+   a) Give prominent notice with each copy of the Combined Work that
+   the Library is used in it and that the Library and its use are
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+   e) Provide Installation Information, but only if you would otherwise
+   be required to provide such information under section 6 of the
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+   Combined Work produced by recombining or relinking the
+   Application with a modified version of the Linked Version. (If
+   you use option 4d0, the Installation Information must accompany
+   the Minimal Corresponding Source and Corresponding Application
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+   Information in the manner specified by section 6 of the GNU GPL
+   for conveying Corresponding Source.)
+
+  5. Combined Libraries.
+
+  You may place library facilities that are a work based on the
+Library side by side in a single library together with other library
+facilities that are not Applications and are not covered by this
+License, and convey such a combined library under terms of your
+choice, if you do both of the following:
+
+   a) Accompany the combined library with a copy of the same work based
+   on the Library, uncombined with any other library facilities,
+   conveyed under the terms of this License.
+
+   b) Give prominent notice with the combined library that part of it
+   is a work based on the Library, and explaining where to find the
+   accompanying uncombined form of the same work.
+
+  6. Revised Versions of the GNU Lesser General Public License.
+
+  The Free Software Foundation may publish revised and/or new versions
+of the GNU Lesser General Public License from time to time. Such new
+versions will be similar in spirit to the present version, but may
+differ in detail to address new problems or concerns.
+
+  Each version is given a distinguishing version number. If the
+Library as you received it specifies that a certain numbered version
+of the GNU Lesser General Public License "or any later version"
+applies to it, you have the option of following the terms and
+conditions either of that published version or of any later version
+published by the Free Software Foundation. If the Library as you
+received it does not specify a version number of the GNU Lesser
+General Public License, you may choose any version of the GNU Lesser
+General Public License ever published by the Free Software Foundation.
+
+  If the Library as you received it specifies that a proxy can decide
+whether future versions of the GNU Lesser General Public License shall
+apply, that proxy's public statement of acceptance of any version is
+permanent authorization for you to choose that version for the
+Library.

3rd/libopencm3/HACKING

@@ -0,0 +1,85 @@
+------------------------------------------------------------------------------
+HACKING
+------------------------------------------------------------------------------
+
+Coding style
+------------
+
+The whole library is programmed using the Linux kernel coding style, see
+https://www.kernel.org/doc/html/latest/process/coding-style.html for details.
+
+Please use the same style for any code contributions, thanks!
+
+Amendments to the Linux kernel coding style
+-------------------------------------------
+
+1) We use the stdint types. The linux kernel accepts the abbreviated types (u8,
+   s8, u16 and so on) for legacy reasons. We should in general not introduce
+   things like types ourselves as long as they are not necessary to make our
+   job possible of refining the hardware and make it easier to be used. stdint
+   is a standard and it is not in the scope of our project to introduce a new
+   type standard.
+
+2) Based on the same logic as in (1) we do not use __packed and __aligned
+   definitions, it is not our job to add compiler extensions. If we need to
+   deal with compiler incompatibility we will do that the same way we are
+   dealing with the deprecated attribute by introducing a normal macro that is
+   not in the compiler reserved keyword space.
+
+3) We accept to write an empty body busy waiting while loop like this:
+	while (1);
+   there is no need to put the colon on the next line as per linux kernel
+   style.
+
+4) We always add brackets around bodies of if, while and for statements, even
+   if the body contains only one expression. It is dangerous to not have them
+   as it easily happens that one adds a second expression and is hunting for
+   hours why the code is not working just because of a missing bracket pair.
+
+Development guidelines
+----------------------
+
+ - Every new file added must have the usual license header, see the
+   existing files for examples.
+
+ - In general, please try to keep the register and bit naming as close
+   as possible to the official vendor datasheets. Among other reasons, this
+   makes it easier for users to find what they're looking for in the
+   datasheets, programming manuals, and application notes.
+
+ - All register definitions should follow the following naming conventions:
+
+   - The #define names should be all-caps, parts are separated by
+     an underscore.
+
+   - The name should be of the form SUBSYSTEM_REGISTER_BIT, e.g.
+     ADC_CR2_DMA, where ADC is the subsystem name, CR2 is the register NAME,
+     and DMA is the name of the bit in the register that is defined.
+
+ - All subsystem-specific function names should be prefixed with the
+   subsystem name. For example, gpio_set_mode() or rcc_osc_on().
+
+ - Please consistently use the stdint types.
+
+ - Variables that are used to store register values read from registers or
+   to be stored in a register should be named reg8, reg16, reg32 etc.
+
+ - For examples on using libopencm3 see the libopencm3-examples repository.
+
+ - Doxygen is used to generate API docs, please follow that style for function
+   and definition commentary where possible.
+
+Tips and tricks
+---------------
+
+SublimeText users:
+
+ - The project contains a sublime project description file with some basic
+   settings provided to make hacking on libopencm3 easier.
+
+ - Recommended SublimeText plugins when hacking on libopencm3:
+
+   - TrailingSpaces: Show and trim trailing line spaces.
+
+   - SublimeLinter: Run checkpatch.pl in the background while you write your
+     code and indicate possible coding style issues on the fly.

3rd/libopencm3/HACKING_COMMON_DOC

@@ -0,0 +1,76 @@
+Files for each peripheral (examples given for STM32 GPIO)
+---------------------------------------------------------
+
+In include/libopencm3/stm32.
+A "dispatch" header to point to the subfamily header (gpio.h)
+
+In include/libopencm3/stm32/f*
+A file with defines that are specific to the subfamily, and an include of
+needed common header files (gpio.h).
+
+In include/libopencm3/stm32/common
+A file with defines common to all subfamilies. Includes the cm3 common header
+(gpio_common_all.h).
+
+In include/libopencm3/stm32/common
+May be one other file with defines common to a subgroup of devices.
+This includes the file common to all (gpio_common_f24.h).
+
+In lib/stm32/f*
+A file with functions specific to the subfamily. Includes the "dispatch" header
+and any common headers needed (gpio.c).
+
+In lib/stm32/common
+Has functions common to all subfamilies. Includes the "dispatch" header
+(gpio_common_all.c).
+
+In lib/stm32/common
+May be one other file with functions common to a group of subfamilies. Includes
+the "dispatch" header and the file common to all (gpio_common_f24.h).
+
+Makefiles in lib/stm32/f? have the common object files added and the
+common directory added to VPATH.
+
+NOTE: The common source files MUST have the "dispatch" header so that
+compilation will use the specific defines for the subfamily being compiled.
+These can differ between subfamilies.
+
+NOTE: The common source files must have a line of the form
+
+#ifdef LIBOPENCM3_xxx_H
+
+where xxx is the associated peripheral name. This prevents the common files
+from being included accidentally into a user's application. This however
+causes doxygen to skip processing of the remainder of the file. Thus a
+
+@cond ... @endcond
+
+directive must be placed around the statement to prevent doxygen from
+processing it. This works only for doxygen 1.8.4 or later. At the present
+time most distros have an earlier buggy version.
+
+Documentation
+-------------
+
+In include/libopencm3/stm32/f*
+A file doc-stm32f*.h contains a definition of the particular family grouping.
+This grouping will appear in the main index of the resulting document with all
+documentation under it.
+
+All header files for a peripheral (common or otherwise) will subgroup under a
+name which is the same in all families (such as gpio_defines). The peripheral
+header file in include/libopencm3/stm32/f* will then include this group as a
+subgroup under the specific family group. Doxygen is run separately for each
+family so there is no danger of accidentally including the wrong stuff.
+
+Similarly for the source files for a peripheral which will subgroup under a
+same name (such as gpio_files). The peripheral source file in lib/stm32/f*
+will include this as a subgroup under the specific family group.
+
+DOXYFILE for a particular family will list the family specific and common files
+(headers and source) that are to be included. The result (in the long run) will
+be that all peripherals will appear under the same family grouping in the
+documentation, even if they are identical over a number of families. That is
+probably most useful to end users who only need to see the documentation for
+one family.
+

3rd/libopencm3/Makefile

@@ -0,0 +1,128 @@
+##
+## This file is part of the libopencm3 project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This library is free software: you can redistribute it and/or modify
+## it under the terms of the GNU Lesser General Public License as published by
+## the Free Software Foundation, either version 3 of the License, or
+## (at your option) any later version.
+##
+## This library is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU Lesser General Public License for more details.
+##
+## You should have received a copy of the GNU Lesser General Public License
+## along with this library.  If not, see <http://www.gnu.org/licenses/>.
+##
+
+PREFIX		?= arm-none-eabi-
+
+STYLECHECK      := scripts/checkpatch.pl
+STYLECHECKFLAGS := --no-tree -f --terse --mailback
+
+TARGETS ?=	stm32/f0 stm32/f1 stm32/f2 stm32/f3 stm32/f4 stm32/f7 \
+		stm32/l0 stm32/l1 stm32/l4 \
+		stm32/g0 stm32/g4 \
+		stm32/h7 \
+		gd32/f1x0 \
+		lpc13xx lpc17xx lpc43xx/m4 lpc43xx/m0 \
+		lm3s lm4f msp432/e4 \
+		efm32/tg efm32/g efm32/lg efm32/gg efm32/hg efm32/wg \
+		efm32/ezr32wg \
+		sam/3a sam/3n sam/3s sam/3u sam/3x sam/4l \
+		sam/d \
+		vf6xx \
+		swm050 \
+		pac55xx
+
+# Be silent per default, but 'make V=1' will show all compiler calls.
+ifneq ($(V),1)
+Q := @
+# Do not print "Entering directory ...".
+MAKEFLAGS += --no-print-directory
+endif
+
+# Avoid the use of shell find, for windows compatibility
+IRQ_DEFN_FILES  := $(foreach TARGET,$(TARGETS),$(wildcard include/libopencm3/$(TARGET)/irq.json))
+NVIC_H := $(IRQ_DEFN_FILES:%/irq.json=%/nvic.h)
+VECTOR_NVIC_C := $(IRQ_DEFN_FILES:./include/libopencm3/%/irq.json=./lib/%/vector_nvic.c)
+IRQHANDLERS_H := $(IRQ_DEFN_FILES:./include/libopencm3/%/irq.json=./include/libopencmsis/%/irqhandlers.h)
+IRQ_GENERATED_FILES = $(NVIC_H) $(VECTOR_NVIC_C) $(IRQHANDLERS_H)
+STYLECHECKFILES := $(wildcard include/*/*.h include/*/*/*.h include/*/*/*/*.h)
+STYLECHECKFILES += $(wildcard lib/*/*.h lib/*/*/*.h lib/*/*/*/*.h)
+STYLECHECKFILES += $(wildcard lib/*/*.c lib/*/*/*.c lib/*/*/*/*.c)
+
+all: build
+
+build: lib
+
+include/libopencm3/%/nvic.h lib/%/vector_nvic.c include/libopencmsis/%/irqhandlers.h: include/libopencm3/%/irq.json ./scripts/irq2nvic_h
+	@printf "  GENHDR  $*\n";
+	$(Q)./scripts/irq2nvic_h ./$<;
+
+%.cleanhdr:
+	@printf "  CLNHDR  $*\n";
+	$(Q)./scripts/irq2nvic_h --remove ./$*
+
+LIB_DIRS:=$(wildcard $(addprefix lib/,$(TARGETS)))
+$(LIB_DIRS): $(IRQ_GENERATED_FILES)
+	$(Q)$(RM) .stamp_failure_$(subst /,_,$@)
+	@printf "  BUILD   $@\n";
+	$(Q)$(MAKE) --directory=$@ PREFIX="$(PREFIX)" || \
+		echo "Failure building: $@: code: $$?" > .stamp_failure_$(subst /,_,$@)
+
+lib: $(LIB_DIRS)
+	$(Q)$(RM) .stamp_failure_tld
+	$(Q)for failure in .stamp_failure_*; do \
+		[ -f $$failure ] && cat $$failure >> .stamp_failure_tld || true; \
+	done;
+	$(Q)[ -f .stamp_failure_tld ] && cat .stamp_failure_tld && exit 1 || true;
+
+html doc:
+	$(Q)$(MAKE) -C doc html TARGETS="$(TARGETS)"
+
+clean: $(IRQ_DEFN_FILES:=.cleanhdr) $(LIB_DIRS:=.clean) $(EXAMPLE_DIRS:=.clean) doc.clean styleclean genlinktests.clean
+
+%.clean:
+	$(Q)if [ -d $* ]; then \
+		printf "  CLEAN   $*\n"; \
+		$(MAKE) -C $* clean || exit $?; \
+	fi;
+	$(Q)$(RM) .stamp_failure_*;
+
+
+stylecheck: $(STYLECHECKFILES:=.stylecheck)
+styleclean: $(STYLECHECKFILES:=.styleclean)
+
+# the cat is due to multithreaded nature - we like to have consistent chunks of text on the output
+%.stylecheck: %
+	$(Q)if ! grep -q "* It was generated by the irq2nvic_h script." $* ; then \
+		$(STYLECHECK) $(STYLECHECKFLAGS) $* > $*.stylecheck; \
+		if [ -s $*.stylecheck ]; then \
+			cat $*.stylecheck; \
+		else \
+			rm -f $*.stylecheck; \
+		fi; \
+	fi;
+
+%.styleclean:
+	$(Q)rm -f $*.stylecheck;
+
+
+LDTESTS		:=$(wildcard ld/tests/*.data)
+
+genlinktests: $(LDTESTS:.data=.ldtest)
+genlinktests.clean:
+	$(Q)rm -f $(LDTESTS:.data=.out)
+
+%.ldtest:
+	@if ./scripts/genlinktest.sh $* >/dev/null; then\
+		printf "  TEST  OK  : $*\n";		\
+	else						\
+		printf "  TEST FAIL : $*\n";		\
+	fi;
+
+
+.PHONY: build lib $(LIB_DIRS) doc clean generatedheaders cleanheaders stylecheck genlinktests genlinktests.clean

3rd/libopencm3/README.md

@@ -0,0 +1,198 @@
+README
+======
+[![Build Status](https://travis-ci.org/libopencm3/libopencm3.svg?branch=master)](https://travis-ci.org/libopencm3/libopencm3)
+
+[![Gitter channel](https://badges.gitter.im/libopencm3/discuss.svg)](https://gitter.im/libopencm3/discuss)
+
+The libopencm3 project aims to create an open-source firmware library for
+various ARM Cortex-M microcontrollers.
+
+Currently (at least partly) supported microcontrollers:
+
+ - ST STM32 F0xx/F1xx/F2xx/F30x/F37x/F4xx/F7xx/H7xx series
+ - ST STM32 G0xx G4xx L0xx L1xx L4xx series
+ - Atmel SAM3A/3N/3S/3U/3X series, as well as SAMDxx and friends
+ - NXP LPC1311/13/17/42/43
+ - Stellaris LM3S series (discontinued, without replacement)
+ - TI (Tiva) LM4F series (continuing as TM4F, pin and peripheral compatible)
+ - EFM32 Gecko series (only core support)
+ - Freescale Vybrid VF6xx
+ - Qorvo (formerly ActiveSemi) PAC55XX
+ - Synwit SWM050
+
+The library is written completely from scratch based on the vendor datasheets,
+programming manuals, and application notes. The code is meant to be used
+with a GCC toolchain for ARM (arm-elf or arm-none-eabi), flashing of the
+code to a microcontroller can be done using the OpenOCD ARM JTAG software.
+
+
+Status and API
+--------------
+
+The libopencm3 project is currently work in progress. Not all subsystems
+of the microcontrollers are supported, yet.
+
+**IMPORTANT**: The API of the library is _NOT_ yet considered stable! Please do
+           not rely on it, yet! Changes to function names, macro names, etc.
+           can happen at any time without prior notice!
+
+_TIP_: Include this repository as a Git submodule in your project to make sure
+     your users get the right version of the library to compile your project.
+     For how that can be done refer to the
+     [libopencm3-template](https://github.com/libopencm3/libopencm3-template) repository.
+
+Prerequisites
+-------------
+
+Building requires Python (some code is generated).
+
+**For Ubuntu/Fedora:**
+
+ - An arm-none-eabi/arm-elf toolchain.
+
+**For Windows:**
+
+ Download and install:
+
+ - msys - http://sourceforge.net/projects/mingw/files/MSYS/Base/msys-core/msys-1.0.11/MSYS-1.0.11.exe
+ - Python - http://www.python.org/ftp/python/2.7/python-2.7.msi (any 2.7 release)
+ - arm-none-eabi/arm-elf toolchain (for example this one https://launchpad.net/gcc-arm-embedded)
+
+Run msys shell and set the path without standard Windows paths, so Windows programs such as 'find' won't interfere:
+
+    export PATH="/c//Python27:/c/ARMToolchain/bin:/usr/local/bin:/usr/bin:/bin"
+
+After that you can navigate to the folder where you've extracted libopencm3 and build it.
+
+Toolchain
+---------
+
+The most heavily tested toolchain is "gcc-arm-embedded"
+https://launchpad.net/gcc-arm-embedded
+
+Other toolchains _should_ work, but they have not been nearly as well tested.
+Toolchains targeting Linux, such as "gcc-arm-linux-gnu" or the like are
+_not_ appropriate.
+
+_NOTE_: We recommend that you use gcc-arm-embedded version 4.8 2014q3 or newer
+to build all platforms covered by libopencm3 successfully.
+
+Building
+--------
+
+    $ make
+
+If you have an arm-elf toolchain (uncommon) you may want to override the
+toolchain prefix (arm-none-eabi is the default)
+
+    $ PREFIX=arm-elf make
+
+For a more verbose build you can use
+
+    $ make V=1
+
+Fine-tuning the build
+---------------------
+
+The build may be fine-tuned with a limited number of parameters, by specifying
+them as environment variables, for example:
+
+    $ VARIABLE=value make
+
+* `FP_FLAGS` - Control the floating-point ABI
+
+   If the Cortex-M core supports a hard float ABI, it will be compiled with
+   the best floating-point support by default. In cases where this is not desired, the
+   behavior can be specified by setting `FP_FLAGS`.
+   
+   Currently, M4F cores default to `-mfloat-abi=hard -mfpu=fpv4-sp-d16`, and
+   M7 cores defaults to double precision `-mfloat-abi=hard -mfpu=fpv5-d16` if available,
+   and single precision `-mfloat-abi=hard -mfpu=fpv5-sp-d16` otherwise.
+   Other architectures use no FP flags, in otherwords, traditional softfp.
+   
+   You may find which FP_FLAGS you can use in a particular architecture in the readme.txt 
+   file shipped with the gcc-arm-embedded package.
+
+   Examples:
+
+        $ FP_FLAGS="-mfloat-abi=soft" make               # No hardfloat
+        $ FP_FLAGS="-mfloat-abi=hard -mfpu=magic" make   # New FPU we don't know of
+
+* `CFLAGS` - Add to or supersede compiler flags
+
+   If the library needs to be compiled with additional flags, they can be
+   passed to the build system via the environment variable `CFLAGS`. The
+   contents of `CFLAGS` will be placed after all flags defined by the build
+   system, giving the user a way to override any default if necessary.
+
+   Examples:
+
+        $ CFLAGS="-fshort-wchar" make    # Compile lib with 2 byte wide wchar_t
+
+Example projects
+----------------
+
+The libopencm3 community has written and is maintaining a huge collection of
+examples, displaying the capabilities and uses of the library. You can find all
+of them in the libopencm3-examples repository:
+
+https://github.com/libopencm3/libopencm3-examples
+
+If you just wish to test your toolchain and build environment, a collection of
+mini blink projects is available too.  This covers _many_ more boards, but, as
+the name suggests, only demonstrates blinking LEDs.
+
+
+https://github.com/libopencm3/libopencm3-miniblink
+
+Installation
+------------
+
+Simply pass -I and -L flags to your own project.  See the
+[libopencm3-template](https://github.com/libopencm3/libopencm3-template)
+repository for a template repository using this library as a Git submodule,
+the most popular method of use.  The libopencm3-examples is another
+example of this.
+
+It is strongly advised that you do not attempt to install this library to any
+path inside your toolchain itself.  While this means you don't have to include
+any `-I` or `-L` flags in your projects, it is _very_ easy to confuse a multi-library
+linker from picking the right versions of libraries.  Common symptoms are
+hardfaults caused by branches into ARM code.  You can use `arm-none-eabi-objdump`
+to check for this in your final ELF file.  You have been warned.
+
+Coding style and development guidelines
+---------------------------------------
+
+See HACKING.
+
+
+License
+-------
+
+The libopencm3 code is released under the terms of the GNU Lesser General
+Public License (LGPL), version 3 or later.
+
+See COPYING.GPL3 and COPYING.LGPL3 for details.
+
+Community
+---------
+
+ * Our [![Gitter channel](https://badges.gitter.im/libopencm3/discuss.svg)](https://gitter.im/libopencm3/discuss)
+ * Our IRC channel on the freenode IRC network is called #libopencm3
+
+Mailing lists
+-------------
+
+ * Developer mailing list (for patches and discussions):
+   https://lists.sourceforge.net/lists/listinfo/libopencm3-devel
+
+ * Commits mailing list (receives one mail per `git push`):
+   https://lists.sourceforge.net/lists/listinfo/libopencm3-commits
+
+
+Website
+-------
+
+ * http://libopencm3.org
+

3rd/libopencm3/doc/Doxyfile

@@ -0,0 +1,21 @@
+# Doxygen include file to generate top level entry document
+
+# 14 September 2012
+# (C) Ken Sarkies <ksarkies@internode.on.net>
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE 			   = ./Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+INPUT                  = ../include/libopencm3/docmain.dox
+
+LAYOUT_FILE 		   = DoxygenLayout.xml
+
+GENERATE_LATEX		   = NO
+

3rd/libopencm3/doc/HACKING

@@ -0,0 +1,106 @@
+libopencm3 Documentation
+12 October 2012 (C) K Sarkies
+-----------------------------
+
+Each family and subfamily of devices has a separate directory and configuration
+files. Doxygen is run independently on each of these and the result is
+integrated under a single HTML page. 
+Due to relative referencing used in the files, the directory
+structure is important and should be maintained.
+The Makefile will automatically generate the list of input files based on the
+current library makefiles, so you _must_ have run built the library itself first.
+
+Each of the subdirectories has a configuration file, a layout file and
+subdirectories for the documentation. Doxygen is intended to be run inside
+these subdirectories. The Makefile will handle this in the appropriate
+order.
+
+Markup
+------
+
+Each family has been given a group name that will allow subgrouping of API
+functions and defines in the documentation.
+
+The header and source files for each peripheral in each family must have a
+heading section in which an @defgroup defines the group name for the particular
+peripheral. This group name will be the same across all families as each one
+is documented separately. Thus for a peripheral xxx the header will have a
+group name xxx_defines and the source file will have xxx_file. This will allow
+the group to appear separately. An @ingroup must be provided to place the group
+as a subgroup of the appropriate family grouping. Note that @file is not used.
+
+The heading section must include the version number and date and authors names
+plus a license reference. Any documentation specific to the family can be
+included here. If there are common files included then their documentation will
+appear in a separate section.
+
+Common header and source files that are included into a number of families must
+have an @addgroup to include its documentation into the appropriate peripheral
+group. These headings may include authors and any specific descriptions but the
+date and version number must be omitted as it will be included from the family
+files. There must not be any reference to family groupings as these common files
+will be incorporated into multiple family groups.
+
+The common files should not be included in an application explicitly. Also the
+doxygen preprocessor must be enabled to ensure that all macros and defines are
+included. This means that common header files need to have a section at the top 
+of the file of the type (eg for gpio_common_f24.h):
+
+/** @cond */
+#ifdef LIBOPENCM3_GPIO_H
+/** @endcond */
+
+and at the end of the file:
+
+/** @cond */
+#else
+#warning "gpio_common_f24.h should not be included explicitly, only via gpio.h"
+#endif
+/** @endcond */
+
+This will stop the compiler preprocessor from including the common header file
+unless the device family header file has also been included. The doxygen
+conditional clauses are needed to stop the doxygen preprocessor seeing this
+statement and so excluding processing of the common file contents.
+
+/** @cond */
+#if defined(LIBOPENCM3_GPIO_H) || defined(LIBOPENCM3_GPIO_COMMON_F24_H)
+/** @endcond */
+
+Each helper function must have a header with an @brief, and where appropriate
+additional description, @parameter and @return elements. These latter must
+describe the allowable parameter ranges preferably with reference to a suitable
+define in the corresponding header file.
+
+The Doxyfile for a family must include input files from the header and source
+subdirectories, as well as all needed common files. The common files can be
+added separately or as an entire directory with exclusions of inappropriate
+files.
+
+Doxyfiles
+---------
+
+Doxyfile_common holds global settings.
+
+OUTPUT_DIRECTORY blank so that the output is placed in the current directory.
+RECURSIVE = NO
+EXTERNAL_GROUPS = NO
+
+Each Doxyfile_include for a processor family has:
+
+@INCLUDE = ../Doxyfile_common
+INPUT = specific directories needed, including /include/libopencm3/cm3
+		in top directory to set the top level page and GNU license.
+LAYOUT_FILE = DoxygenLayout_$processor.xml
+WARN_LOGFILE = doxygen_$processor.log
+TAGFILES = ../cm3/cm3.tag=../../cm3/html
+GENERATE_TAGFILE = $processor.tag
+PREDEFINED = list of macro definitions
+
+For the top level Doxyfile
+
+INPUT = ../include/libopencm3/docmain.dox to add in the main page text
+LAYOUT_FILE = DoxygenLayout.xml
+WARN_LOGFILE = doxygen.log
+TAGFILES = cm3/cm3.tag=../cm3/html plus all families to be included.
+

3rd/libopencm3/doc/Makefile

@@ -0,0 +1,64 @@
+# Makefile to build libopencm3 documentation
+
+# 14 September 2012
+# (C) Ken Sarkies <ksarkies@internode.on.net>
+
+# setup TARGETS if not set for legacy and ease of debug.
+TARGETS ?= stm32/f0 stm32/f1 stm32/f2 stm32/f3 stm32/f4 stm32/f7 stm32/h7 \
+		   stm32/l0 stm32/l1 stm32/l4 \
+		   stm32/g0 stm32/g4 \
+		   gd32/f1x0 \
+		   efm32/g efm32/gg efm32/hg efm32/lg efm32/tg \
+		   efm32/wg efm32/ezr32wg \
+		   lm3s lm4f \
+		   msp432/e4 \
+		   lpc13xx lpc17xx lpc43xx \
+		   sam/3a sam/3n sam/3s sam/3u sam/3x \
+		   sam/d sam/4l \
+		   vf6xx \
+		   swm050 \
+   		   pac55xx
+
+
+TARGETS_DIRS = $(subst /,,$(TARGETS))
+
+doc: html
+
+
+DoxygenLayout.xml: templates/DoxygenLayout_Root.xml
+	../scripts/gendoxylayout.py --template $< --out $@ $(TARGETS_DIRS)
+
+define gen_DOC_TARGET
+DOC_TARGETS += doc_$(1)
+CLEAN_TARGETS += clean_$(1)
+
+$(1)/:
+	@mkdir -p $$@
+
+$(1)/doxy.sourcelist: $(1)/
+	@../scripts/gendoxylist ../lib/$(TARGET_SRC_DIR) $(1)
+
+$(1)/Doxyfile: templates/Doxyfile_Device | $(1)/
+	@cat $$< | sed s/#device#/$(1)/g > $$@
+
+$(1)/DoxygenLayout_$(1).xml: templates/DoxygenLayout_Device.xml | $(1)/
+	@../scripts/gendoxylayout.py --template $$< --out $$@ --target $(1) $$(TARGETS_DIRS)
+
+doc_$(1): $(1)/doxy.sourcelist $(1)/Doxyfile $(1)/DoxygenLayout_$(1).xml
+	@(cd $(1); doxygen)
+
+clean_$(1):
+	@$(RM) -rf $(1)/doxy.sourcelist $(1)/Doxyfile $(1)/DoxygenLayout_$1.xml $(1)/doxygen_$(1).log $(1)/html $(1)/$(1).tag
+
+endef
+
+$(foreach TARGET_SRC_DIR, $(TARGETS), $(eval $(call gen_DOC_TARGET,$(subst /,,$(TARGET_SRC_DIR)))))
+
+html: $(DOC_TARGETS) DoxygenLayout.xml
+	doxygen
+
+clean: $(CLEAN_TARGETS)
+	@rm -rf html/ DoxygenLayout.xml doxygen.log
+ 
+.PHONY: doc html $(DOC_TARGETS) $(CLEAN_TARGETS)
+

3rd/libopencm3/doc/README

@@ -0,0 +1,34 @@
+libopencm3 Documentation
+14 September 2012 (C) K Sarkies
+-------------------------------
+
+To generate all documentation run 'make doc' in the doc directory, or
+for html documentation only run 'make html' (much faster). This runs doxygen
+for each of the processor families then integrates the whole.
+
+Alternatively run 'make doc' in the top directory to make html documentation.
+LaTeX and pdf documentation is currently very large in size.
+
+This requires doxygen v 1.8.2 or later.
+
+HTML, LaTeX, and pdf output can be produced.
+
+Generation of HTML
+------------------
+
+To view HTML, point a browser to libopencm3/doc/html/index.html.
+
+Generation of PDF
+-----------------
+
+The pdf is generated via LaTeX. The pdf files are placed in the
+doc directory. Each file contains all documentation for the core and common
+features. The resulting files are huge.
+
+
+Requirements
+------------
+On Fedora 19, the following packages (at least!) are needed to build the pdf
+output
+
+    texlive texlive-sectsty texlive-tocloft texlive-xtab texlive-multirow

3rd/libopencm3/doc/efm32ezr32wg/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7EM__

3rd/libopencm3/doc/efm32g/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7M__

3rd/libopencm3/doc/efm32gg/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7M__

3rd/libopencm3/doc/efm32hg/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_6M__

3rd/libopencm3/doc/efm32lg/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7M__

3rd/libopencm3/doc/efm32tg/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7M__

3rd/libopencm3/doc/efm32wg/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7EM__

3rd/libopencm3/doc/gd32f1x0/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7M__

3rd/libopencm3/doc/index.html

@@ -0,0 +1,8 @@
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+	<meta http-equiv="refresh" content="0;URL='html/index.html'" />
+</head>
+<body> 
+	<a href="html/index.html">Documentation index</a></p>
+</body>
+</html>

3rd/libopencm3/doc/lm3s/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7M__

3rd/libopencm3/doc/lm4f/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7EM__

3rd/libopencm3/doc/lpc13xx/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7M__

3rd/libopencm3/doc/lpc17xx/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7M__

3rd/libopencm3/doc/lpc43xx/doxy.custom

@@ -0,0 +1,3 @@
+# Empty file to satisfy doxygen include.
+# this directory is for shared code between m3 and m4 cores of lpc43xx
+# So needs no predefined arch macros

3rd/libopencm3/doc/lpc43xxm0/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_6M__

3rd/libopencm3/doc/lpc43xxm4/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7EM__

3rd/libopencm3/doc/msp432e4/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7EM__

3rd/libopencm3/doc/pac55xx/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7EM__

3rd/libopencm3/doc/sam3a/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7M__

3rd/libopencm3/doc/sam3n/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7M__

3rd/libopencm3/doc/sam3s/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7M__

3rd/libopencm3/doc/sam3u/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7M__

3rd/libopencm3/doc/sam3x/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7M__

3rd/libopencm3/doc/sam4l/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7EM__

3rd/libopencm3/doc/samd/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_6M__

3rd/libopencm3/doc/stm32f0/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_6M__

3rd/libopencm3/doc/stm32f1/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7M__

3rd/libopencm3/doc/stm32f2/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7M__

3rd/libopencm3/doc/stm32f3/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7EM__

3rd/libopencm3/doc/stm32f4/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7EM__

3rd/libopencm3/doc/stm32f7/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7EM__

3rd/libopencm3/doc/stm32g0/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_6M__

3rd/libopencm3/doc/stm32g4/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7EM__

3rd/libopencm3/doc/stm32h7/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7EM__

3rd/libopencm3/doc/stm32l0/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_6M__

3rd/libopencm3/doc/stm32l1/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7M__

3rd/libopencm3/doc/stm32l4/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7EM__

3rd/libopencm3/doc/swm050/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_6M__

3rd/libopencm3/doc/templates/Doxyfile_Device

@@ -0,0 +1,8 @@
+@INCLUDE				= ../Doxyfile_common
+INPUT					= ../../include/libopencm3/license.dox
+@INCLUDE				= doxy.sourcelist
+@INCLUDE	= doxy.custom
+WARN_LOGFILE			= doxygen_#device#.log
+LAYOUT_FILE				= DoxygenLayout_#device#.xml
+GENERATE_TAGFILE		= #device#.tag
+ENABLE_PREPROCESSING	= YES

3rd/libopencm3/doc/templates/DoxygenLayout_Device.xml

@@ -0,0 +1,185 @@
+<doxygenlayout version="1.0">
+  <!-- Navigation index tabs for HTML output -->
+  <navindex>
+    <tab type="mainpage" visible="yes" title="libopencm3"/>
+    <tab type="pages" visible="yes" title="General Information" intro=""/>
+    <tab type="user" visible="yes" url="../../html/index.html" title="Back to Top" intro=""/>
+    <!-- #devices# -->
+    <tab type="namespaces" visible="yes" title="">
+      <tab type="namespaces" visible="yes" title="" intro=""/>
+      <tab type="namespacemembers" visible="yes" title="" intro=""/>
+    </tab>
+    <tab type="classes" visible="yes" title="">
+      <tab type="classes" visible="yes" title="" intro=""/>
+      <tab type="classindex" visible="$ALPHABETICAL_INDEX" title=""/> 
+      <tab type="hierarchy" visible="yes" title="" intro=""/>
+      <tab type="classmembers" visible="yes" title="" intro=""/>
+    </tab>
+    <tab type="files" visible="yes" title="">
+      <tab type="files" visible="yes" title="" intro=""/>
+      <tab type="globals" visible="yes" title="" intro=""/>
+    </tab>
+    <tab type="examples" visible="yes" title="" intro=""/>  
+  </navindex>
+
+  <!-- Layout definition for a class page -->
+  <class>
+    <briefdescription visible="yes"/>
+    <includes visible="$SHOW_INCLUDE_FILES"/>
+    <inheritancegraph visible="$CLASS_GRAPH"/>
+    <collaborationgraph visible="$COLLABORATION_GRAPH"/>
+    <allmemberslink visible="yes"/>
+    <memberdecl>
+      <nestedclasses visible="yes" title=""/>
+      <publictypes title=""/>
+      <publicslots title=""/>
+      <signals title=""/>
+      <publicmethods title=""/>
+      <publicstaticmethods title=""/>
+      <publicattributes title=""/>
+      <publicstaticattributes title=""/>
+      <protectedtypes title=""/>
+      <protectedslots title=""/>
+      <protectedmethods title=""/>
+      <protectedstaticmethods title=""/>
+      <protectedattributes title=""/>
+      <protectedstaticattributes title=""/>
+      <packagetypes title=""/>
+      <packagemethods title=""/>
+      <packagestaticmethods title=""/>
+      <packageattributes title=""/>
+      <packagestaticattributes title=""/>
+      <properties title=""/>
+      <events title=""/>
+      <privatetypes title=""/>
+      <privateslots title=""/>
+      <privatemethods title=""/>
+      <privatestaticmethods title=""/>
+      <privateattributes title=""/>
+      <privatestaticattributes title=""/>
+      <friends title=""/>
+      <related title="" subtitle=""/>
+      <membergroups visible="yes"/>
+    </memberdecl>
+    <detaileddescription title=""/>
+    <memberdef>
+      <typedefs title=""/>
+      <enums title=""/>
+      <constructors title=""/>
+      <functions title=""/>
+      <related title=""/>
+      <variables title=""/>
+      <properties title=""/>
+      <events title=""/>
+    </memberdef>
+    <usedfiles visible="$SHOW_USED_FILES"/>
+    <authorsection visible="yes"/>
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+    <detaileddescription title=""/>
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+</doxygenlayout>

3rd/libopencm3/doc/templates/DoxygenLayout_Root.xml

@@ -0,0 +1,174 @@
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+  <!-- Navigation index tabs for HTML output -->
+  <navindex>
+    <tab type="mainpage" visible="yes" title="libopencm3"/>
+    <tab type="pages" visible="yes" title="General Information" intro=""/>
+    <tab type="user" visible="yes" url="../html/index.html" title="Top Level" intro=""/>
+    <!-- #devices# -->
+    <tab type="namespaces" visible="yes" title="">
+      <tab type="namespaces" visible="yes" title="" intro=""/>
+      <tab type="namespacemembers" visible="yes" title="" intro=""/>
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3rd/libopencm3/doc/vf6xx/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7EM__

3rd/libopencm3/include/libopencm3/cm3/assert.h

@@ -0,0 +1,138 @@
+/** @defgroup debugging Debugging
+@ingroup CM3_defines
+
+@brief Macros and functions to aid in debugging
+
+@version 1.0.0
+
+@date 25 September 2012
+
+Two preprocessor defines control the behavior of assertion check macros in
+this module. They allow the choice between generated code size and ease of
+debugging.
+
+If NDEBUG is defined, all assertion checks are disabled and macros do not
+generate any code.
+
+If CM3_ASSERT_VERBOSE is defined, information regarding the position of
+assertion checks will be stored in the binary, allowing for more
+informative error messages, but also significantly increased code size. As
+default assertion checks do not use this information it is only useful if
+the application linked with libopencm3 defines its own
+cm3_assert_failed_verbose() implementation.
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Tomaz Solc <tomaz.solc@tablix.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+
+#ifndef LIBOPENCM3_CM3_ASSERT_H
+#define LIBOPENCM3_CM3_ASSERT_H
+
+#include <libopencm3/cm3/common.h>
+
+#define CM3_LIKELY(expr) (__builtin_expect(!!(expr), 1))
+
+#ifdef NDEBUG
+# define cm3_assert(expr) (void)0
+# define cm3_assert_not_reached() do { } while (1)
+#else
+# ifdef CM3_ASSERT_VERBOSE
+#  define cm3_assert(expr) do { \
+				if (CM3_LIKELY(expr)) { \
+					(void)0; \
+				} else { \
+					cm3_assert_failed_verbose( \
+						__FILE__, __LINE__, \
+						__func__, #expr); \
+				} \
+			   } while (0)
+#  define cm3_assert_not_reached() \
+	cm3_assert_failed_verbose( \
+			__FILE__, __LINE__, \
+			__func__, 0)
+# else
+/** @brief Check if assertion is true.
+ *
+ * If NDEBUG macro is defined, this macro generates no code. Otherwise
+ * cm3_assert_failed() or cm3_assert_failed_verbose() is called if assertion
+ * is false.
+ *
+ * The purpose of this macro is to aid in debugging libopencm3 and
+ * applications using it. It can be used for example to check if function
+ * arguments are within expected ranges and stop execution in case an
+ * unexpected state is reached.
+ *
+ * @param expr expression to check */
+#  define cm3_assert(expr) do { \
+				if (CM3_LIKELY(expr)) { \
+					(void)0; \
+				} else { \
+					cm3_assert_failed(); \
+				} \
+			} while (0)
+/** @brief Check if unreachable code is reached.
+ *
+ * If NDEBUG macro is defined, this macro generates code for an infinite loop.
+ * Otherwise cm3_assert_failed() or cm3_assert_failed_verbose() is called if
+ * the macro is ever reached.
+ *
+ * The purpose of this macro is to aid in debugging libopencm3 and
+ * applications using it. It can be used for example to stop execution if an
+ * unreachable portion of code is reached. */
+#  define cm3_assert_not_reached() cm3_assert_failed()
+# endif
+#endif
+
+BEGIN_DECLS
+
+/** @brief Called on a failed assertion.
+ *
+ * Halts execution in an infinite loop. This function never returns.
+ *
+ * Defined as a weak symbol, so applications can define their own
+ * implementation. Usually, a custom implementation of this function should
+ * report an error in some way (print a message to a debug console, display,
+ * LED, ...) and halt execution or reboot the device. */
+void cm3_assert_failed(void) __attribute__((__noreturn__));
+
+/** @brief Called on a failed assertion with verbose messages enabled.
+ *
+ * Halts execution in an infinite loop. This function never returns.
+ *
+ * Defined as a weak symbol, so applications can define their own
+ * implementation. Usually, a custom implementation of this function should
+ * report an error in some way (print a message to a debug console, display,
+ * LED, ...) and halt execution or reboot the device.
+ *
+ * @param file File name where the failed assertion occurred
+ * @param line Line number where the failed assertion occurred
+ * @param func Name of the function where the failed assertion occurred
+ * @param assert_expr Expression that evaluated to false (can be NULL) */
+void cm3_assert_failed_verbose(const char *file, int line, const char *func,
+		const char *assert_expr) __attribute__((__noreturn__));
+
+END_DECLS
+
+#endif
+
+/**@}*/

3rd/libopencm3/include/libopencm3/cm3/common.h

@@ -0,0 +1,114 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_CM3_COMMON_H
+#define LIBOPENCM3_CM3_COMMON_H
+
+#ifdef __cplusplus
+/* Declarations need wrapping for C++ */
+# define BEGIN_DECLS extern "C" {
+# define END_DECLS }
+#elif defined(__ASSEMBLER__)
+/* skipping for assembly */
+#define BEGIN_DECLS .if 0
+#define END_DECLS .endif
+#else
+/* And nothing for C */
+# define BEGIN_DECLS
+# define END_DECLS
+#endif
+
+/* Full-featured deprecation attribute with fallback for older compilers. */
+
+#ifdef __GNUC__
+#	if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ > 4)
+#		define LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))
+#	else
+#		define LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated))
+#	endif
+#else
+#	define LIBOPENCM3_DEPRECATED(x)
+#endif
+
+
+#if defined (__ASSEMBLER__)
+#define MMIO8(addr)	(addr)
+#define MMIO16(addr)	(addr)
+#define MMIO32(addr)	(addr)
+#define MMIO64(addr)	(addr)
+
+#define BBIO_SRAM(addr, bit) \
+	(((addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)
+
+#define BBIO_PERIPH(addr, bit) \
+	(((addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)
+#else
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/* Generic memory-mapped I/O accessor functions */
+#define MMIO8(addr)		(*(volatile uint8_t *)(addr))
+#define MMIO16(addr)		(*(volatile uint16_t *)(addr))
+#define MMIO32(addr)		(*(volatile uint32_t *)(addr))
+#define MMIO64(addr)		(*(volatile uint64_t *)(addr))
+
+/* Generic bit-band I/O accessor functions */
+#define BBIO_SRAM(addr, bit) \
+	MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)
+
+#define BBIO_PERIPH(addr, bit) \
+	MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)
+#endif
+
+/* Generic bit definition */
+#define BIT0  (1<<0)
+#define BIT1  (1<<1)
+#define BIT2  (1<<2)
+#define BIT3  (1<<3)
+#define BIT4  (1<<4)
+#define BIT5  (1<<5)
+#define BIT6  (1<<6)
+#define BIT7  (1<<7)
+#define BIT8  (1<<8)
+#define BIT9  (1<<9)
+#define BIT10 (1<<10)
+#define BIT11 (1<<11)
+#define BIT12 (1<<12)
+#define BIT13 (1<<13)
+#define BIT14 (1<<14)
+#define BIT15 (1<<15)
+#define BIT16 (1<<16)
+#define BIT17 (1<<17)
+#define BIT18 (1<<18)
+#define BIT19 (1<<19)
+#define BIT20 (1<<20)
+#define BIT21 (1<<21)
+#define BIT22 (1<<22)
+#define BIT23 (1<<23)
+#define BIT24 (1<<24)
+#define BIT25 (1<<25)
+#define BIT26 (1<<26)
+#define BIT27 (1<<27)
+#define BIT28 (1<<28)
+#define BIT29 (1<<29)
+#define BIT30 (1<<30)
+#define BIT31 (1<<31)
+
+#endif

3rd/libopencm3/include/libopencm3/cm3/cortex.h

@@ -0,0 +1,285 @@
+/** @defgroup CM3_cortex_defines Cortex Core Defines
+ *
+ * @brief <b>libopencm3 Defined Constants and Types for the Cortex Core </b>
+ *
+ * @ingroup CM3_defines
+ *
+ * @version 1.0.0
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2013 Ben Gamari <bgamari@gmail.com>
+ * Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_CORTEX_H
+#define LIBOPENCM3_CORTEX_H
+
+/**@{*/
+
+#include <stdbool.h>
+#include <stdint.h>
+
+/*---------------------------------------------------------------------------*/
+/** @brief Cortex M Enable interrupts
+ *
+ * Disable the interrupt mask and enable interrupts globally
+ */
+static inline void cm_enable_interrupts(void)
+{
+	__asm__ volatile ("CPSIE I\n");
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Cortex M Disable interrupts
+ *
+ * Mask all interrupts globally
+ */
+static inline void cm_disable_interrupts(void)
+{
+	__asm__ volatile ("CPSID I\n");
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Cortex M Enable faults
+ *
+ * Disable the HardFault mask and enable fault interrupt globally
+ */
+static inline void cm_enable_faults(void)
+{
+	__asm__ volatile ("CPSIE F\n");
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Cortex M Disable faults
+ *
+ * Mask the HardFault interrupt globally
+ */
+static inline void cm_disable_faults(void)
+{
+	__asm__ volatile ("CPSID F\n");
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Cortex M Check if interrupts are masked
+ *
+ * Checks, if interrupts are masked (disabled).
+ *
+ * @returns true, if interrupts are disabled.
+ */
+__attribute__((always_inline))
+static inline bool cm_is_masked_interrupts(void)
+{
+	register uint32_t result;
+	__asm__ volatile ("MRS %0, PRIMASK"  : "=r" (result));
+	return result;
+}
+
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+/*---------------------------------------------------------------------------*/
+/** @brief Cortex M Check if Fault interrupt is masked
+ *
+ * Checks, if HardFault interrupt is masked (disabled).
+ *
+ * @returns bool true, if HardFault interrupt is disabled.
+ */
+__attribute__((always_inline))
+static inline bool cm_is_masked_faults(void)
+{
+	register uint32_t result;
+	__asm__ volatile ("MRS %0, FAULTMASK"  : "=r" (result));
+	return result;
+}
+#endif
+
+/*---------------------------------------------------------------------------*/
+/** @brief Cortex M Mask interrupts
+ *
+ * This function switches the mask of the interrupts. If mask is true, the
+ * interrupts will be disabled. The result of this function can be used for
+ * restoring previous state of the mask.
+ *
+ * @param[in] mask uint32_t New state of the interrupt mask
+ * @returns uint32_t old state of the interrupt mask
+ */
+__attribute__((always_inline))
+static inline uint32_t cm_mask_interrupts(uint32_t mask)
+{
+	register uint32_t old;
+	__asm__ __volatile__("MRS %0, PRIMASK"  : "=r" (old));
+	__asm__ __volatile__(""  : : : "memory");
+	__asm__ __volatile__("MSR PRIMASK, %0" : : "r" (mask));
+	return old;
+}
+
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+/*---------------------------------------------------------------------------*/
+/** @brief Cortex M Mask HardFault interrupt
+ *
+ * This function switches the mask of the HardFault interrupt. If mask is true,
+ * the HardFault interrupt will be disabled. The result of this function can be
+ * used for restoring previous state of the mask.
+ *
+ * @param[in] mask uint32_t New state of the HardFault interrupt mask
+ * @returns uint32_t old state of the HardFault interrupt mask
+ */
+__attribute__((always_inline))
+static inline uint32_t cm_mask_faults(uint32_t mask)
+{
+	register uint32_t old;
+	__asm__ __volatile__ ("MRS %0, FAULTMASK"  : "=r" (old));
+	__asm__ __volatile__ (""  : : : "memory");
+	__asm__ __volatile__ ("MSR FAULTMASK, %0" : : "r" (mask));
+	return old;
+}
+#endif
+
+/**@}*/
+
+/*===========================================================================*/
+/** @defgroup CM3_cortex_atomic_defines Cortex Core Atomic support Defines
+ *
+ * @brief Atomic operation support
+ *
+ * @ingroup CM3_cortex_defines
+ */
+/**@{*/
+
+#if !defined(__DOXYGEN__)
+/* Do not populate this definition outside */
+static inline uint32_t __cm_atomic_set(uint32_t *val)
+{
+	return cm_mask_interrupts(*val);
+}
+
+#define __CM_SAVER(state)					\
+	__val = (state),					\
+	__save __attribute__((__cleanup__(__cm_atomic_set))) =	\
+	__cm_atomic_set(&__val)
+
+#endif /* !defined(__DOXYGEN) */
+
+
+/*---------------------------------------------------------------------------*/
+/** @brief Cortex M Atomic Declare block
+ *
+ * This macro disables interrupts for the next command or block of code. The
+ * interrupt mask is automatically restored after exit of the boundary of the
+ * code block. Therefore restore of interrupt is done automatically after call
+ * of return or goto control sentence jumping outside of the block.
+ *
+ * @warning The usage of sentences break or continue is prohibited in the block
+ * due to implementation of this macro!
+ *
+ * @note It is safe to use this block inside normal code and in interrupt
+ * routine.
+ *
+ * Basic usage of atomic block
+ *
+ * @code
+ * uint64_t value;		// This value is used somewhere in interrupt
+ *
+ * ...
+ *
+ * CM_ATOMIC_BLOCK() {			// interrupts are masked in this block
+ *     value = value * 1024 + 651;	// access value as atomic
+ * }					// interrupts is restored automatically
+ * @endcode
+ *
+ * Use of return inside block
+ *
+ * @code
+ * uint64_t value;		// This value is used somewhere in interrupt
+ *
+ * ...
+ *
+ * uint64_t allocval(void)
+ * {
+ *     CM_ATOMIC_BLOCK() {		// interrupts are masked in this block
+ *         value = value * 1024 + 651;	// do long atomic operation
+ *         return value;		// interrupts is restored automatically
+ *     }
+ * }
+ * @endcode
+ */
+#if defined(__DOXYGEN__)
+#define CM_ATOMIC_BLOCK()
+#else /* defined(__DOXYGEN__) */
+#define CM_ATOMIC_BLOCK()						\
+	for (uint32_t __CM_SAVER(true), __my = true; __my; __my = false)
+#endif /* defined(__DOXYGEN__) */
+
+/*---------------------------------------------------------------------------*/
+/** @brief Cortex M Atomic Declare context
+ *
+ * This macro disables interrupts in the current block of code from the place
+ * where it is defined to the end of the block. The interrupt mask is
+ * automatically restored after exit of the boundary of the code block.
+ * Therefore restore of interrupt is done automatically after call of return,
+ * continue, break, or goto control sentence jumping outside of the block.
+ *
+ * @note This function is intended for use in for- cycles to enable the use of
+ * break and contine sentences inside the block, and for securing the atomic
+ * reader-like functions.
+ *
+ * @note It is safe to use this block inside normal code and in interrupt
+ * routine.
+ *
+ * Basic usage of atomic context
+ *
+ * @code
+ * uint64_t value;		// This value is used somewhere in interrupt
+ *
+ * ...
+ *
+ * for (int i=0;i < 100; i++) {
+ *     CM_ATOMIC_CONTEXT();		// interrupts are masked in this block
+ *     value += 100;			// access value as atomic
+ *     if ((value % 16) == 0) {
+ *         break;			// restore interrupts and break cycle
+ *     }
+ * }					// interrupts is restored automatically
+ * @endcode
+ *
+ * Usage of atomic context inside atomic reader fcn.
+ *
+ * @code
+ * uint64_t value;		// This value is used somewhere in interrupt
+ *
+ * ...
+ *
+ * uint64_t getnextval(void)
+ * {
+ *     CM_ATOMIC_CONTEXT();	// interrupts are masked in this block
+ *     value = value + 3;	// do long atomic operation
+ *     return value;		// interrupts is restored automatically
+ * }
+ * @endcode
+ */
+#if defined(__DOXYGEN__)
+#define CM_ATOMIC_CONTEXT()
+#else /* defined(__DOXYGEN__) */
+#define CM_ATOMIC_CONTEXT()	uint32_t __CM_SAVER(true)
+#endif /* defined(__DOXYGEN__) */
+
+/**@}*/
+
+
+
+#endif

3rd/libopencm3/include/libopencm3/cm3/doc-cm3.h

@@ -0,0 +1,26 @@
+/** @mainpage libopencm3 Core CM3
+
+@version 1.0.0
+
+@date 14 September 2012
+
+API documentation for Cortex M3 core features.
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup CM3_defines CM3 Defines
+
+@brief Defined Constants and Types for Cortex M3 core features
+
+@version 1.0.0
+
+@date 14 September 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup CM3_files Cortex Core Peripheral APIs
+ * APIs for Cortex Core peripherals
+ */
+

3rd/libopencm3/include/libopencm3/cm3/dwt.h

@@ -0,0 +1,209 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_CM3_DWT_H
+#define LIBOPENCM3_CM3_DWT_H
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/cm3/memorymap.h>
+
+/**
+ * @defgroup cm_dwt Cortex-M Data Watch and Trace unit.
+ * @ingroup CM3_defines
+ * System Control Space (SCS) =>  Data Watchpoint and Trace (DWT).
+ * See "ARMv7-M Architecture Reference Manual"
+ * and "ARMv6-M Architecture Reference Manual"
+ * The DWT is an optional debug unit that provides watchpoints, data tracing,
+ * and system profiling for the processor.
+ * @{
+ */
+
+/*****************************************************************************/
+/* Register definitions                                                      */
+/*****************************************************************************/
+
+/** DWT Control register
+ * Purpose Provides configuration and status information for the DWT block, and
+ * used to control features of the block
+ * Usage constraints: There are no usage constraints.
+ * Configurations Always implemented.
+ */
+#define DWT_CTRL			MMIO32(DWT_BASE + 0x00)
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+
+/**
+ * DWT_CYCCNT register
+ * Cycle Count Register (Shows or sets the value of the processor cycle
+ * counter, CYCCNT)
+ * When enabled, CYCCNT increments on each processor clock cycle. On overflow,
+ * CYCCNT wraps to zero.
+ *
+ * Purpose Shows or sets the value of the processor cycle counter, CYCCNT.
+ * Usage constraints: The DWT unit suspends CYCCNT counting when the processor
+ * is in Debug state.
+ * Configurations Implemented: only when DWT_CTRL.NOCYCCNT is RAZ, see Control
+ * register, DWT_CTRL.
+ * When DWT_CTRL.NOCYCCNT is RAO no cycle counter is implemented and this
+ * register is UNK/SBZP.
+*/
+#define DWT_CYCCNT			MMIO32(DWT_BASE + 0x04)
+
+/** DWT_CPICNT register
+ * Purpose Counts additional cycles required to execute multi-cycle
+ * instructions and instruction fetch stalls.
+ * Usage constraints: The counter initializes to 0 when software enables its
+ * counter overflow event by
+ * setting the DWT_CTRL.CPIEVTENA bit to 1.
+ * Configurations Implemented: only when DWT_CTRL.NOPRFCNT is RAZ, see Control
+ * register, DWT_CTRL.
+ * If DWT_CTRL.NOPRFCNT is RAO, indicating that the implementation does not
+ * include the profiling counters, this register is UNK/SBZP.
+ */
+#define DWT_CPICNT			MMIO32(DWT_BASE + 0x08)
+#define DWT_EXCCNT			MMIO32(DWT_BASE + 0x0C)
+#define DWT_SLEEPCNT			MMIO32(DWT_BASE + 0x10)
+#define DWT_LSUCNT			MMIO32(DWT_BASE + 0x14)
+#define DWT_FOLDCNT			MMIO32(DWT_BASE + 0x18)
+
+#endif /* defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) */
+
+#define DWT_PCSR			MMIO32(DWT_BASE + 0x1C)
+#define DWT_COMP(n)			MMIO32(DWT_BASE + 0x20 + (n) * 16)
+#define DWT_MASK(n)			MMIO32(DWT_BASE + 0x24 + (n) * 16)
+#define DWT_FUNCTION(n)			MMIO32(DWT_BASE + 0x28 + (n) * 16)
+
+/* CoreSight Lock Status Register for this peripheral */
+#define DWT_LSR			MMIO32(DWT_BASE + CORESIGHT_LSR_OFFSET)
+/* CoreSight Lock Access Register for this peripheral */
+#define DWT_LAR			MMIO32(DWT_BASE + CORESIGHT_LAR_OFFSET)
+
+
+/*****************************************************************************/
+/* Register values                                                           */
+/*****************************************************************************/
+
+/* --- DWT_CTRL values ---------------------------------------------------- */
+
+#define DWT_CTRL_NUMCOMP_SHIFT		28
+#define DWT_CTRL_NUMCOMP		(0x0F << DWT_CTRL_NUMCOMP_SHIFT)
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+
+#define DWT_CTRL_NOTRCPKT		(1 << 27)
+#define DWT_CTRL_NOEXTTRIG		(1 << 26)
+#define DWT_CTRL_NOCYCCNT		(1 << 25)
+#define DWT_CTRL_NOPRFCCNT		(1 << 24)
+
+#define DWT_CTRL_CYCEVTENA		(1 << 22)
+#define DWT_CTRL_FOLDEVTENA		(1 << 21)
+#define DWT_CTRL_LSUEVTENA		(1 << 20)
+#define DWT_CTRL_SLEEPEVTENA		(1 << 19)
+#define DWT_CTRL_EXCEVTENA		(1 << 18)
+#define DWT_CTRL_CPIEVTENA		(1 << 17)
+#define DWT_CTRL_EXCTRCENA		(1 << 16)
+#define DWT_CTRL_PCSAMPLENA		(1 << 12)
+
+#define DWT_CTRL_SYNCTAP_SHIFT		10
+#define DWT_CTRL_SYNCTAP		(3 << DWT_CTRL_SYNCTAP_SHIFT)
+#define DWT_CTRL_SYNCTAP_DISABLED	(0 << DWT_CTRL_SYNCTAP_SHIFT)
+#define DWT_CTRL_SYNCTAP_BIT24		(1 << DWT_CTRL_SYNCTAP_SHIFT)
+#define DWT_CTRL_SYNCTAP_BIT26		(2 << DWT_CTRL_SYNCTAP_SHIFT)
+#define DWT_CTRL_SYNCTAP_BIT28		(3 << DWT_CTRL_SYNCTAP_SHIFT)
+
+#define DWT_CTRL_CYCTAP			(1 << 9)
+
+#define DWT_CTRL_POSTCNT_SHIFT		5
+#define DWT_CTRL_POSTCNT		(0x0F << DWT_CTRL_POSTCNT_SHIFT)
+
+#define DWT_CTRL_POSTPRESET_SHIFT	1
+#define DWT_CTRL_POSTPRESET		(0x0F << DWT_CTRL_POSTPRESET_SHIFT)
+
+/**
+ * CYCCNTENA Enables the Cycle counter.
+ * 0 = Disabled, 1 = Enabled
+ * This bit is UNK/SBZP if the NOCYCCNT bit is RAO.
+ */
+#define DWT_CTRL_CYCCNTENA		(1 << 0)
+
+#endif /* defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) */
+
+/* --- DWT_MASK(x) values -------------------------------------------------- */
+
+#define DWT_MASKx_MASK			0x0F
+
+/* --- DWT_FUNCTION(x) values ---------------------------------------------- */
+
+#define DWT_FUNCTIONx_MATCHED		(1 << 24)
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+
+#define DWT_FUNCTIONx_DATAVADDR1_SHIFT	16
+#define DWT_FUNCTIONx_DATAVADDR1	(15 << DWT_FUNCTIONx_DATAVADDR1_SHIFT)
+
+#define DWT_FUNCTIONx_DATAVADDR0_SHIFT	12
+#define DWT_FUNCTIONx_DATAVADDR0	(15 << DWT_FUNCTIONx_DATAVADDR0_SHIFT)
+
+#define DWT_FUNCTIONx_DATAVSIZE_SHIFT	10
+#define DWT_FUNCTIONx_DATAVSIZE		(3 << DWT_FUNCTIONx_DATAVSIZE_SHIFT)
+#define DWT_FUNCTIONx_DATAVSIZE_BYTE	(0 << DWT_FUNCTIONx_DATAVSIZE_SHIFT)
+#define DWT_FUNCTIONx_DATAVSIZE_HALF	(1 << DWT_FUNCTIONx_DATAVSIZE_SHIFT)
+#define DWT_FUNCTIONx_DATAVSIZE_WORD	(2 << DWT_FUNCTIONx_DATAVSIZE_SHIFT)
+
+#define DWT_FUNCTIONx_LNK1ENA		(1 << 9)
+#define DWT_FUNCTIONx_DATAVMATCH	(1 << 8)
+#define DWT_FUNCTIONx_CYCMATCH		(1 << 7)
+#define DWT_FUNCTIONx_EMITRANGE		(1 << 5)
+
+#endif /* defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) */
+
+#define DWT_FUNCTIONx_FUNCTION				15
+#define DWT_FUNCTIONx_FUNCTION_DISABLED			0
+
+/* Those defined only on ARMv6 */
+#if defined(__ARM_ARCH_6M__)
+
+#define DWT_FUNCTIONx_FUNCTION_PCWATCH			4
+#define DWT_FUNCTIONx_FUNCTION_DWATCH_R			5
+#define DWT_FUNCTIONx_FUNCTION_DWATCH_W			6
+#define DWT_FUNCTIONx_FUNCTION_DWATCH_RW		7
+
+#endif /* defined(__ARM_ARCH_6M__)*/
+
+/*****************************************************************************/
+/* API definitions                                                           */
+/*****************************************************************************/
+
+/*****************************************************************************/
+/* API Functions                                                             */
+/*****************************************************************************/
+
+BEGIN_DECLS
+
+bool dwt_enable_cycle_counter(void);
+uint32_t dwt_read_cycle_counter(void);
+
+END_DECLS
+
+/**@}*/
+
+#endif /* LIBOPENCM3_CM3_DWT_H */

3rd/libopencm3/include/libopencm3/cm3/fpb.h

@@ -0,0 +1,93 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_CM3_FPB_H
+#define LIBOPENCM3_CM3_FPB_H
+
+/**
+ * @defgroup cm_fpb Cortex-M Flash Patch and Breakpoint (FPB) unit
+ * @ingroup CM3_defines
+ * @{
+ */
+
+/* Those defined only on ARMv7 and above */
+#if !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__)
+#error "Flash Patch and Breakpoint not available in CM0"
+#endif
+
+/* Note: We always use "FPB" as abbreviation, docs sometimes use only "FP". */
+
+/* --- FPB registers ------------------------------------------------------- */
+
+/* Flash Patch Control (FPB_CTRL) */
+#define FPB_CTRL			MMIO32(FPB_BASE + 0)
+
+/* Flash Patch Remap (FPB_REMAP) */
+#define FPB_REMAP			MMIO32(FPB_BASE + 4)
+
+/* Flash Patch Comparator (FPB_COMPx) */
+#define FPB_COMP			(&MMIO32(FPB_BASE + 8))
+
+/* CoreSight Lock Status Register for this peripheral */
+#define FPB_LSR				MMIO32(FPB_BASE + CORESIGHT_LSR_OFFSET)
+/* CoreSight Lock Access Register for this peripheral */
+#define FPB_LAR				MMIO32(FPB_BASE + CORESIGHT_LAR_OFFSET)
+
+
+/* TODO: PID, CID */
+
+/* --- FPB_CTRL values ----------------------------------------------------- */
+
+/* Bits [31:15]: Reserved, read as zero, writes ignored */
+
+#define FPB_CTRL_NUM_CODE2_MASK		(0x7 << 12)
+
+#define FPB_CTRL_NUM_LIT_MASK		(0xf << 8)
+
+#define FPB_CTRL_NUM_CODE1_MASK		(0xf << 4)
+
+/* Bits [3:2]: Reserved */
+
+#define FPB_CTRL_KEY			(1 << 1)
+
+#define FPB_CTRL_ENABLE			(1 << 0)
+
+/* --- FPB_REMAP values ---------------------------------------------------- */
+
+/* TODO */
+
+/* --- FPB_COMPx values ---------------------------------------------------- */
+
+#define FPB_COMP_REPLACE_REMAP		(0x0 << 30)
+#define FPB_COMP_REPLACE_BREAK_LOWER	(0x1 << 30)
+#define FPB_COMP_REPLACE_BREAK_UPPER	(0x2 << 30)
+#define FPB_COMP_REPLACE_BREAK_BOTH	(0x3 << 30)
+#define FPB_COMP_REPLACE_MASK		(0x3 << 30)
+
+/* Bit 29: Reserved */
+
+/* TODO */
+
+/* Bit 1: Reserved */
+
+#define FPB_COMP_ENABLE			(1 << 0)
+
+/**@}*/
+
+#endif

3rd/libopencm3/include/libopencm3/cm3/itm.h

@@ -0,0 +1,94 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_CM3_ITM_H
+#define LIBOPENCM3_CM3_ITM_H
+
+/**
+ * @defgroup cm_itm Cortex-M Instrumentation Trace Macrocell (ITM)
+ * @ingroup CM3_defines
+ * @{
+ */
+
+/* Those defined only on ARMv7 and above */
+#if !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__)
+#error "Instrumentation Trace Macrocell not available in CM0"
+#endif
+
+/* --- ITM registers ------------------------------------------------------- */
+
+/* Stimulus Port x (ITM_STIM<sz>(x)) */
+#define ITM_STIM8(n)			(MMIO8(ITM_BASE + ((n)*4)))
+#define ITM_STIM16(n)			(MMIO16(ITM_BASE + ((n)*4)))
+#define ITM_STIM32(n)			(MMIO32(ITM_BASE + ((n)*4)))
+
+/* Trace Enable ports (ITM_TER[x]) */
+#define ITM_TER				(&MMIO32(ITM_BASE + 0xE00))
+
+/* Trace Privilege (ITM_TPR) */
+#define ITM_TPR				MMIO32(ITM_BASE + 0xE40)
+
+/* Trace Control (ITM_TCR) */
+#define ITM_TCR				MMIO32(ITM_BASE + 0xE80)
+
+/* CoreSight Lock Status Register for this peripheral */
+#define ITM_LSR			MMIO32(ITM_BASE + CORESIGHT_LSR_OFFSET)
+/* CoreSight Lock Access Register for this peripheral */
+#define ITM_LAR			MMIO32(ITM_BASE + CORESIGHT_LAR_OFFSET)
+
+/* TODO: PID, CID */
+
+/* --- ITM_STIM values ----------------------------------------------------- */
+
+/* Bits 31:0 - Write to port FIFO for forwarding as software event packet */
+/* Bits 31:1 - RAZ */
+#define ITM_STIM_FIFOREADY		(1 << 0)
+
+/* --- ITM_TER values ------------------------------------------------------ */
+
+/* Bits 31:0 - Stimulus port #N is enabled with STIMENA[N] is set */
+
+/* --- ITM_TPR values ------------------------------------------------------ */
+/*
+ * Bits 31:0 - Bit [N] of PRIVMASK controls stimulus ports 8N to 8N+7
+ *             0: User access allowed to stimulus ports
+ *             1: Privileged access only to stimulus ports
+ */
+
+/* --- ITM_TCR values ------------------------------------------------------ */
+
+/* Bits 31:24 - Reserved */
+#define ITM_TCR_BUSY			(1 << 23)
+#define ITM_TCR_TRACE_BUS_ID_MASK	(0x3f << 16)
+/* Bits 15:10 - Reserved */
+#define ITM_TCR_TSPRESCALE_NONE		(0 << 8)
+#define ITM_TCR_TSPRESCALE_DIV4		(1 << 8)
+#define ITM_TCR_TSPRESCALE_DIV16	(2 << 8)
+#define ITM_TCR_TSPRESCALE_DIV64	(3 << 8)
+#define ITM_TCR_TSPRESCALE_MASK		(3 << 8)
+/* Bits 7:5 - Reserved */
+#define ITM_TCR_SWOENA			(1 << 4)
+#define ITM_TCR_TXENA			(1 << 3)
+#define ITM_TCR_SYNCENA			(1 << 2)
+#define ITM_TCR_TSENA			(1 << 1)
+#define ITM_TCR_ITMENA			(1 << 0)
+
+/**@}*/
+
+#endif

3rd/libopencm3/include/libopencm3/cm3/memorymap.h

@@ -0,0 +1,103 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_CM3_MEMORYMAP_H
+#define LIBOPENCM3_CM3_MEMORYMAP_H
+
+/* --- ARM Cortex-M0, M3 and M4 specific definitions ----------------------- */
+
+/* Private peripheral bus - Internal */
+#define PPBI_BASE                       (0xE0000000U)
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+/* ITM: Instrumentation Trace Macrocell */
+#define ITM_BASE                        (PPBI_BASE + 0x0000)
+
+/* DWT: Data Watchpoint and Trace unit */
+#define DWT_BASE                        (PPBI_BASE + 0x1000)
+
+/* FPB: Flash Patch and Breakpoint unit */
+#define FPB_BASE                        (PPBI_BASE + 0x2000)
+#endif
+
+/* PPBI_BASE + 0x3000 (0xE000 3000 - 0xE000 DFFF): Reserved */
+
+#define SCS_BASE                        (PPBI_BASE + 0xE000)
+
+/* PPBI_BASE + 0xF000 (0xE000 F000 - 0xE003 FFFF): Reserved */
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+#define TPIU_BASE                       (PPBI_BASE + 0x40000)
+#endif
+
+/* --- SCS: System Control Space --- */
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+/* ITR: Interrupt Type Register */
+#define ITR_BASE                        (SCS_BASE + 0x0000)
+#endif
+
+/* SYS_TICK: System Timer */
+#define SYS_TICK_BASE                   (SCS_BASE + 0x0010)
+
+/* NVIC: Nested Vector Interrupt Controller */
+#define NVIC_BASE                       (SCS_BASE + 0x0100)
+
+/* SCB: System Control Block */
+#define SCB_BASE                        (SCS_BASE + 0x0D00)
+
+/* MPU: Memory protection unit */
+#define MPU_BASE                        (SCS_BASE + 0x0D90)
+
+/* Those defined only on CM0*/
+#if defined(__ARM_ARCH_6M__)
+/* DEBUG: Debug control and configuration */
+#define DEBUG_BASE                      (SCS_BASE + 0x0DF0)
+#endif
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+/* STE: Software Trigger Interrupt Register */
+#define STIR_BASE                       (SCS_BASE + 0x0F00)
+/* ID: ID space */
+#define ID_BASE                         (SCS_BASE + 0x0FD0)
+#endif
+
+/**
+ * @defgroup coresight_registers Coresight Registers
+ * @{
+ * CoreSight Lock Status Registers and Lock Access Registers are
+ * documented for the DWT, ITM, FPB and TPIU peripherals
+ */
+#define CORESIGHT_LSR_OFFSET	0xfb4
+#define CORESIGHT_LAR_OFFSET	0xfb0
+
+/** CoreSight Lock Status Register lock status bit */
+#define CORESIGHT_LSR_SLK		(1<<1)
+/** CoreSight Lock Status Register lock availability bit */
+#define CORESIGHT_LSR_SLI		(1<<0)
+/** CoreSight Lock Access key, common for all */
+#define CORESIGHT_LAR_KEY		0xC5ACCE55
+
+/**@}*/
+
+#endif

3rd/libopencm3/include/libopencm3/cm3/mpu.h

@@ -0,0 +1,143 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/** @defgroup CM3_mpu_defines Cortex-M MPU Defines
+ *
+ * @brief <b>libopencm3 Cortex Memory Protection Unit</b>
+ *
+ * @ingroup CM3_defines
+ *
+ * @version 1.0.0
+ *
+ * LGPL License Terms @ref lgpl_license
+ *
+ * The MPU is available as an option in both ARMv6-M and ARMv7-M, but it has
+ * more features in v7, particularly in the available attributes.
+ *
+ * For more information see the ARM Architecture reference manuals.
+ */
+/**@{*/
+
+#ifndef LIBOPENCM3_MPU_H
+#define LIBOPENCM3_MPU_H
+
+#include <libopencm3/cm3/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- SCB: Registers ------------------------------------------------------ */
+/** @defgroup CM3_mpu_registers MPU Registers
+ * @ingroup CM3_mpu_defines
+ *
+ *@{*/
+/** MPU_TYPE is always available, even if the MPU is not implemented */
+#define MPU_TYPE			MMIO32(MPU_BASE + 0x00)
+#define MPU_CTRL			MMIO32(MPU_BASE + 0x04)
+#define MPU_RNR				MMIO32(MPU_BASE + 0x08)
+#define MPU_RBAR			MMIO32(MPU_BASE + 0x0C)
+#define MPU_RASR			MMIO32(MPU_BASE + 0x10)
+/**@}*/
+
+/* --- MPU values ---------------------------------------------------------- */
+
+/** @defgroup CM3_mpu_type MPU TYPE register fields
+ * @ingroup CM3_mpu_defines
+ * The MPU_TYPE register is always available, even if the MPU is not implemented.
+ * In that case, the DREGION field will read as 0.
+ *@{*/
+/** v6m/v7m only support a unified MPU (IREGION always 0) */
+#define MPU_TYPE_IREGION_LSB		16
+#define MPU_TYPE_IREGION		(0xFF << MPU_TYPE_IREGION_LSB)
+/** DREGION is non zero if the MPU is available */
+#define MPU_TYPE_DREGION_LSB		8
+#define MPU_TYPE_DREGION		(0xFF << MPU_TYPE_DREGION_LSB)
+/** v6m/v7m only support a unifed MPU (Separate always 0) */
+#define MPU_TYPE_SEPARATE		(1<<0)
+/**@}*/
+
+/** @defgroup CM3_mpu_ctrl MPU CTRL register fields
+ * @ingroup CM3_mpu_defines
+ * Defines for the Control Register.
+ *@{*/
+#define MPU_CTRL_PRIVDEFENA		(1<<2)
+#define MPU_CTRL_HFNMIENA		(1<<1)
+#define MPU_CTRL_ENABLE			(1<<0)
+/**@}*/
+
+/** @defgroup CM3_mpu_rnr MPU RNR register fields
+ * @ingroup CM3_mpu_defines
+ * Defines for the Region Number Register.
+ *@{*/
+#define MPU_RNR_REGION_LSB		0
+#define MPU_RNR_REGION			(0xFF << MPU_RNR_REGION_LSB)
+/**@}*/
+
+/** @defgroup CM3_mpu_rbar MPU RBAR register fields
+ * @ingroup CM3_mpu_defines
+ * Defines for the Region Base Address Register.
+ *@{*/
+/** minimum size supported is by writing all ones to ADDR, then reading back */
+#define MPU_RBAR_ADDR			0xFFFFFFE0
+#define MPU_RBAR_VALID			(1<<4)
+#define MPU_RBAR_REGION_LSB		0
+#define MPU_RBAR_REGION			(0xF << MPU_RBAR_REGION_LSB)
+/**@}*/
+
+/** @defgroup CM3_mpu_rasr MPU RASR register fields
+ * @ingroup CM3_mpu_defines
+ * Defines for the Region Attribute and Size Register.
+ *@{*/
+#define MPU_RASR_ATTRS_LSB		16
+#define MPU_RASR_ATTRS			(0xFFFF << MPU_RASR_ATTRS_LSB)
+#define MPU_RASR_SRD_LSB		8
+#define MPU_RASR_SRD			(0xFF << MPU_RASR_SRD_LSB)
+#define MPU_RASR_SIZE_LSB		1
+#define MPU_RASR_SIZE			(0x1F << MPU_RASR_SIZE_LSB)
+#define MPU_RASR_ENABLE			(1 << 0)
+
+/** @defgroup mpu_rasr_attributes MPU RASR Attributes
+ * @ingroup CM3_mpu_rasr
+ * Not all attributes are available on v6m.
+ *
+ *@{*/
+#define MPU_RASR_ATTR_XN		(1 << 28)
+#define MPU_RASR_ATTR_AP		(7 << 24)
+#define MPU_RASR_ATTR_AP_PNO_UNO	(0 << 24)
+#define MPU_RASR_ATTR_AP_PRW_UNO	(1 << 24)
+#define MPU_RASR_ATTR_AP_PRW_URO	(2 << 24)
+#define MPU_RASR_ATTR_AP_PRW_URW	(3 << 24)
+#define MPU_RASR_ATTR_AP_PRO_UNO	(5 << 24)
+#define MPU_RASR_ATTR_AP_PRO_URO	(6 << 24)
+#define MPU_RASR_ATTR_TEX		(7 << 19)
+#define MPU_RASR_ATTR_S			(1 << 18)
+#define MPU_RASR_ATTR_C			(1 << 17)
+#define MPU_RASR_ATTR_B			(1 << 16)
+#define MPU_RASR_ATTR_SCB		(7 << 16)
+/**@}*/
+/**@}*/
+
+/* --- MPU functions ------------------------------------------------------- */
+
+BEGIN_DECLS
+
+
+END_DECLS
+
+/**@}*/
+
+#endif

3rd/libopencm3/include/libopencm3/cm3/nvic.h

@@ -0,0 +1,186 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
+ * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
+ * Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/** @defgroup CM3_nvic_defines Cortex-M NVIC Defines
+ *
+ * @brief <b>libopencm3 Cortex Nested Vectored Interrupt Controller</b>
+ *
+ * @ingroup CM3_defines
+ *
+ * @version 1.0.0
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2010 Piotr Esden-Tempski <piotr@esden.net>
+ *
+ * @date 18 August 2012
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+/**@{*/
+
+#ifndef LIBOPENCM3_NVIC_H
+#define LIBOPENCM3_NVIC_H
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/cm3/memorymap.h>
+
+/** @defgroup nvic_registers NVIC Registers
+ * @{
+ */
+
+/** ISER: Interrupt Set Enable Registers
+ * @note 8 32bit Registers
+ * @note Single register on CM0
+ */
+#define NVIC_ISER(iser_id)		MMIO32(NVIC_BASE + 0x00 + \
+						((iser_id) * 4))
+
+/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */
+
+/** ICER: Interrupt Clear Enable Registers
+ * @note 8 32bit Registers
+ * @note Single register on CM0
+ */
+#define NVIC_ICER(icer_id)		MMIO32(NVIC_BASE + 0x80 + \
+						((icer_id) * 4))
+
+/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */
+
+/** ISPR: Interrupt Set Pending Registers
+ * @note 8 32bit Registers
+ * @note Single register on CM0
+ */
+#define NVIC_ISPR(ispr_id)		MMIO32(NVIC_BASE + 0x100 + \
+						((ispr_id) * 4))
+
+/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */
+
+/** ICPR: Interrupt Clear Pending Registers
+ * @note 8 32bit Registers
+ * @note Single register on CM0
+ */
+#define NVIC_ICPR(icpr_id)		MMIO32(NVIC_BASE + 0x180 + \
+						((icpr_id) * 4))
+
+/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+/** IABR: Interrupt Active Bit Register
+ * @note 8 32bit Registers */
+#define NVIC_IABR(iabr_id)		MMIO32(NVIC_BASE + 0x200 + \
+						((iabr_id) * 4))
+#endif
+
+/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */
+
+/** IPR: Interrupt Priority Registers
+ * @note 240 8bit Registers
+ * @note 32 8bit Registers on CM0, requires word access
+ */
+#if defined(__ARM_ARCH_6M__)
+#define NVIC_IPR32(ipr_id)		MMIO32(NVIC_BASE + 0x300 + \
+						((ipr_id) * 4))
+#else
+#define NVIC_IPR(ipr_id)		MMIO8(NVIC_BASE + 0x300 + \
+						(ipr_id))
+#endif
+
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+/** STIR: Software Trigger Interrupt Register */
+#define NVIC_STIR			MMIO32(STIR_BASE)
+#endif
+
+/**@}*/
+
+/* --- IRQ channel numbers-------------------------------------------------- */
+
+/* Cortex M0, M3 and M4 System Interrupts */
+/** @defgroup nvic_sysint Cortex M0/M3/M4 System Interrupts
+@ingroup CM3_nvic_defines
+
+IRQ numbers -3 and -6 to -9 are reserved
+@{*/
+#define NVIC_NMI_IRQ			-14
+#define NVIC_HARD_FAULT_IRQ		-13
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+#define NVIC_MEM_MANAGE_IRQ		-12
+#define NVIC_BUS_FAULT_IRQ		-11
+#define NVIC_USAGE_FAULT_IRQ		-10
+#endif
+
+/* irq numbers -6 to -9 are reserved */
+#define NVIC_SV_CALL_IRQ		-5
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+#define DEBUG_MONITOR_IRQ		-4
+#endif
+
+/* irq number -3 reserved */
+#define NVIC_PENDSV_IRQ			-2
+#define NVIC_SYSTICK_IRQ		-1
+/**@}*/
+
+/* @note User interrupts are family specific and are defined in a family
+ * specific header file in the corresponding subfolder.
+ */
+
+#include <libopencm3/dispatch/nvic.h>
+
+/* --- NVIC functions ------------------------------------------------------ */
+
+BEGIN_DECLS
+
+void nvic_enable_irq(uint8_t irqn);
+void nvic_disable_irq(uint8_t irqn);
+uint8_t nvic_get_pending_irq(uint8_t irqn);
+void nvic_set_pending_irq(uint8_t irqn);
+void nvic_clear_pending_irq(uint8_t irqn);
+uint8_t nvic_get_irq_enabled(uint8_t irqn);
+void nvic_set_priority(uint8_t irqn, uint8_t priority);
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+uint8_t nvic_get_active_irq(uint8_t irqn);
+void nvic_generate_software_interrupt(uint16_t irqn);
+#endif
+
+void reset_handler(void);
+void nmi_handler(void);
+void hard_fault_handler(void);
+void sv_call_handler(void);
+void pend_sv_handler(void);
+void sys_tick_handler(void);
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+void mem_manage_handler(void);
+void bus_fault_handler(void);
+void usage_fault_handler(void);
+void debug_monitor_handler(void);
+#endif
+
+END_DECLS
+
+/**@}*/
+
+#endif

3rd/libopencm3/include/libopencm3/cm3/scb.h

@@ -0,0 +1,492 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_SCB_H
+#define LIBOPENCM3_SCB_H
+
+/**
+ * @defgroup cm_scb Cortex-M System Control Block
+ * @ingroup CM3_defines
+ *
+ * The System Control Block is a section of the System Control Space.
+ * Other members of the SCS are, for instance, DWT, ITM, SYSTICKK.
+ * The exact details of the SCB are defined in the "Architecture Reference
+ * Manual" for either ARMv7-M or ARMV6-m.
+ * @{
+ */
+#include <libopencm3/cm3/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/** @defgroup cm_scb_registers SCB Registers
+ * @ingroup cm_scb
+ * @{
+ */
+
+/** CPUID: CPUID base register */
+#define SCB_CPUID				MMIO32(SCB_BASE + 0x00)
+
+/** ICSR: Interrupt Control State Register */
+#define SCB_ICSR				MMIO32(SCB_BASE + 0x04)
+
+/** VTOR: Vector Table Offset Register */
+#define SCB_VTOR				MMIO32(SCB_BASE + 0x08)
+
+/** AIRCR: Application Interrupt and Reset Control Register */
+#define SCB_AIRCR				MMIO32(SCB_BASE + 0x0C)
+
+/** SCR: System Control Register */
+#define SCB_SCR					MMIO32(SCB_BASE + 0x10)
+
+/** CCR: Configuration Control Register */
+#define SCB_CCR					MMIO32(SCB_BASE + 0x14)
+
+/** System Handler Priority 8 bits Registers, SHPR1/2/3.
+ * @note: 12 8bit Registers
+ * @note: 2 32bit Registers on CM0, requires word access,
+ * (shpr1 doesn't actually exist)
+ */
+#if defined(__ARM_ARCH_6M__)
+#define SCB_SHPR32(ipr_id)		MMIO32(SCS_BASE + 0xD18 + ((ipr_id) * 4))
+#else
+#define SCB_SHPR(ipr_id)		MMIO8(SCS_BASE + 0xD18 + (ipr_id))
+#endif
+
+/** SHCSR: System Handler Control and State Register */
+#define SCB_SHCSR				MMIO32(SCB_BASE + 0x24)
+
+/** DFSR: Debug Fault Status Register */
+#define SCB_DFSR				MMIO32(SCB_BASE + 0x30)
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+/** CFSR: Configurable Fault Status Registers */
+#define SCB_CFSR				MMIO32(SCB_BASE + 0x28)
+
+/** HFSR: Hard Fault Status Register */
+#define SCB_HFSR				MMIO32(SCB_BASE + 0x2C)
+
+/** MMFAR: Memory Manage Fault Address Register */
+#define SCB_MMFAR				MMIO32(SCB_BASE + 0x34)
+
+/** BFAR: Bus Fault Address Register */
+#define SCB_BFAR				MMIO32(SCB_BASE + 0x38)
+
+/** AFSR: Auxiliary Fault Status Register */
+#define SCB_AFSR				MMIO32(SCB_BASE + 0x3C)
+
+/** ID_PFR0: Processor Feature Register 0 */
+#define SCB_ID_PFR0				MMIO32(SCB_BASE + 0x40)
+
+/** ID_PFR1: Processor Feature Register 1 */
+#define SCB_ID_PFR1				MMIO32(SCB_BASE + 0x44)
+
+/** ID_DFR0: Debug Features Register 0 */
+#define SCB_ID_DFR0				MMIO32(SCB_BASE + 0x48)
+
+/** ID_AFR0: Auxiliary Features Register 0 */
+#define SCB_ID_AFR0				MMIO32(SCB_BASE + 0x4C)
+
+/** ID_MMFR0: Memory Model Feature Register 0 */
+#define SCB_ID_MMFR0				MMIO32(SCB_BASE + 0x50)
+
+/** ID_MMFR1: Memory Model Feature Register 1 */
+#define SCB_ID_MMFR1				MMIO32(SCB_BASE + 0x54)
+
+/** ID_MMFR2: Memory Model Feature Register 2 */
+#define SCB_ID_MMFR2				MMIO32(SCB_BASE + 0x58)
+
+/** ID_MMFR3: Memory Model Feature Register 3 */
+#define SCB_ID_MMFR3				MMIO32(SCB_BASE + 0x5C)
+
+/** ID_ISAR0: Instruction Set Attributes Register 0 */
+#define SCB_ID_ISAR0				MMIO32(SCB_BASE + 0x60)
+
+/** ID_ISAR1: Instruction Set Attributes Register 1 */
+#define SCB_ID_ISAR1				MMIO32(SCB_BASE + 0x64)
+
+/** ID_ISAR2: Instruction Set Attributes Register 2 */
+#define SCB_ID_ISAR2				MMIO32(SCB_BASE + 0x68)
+
+/** ID_ISAR3: Instruction Set Attributes Register 3 */
+#define SCB_ID_ISAR3				MMIO32(SCB_BASE + 0x6C)
+
+/** ID_ISAR4: Instruction Set Attributes Register 4 */
+#define SCB_ID_ISAR4				MMIO32(SCB_BASE + 0x70)
+
+/** CPACR: Coprocessor Access Control Register */
+#define SCB_CPACR				MMIO32(SCB_BASE + 0x88)
+
+/** FPCCR: Floating-Point Context Control Register */
+#define SCB_FPCCR				MMIO32(SCB_BASE + 0x234)
+
+/** FPCAR: Floating-Point Context Address Register */
+#define SCB_FPCAR				MMIO32(SCB_BASE + 0x238)
+
+/** FPDSCR: Floating-Point Default Status Control Register */
+#define SCB_FPDSCR				MMIO32(SCB_BASE + 0x23C)
+
+/** MVFR0: Media and Floating-Point Feature Register 0 */
+#define SCB_MVFR0				MMIO32(SCB_BASE + 0x240)
+
+/** MVFR1: Media and Floating-Point Feature Register 1 */
+#define SCB_MVFR1				MMIO32(SCB_BASE + 0x244)
+#endif
+
+/**@}*/
+
+/* --- SCB values ---------------------------------------------------------- */
+
+/**
+ * @defgroup cm3_scb_cpuid_values SCB_CPUID Values
+ * @{
+ */
+/** Implementer[31:24]: Implementer code */
+#define SCB_CPUID_IMPLEMENTER_LSB	24
+#define SCB_CPUID_IMPLEMENTER		(0xFF << SCB_CPUID_IMPLEMENTER_LSB)
+/** Variant[23:20]: Variant number */
+#define SCB_CPUID_VARIANT_LSB		20
+#define SCB_CPUID_VARIANT		(0xF << SCB_CPUID_VARIANT_LSB)
+/** Constant[19:16]
+ * Reads as 0xF (ARMv7-M) M3, M4
+ * Reads as 0xC (ARMv6-M) M0, M0+
+ */
+#define SCB_CPUID_CONSTANT_LSB		16
+#define SCB_CPUID_CONSTANT		(0xF << SCB_CPUID_CONSTANT_LSB)
+#define SCB_CPUID_CONSTANT_ARMV6	(0xC << SCB_CPUID_CONSTANT_LSB)
+#define SCB_CPUID_CONSTANT_ARMV7	(0xF << SCB_CPUID_CONSTANT_LSB)
+
+/** PartNo[15:4]: Part number of the processor */
+#define SCB_CPUID_PARTNO_LSB		4
+#define SCB_CPUID_PARTNO		(0xFFF << SCB_CPUID_PARTNO_LSB)
+/** Revision[3:0]: Revision number */
+#define SCB_CPUID_REVISION_LSB			0
+#define SCB_CPUID_REVISION		(0xF << SCB_CPUID_REVISION_LSB)
+/**@}*/
+
+/**
+ * @defgroup cm3_scb_icsr_values SCB_ICSR Values
+ * @{
+ */
+/** NMIPENDSET: NMI set-pending bit */
+#define SCB_ICSR_NMIPENDSET		(1 << 31)
+/* Bits [30:29]: reserved - must be kept cleared */
+/** PENDSVSET: PendSV set-pending bit */
+#define SCB_ICSR_PENDSVSET		(1 << 28)
+/** PENDSVCLR: PendSV clear-pending bit */
+#define SCB_ICSR_PENDSVCLR		(1 << 27)
+/** PENDSTSET: SysTick exception set-pending bit */
+#define SCB_ICSR_PENDSTSET		(1 << 26)
+/** PENDSTCLR: SysTick exception clear-pending bit */
+#define SCB_ICSR_PENDSTCLR		(1 << 25)
+/* Bit 24: reserved - must be kept cleared */
+/** Bit 23: reserved for debug - reads as 0 when not in debug mode */
+#define SCB_ICSR_ISRPREEMPT		(1 << 23)
+/** ISRPENDING: Interrupt pending flag, excluding NMI and Faults */
+#define SCB_ICSR_ISRPENDING		(1 << 22)
+/** VECTPENDING[21:12] Pending vector */
+#define SCB_ICSR_VECTPENDING_LSB	12
+#define SCB_ICSR_VECTPENDING		(0x1FF << SCB_ICSR_VECTPENDING_LSB)
+/** RETOBASE: Return to base level */
+#define SCB_ICSR_RETOBASE		(1 << 11)
+/* Bits [10:9]: reserved - must be kept cleared */
+/** VECTACTIVE[8:0] Active vector */
+#define SCB_ICSR_VECTACTIVE_LSB		0
+#define SCB_ICSR_VECTACTIVE		(0x1FF << SCB_ICSR_VECTACTIVE_LSB)
+/**@}*/
+
+/**
+ * @defgroup cm3_scb_vtor_values SCB_VTOR Values
+ * @{
+ */
+
+/* IMPLEMENTATION DEFINED */
+
+#if defined(__ARM_ARCH_6M__)
+
+#define SCB_VTOR_TBLOFF_LSB		7
+#define SCB_VTOR_TBLOFF			(0x1FFFFFF << SCB_VTOR_TBLOFF_LSB)
+
+#elif defined(CM1)
+/* VTOR not defined there */
+
+#elif defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+
+/* Bits [31:30]: reserved - must be kept cleared */
+/* TBLOFF[29:9]: Vector table base offset field */
+/* inconsistent datasheet - LSB could be 11 */
+/* BUG: TBLOFF is in the ARMv6 Architecture reference manual defined from b7 */
+#define SCB_VTOR_TBLOFF_LSB		9
+#define SCB_VTOR_TBLOFF			(0x7FFFFF << SCB_VTOR_TBLOFF_LSB)
+
+#endif
+/**@}*/
+
+
+/**
+ * @defgroup cm3_scb_aicr_values SCB_AICR Values
+ * @{
+ */
+/** VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */
+#define SCB_AIRCR_VECTKEYSTAT_LSB	16
+#define SCB_AIRCR_VECTKEYSTAT		(0xFFFF << SCB_AIRCR_VECTKEYSTAT_LSB)
+#define SCB_AIRCR_VECTKEY		(0x05FA << SCB_AIRCR_VECTKEYSTAT_LSB)
+
+/** ENDIANNESS Data endianness bit */
+#define SCB_AIRCR_ENDIANESS			(1 << 15)
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+/* Bits [14:11]: reserved - must be kept cleared */
+/** PRIGROUP[10:8]: Interrupt priority grouping field */
+#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB	(0x3 << 8)
+#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2		(0x4 << 8)
+#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4		(0x5 << 8)
+#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8		(0x6 << 8)
+#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16	(0x7 << 8)
+#define SCB_AIRCR_PRIGROUP_MASK			(0x7 << 8)
+#define SCB_AIRCR_PRIGROUP_SHIFT		8
+/* Bits [7:3]: reserved - must be kept cleared */
+#endif
+
+/** SYSRESETREQ System reset request */
+#define SCB_AIRCR_SYSRESETREQ			(1 << 2)
+/** VECTCLRACTIVE clears state information for exceptions */
+#define SCB_AIRCR_VECTCLRACTIVE			(1 << 1)
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+/** VECTRESET cause local system reset */
+#define SCB_AIRCR_VECTRESET			(1 << 0)
+#endif
+/**@}*/
+
+/**
+ * @defgroup cm3_scb_scr_values SCB_SCR Values
+ * @{
+ */
+/* Bits [31:5]: reserved - must be kept cleared */
+/** SEVONPEND Send Event on Pending bit */
+#define SCB_SCR_SEVONPEND			(1 << 4)
+/* Bit 3: reserved - must be kept cleared */
+/** SLEEPDEEP implementation defined */
+#define SCB_SCR_SLEEPDEEP			(1 << 2)
+/** SLEEPONEXIT sleep when exiting ISR */
+#define SCB_SCR_SLEEPONEXIT			(1 << 1)
+/* Bit 0: reserved - must be kept cleared */
+/**@}*/
+
+/**
+ * @defgroup cm3_scb_ccr_values SCB_CCR Values
+ * @{
+ */
+/* Bits [31:10]: reserved - must be kept cleared */
+/** STKALIGN set to zero to break things :) */
+#define SCB_CCR_STKALIGN			(1 << 9)
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+/** BFHFNMIGN set to attempt ignoring faults in handlers */
+#define SCB_CCR_BFHFNMIGN			(1 << 8)
+/* Bits [7:5]: reserved - must be kept cleared */
+/** DIV_0_TRP set to trap on divide by zero*/
+#define SCB_CCR_DIV_0_TRP			(1 << 4)
+#endif
+
+/** UNALIGN_TRP set to trap on unaligned */
+#define SCB_CCR_UNALIGN_TRP			(1 << 3)
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+/* Bit 2: reserved - must be kept cleared */
+/** USERSETMPEND set to allow unprivileged access to STIR */
+#define SCB_CCR_USERSETMPEND			(1 << 1)
+/** NONBASETHRDENA set to allow non base priority threads */
+#define SCB_CCR_NONBASETHRDENA			(1 << 0)
+#endif
+/**@}*/
+
+/* These numbers are designed to be used with the SCB_SHPR() macro */
+/* SCB_SHPR1 */
+#define SCB_SHPR_PRI_4_MEMMANAGE	0
+#define SCB_SHPR_PRI_5_BUSFAULT		1
+#define SCB_SHPR_PRI_6_USAGEFAULT	2
+#define SCB_SHPR_PRI_7_RESERVED		3
+/* SCB_SHPR2  */
+#define SCB_SHPR_PRI_8_RESERVED		4
+#define SCB_SHPR_PRI_9_RESERVED		5
+#define SCB_SHPR_PRI_10_RESERVED	6
+#define SCB_SHPR_PRI_11_SVCALL		7
+/* SCB_SHPR3 */
+#define SCB_SHPR_PRI_12_RESERVED	8
+#define SCB_SHPR_PRI_13_RESERVED	9
+#define SCB_SHPR_PRI_14_PENDSV		10
+#define SCB_SHPR_PRI_15_SYSTICK		11
+
+/* --- SCB_SHCSR values ---------------------------------------------------- */
+
+/* Bits [31:19]: reserved - must be kept cleared */
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+/* USGFAULTENA: Usage fault enable */
+#define SCB_SHCSR_USGFAULTENA			(1 << 18)
+/* BUSFAULTENA: Bus fault enable */
+#define SCB_SHCSR_BUSFAULTENA			(1 << 17)
+/* MEMFAULTENA: Memory management fault enable */
+#define SCB_SHCSR_MEMFAULTENA			(1 << 16)
+#endif
+
+/* SVCALLPENDED: SVC call pending */
+#define SCB_SHCSR_SVCALLPENDED			(1 << 15)
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+/* BUSFAULTPENDED: Bus fault exception pending */
+#define SCB_SHCSR_BUSFAULTPENDED		(1 << 14)
+/* MEMFAULTPENDED: Memory management fault exception pending */
+#define SCB_SHCSR_MEMFAULTPENDED		(1 << 13)
+/* USGFAULTPENDED: Usage fault exception pending */
+#define SCB_SHCSR_USGFAULTPENDED		(1 << 12)
+/* SYSTICKACT: SysTick exception active */
+#define SCB_SHCSR_SYSTICKACT			(1 << 11)
+/* PENDSVACT: PendSV exception active */
+#define SCB_SHCSR_PENDSVACT			(1 << 10)
+/* Bit 9: reserved - must be kept cleared */
+/* MONITORACT: Debug monitor active */
+#define SCB_SHCSR_MONITORACT			(1 << 8)
+/* SVCALLACT: SVC call active */
+#define SCB_SHCSR_SVCALLACT			(1 << 7)
+/* Bits [6:4]: reserved - must be kept cleared */
+/* USGFAULTACT: Usage fault exception active */
+#define SCB_SHCSR_USGFAULTACT			(1 << 3)
+/* Bit 2: reserved - must be kept cleared */
+/* BUSFAULTACT: Bus fault exception active */
+#define SCB_SHCSR_BUSFAULTACT			(1 << 1)
+/* MEMFAULTACT: Memory management fault exception active */
+#define SCB_SHCSR_MEMFAULTACT			(1 << 0)
+
+/* --- SCB_CFSR values ----------------------------------------------------- */
+
+/* Bits [31:26]: reserved - must be kept cleared */
+/* DIVBYZERO: Divide by zero usage fault */
+#define SCB_CFSR_DIVBYZERO			(1 << 25)
+/* UNALIGNED: Unaligned access usage fault */
+#define SCB_CFSR_UNALIGNED			(1 << 24)
+/* Bits [23:20]: reserved - must be kept cleared */
+/* NOCP: No coprocessor usage fault */
+#define SCB_CFSR_NOCP				(1 << 19)
+/* INVPC: Invalid PC load usage fault */
+#define SCB_CFSR_INVPC				(1 << 18)
+/* INVSTATE: Invalid state usage fault */
+#define SCB_CFSR_INVSTATE			(1 << 17)
+/* UNDEFINSTR: Undefined instruction usage fault */
+#define SCB_CFSR_UNDEFINSTR			(1 << 16)
+/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */
+#define SCB_CFSR_BFARVALID			(1 << 15)
+/* Bits [14:13]: reserved - must be kept cleared */
+/* STKERR: Bus fault on stacking for exception entry */
+#define SCB_CFSR_STKERR				(1 << 12)
+/* UNSTKERR: Bus fault on unstacking for a return from exception */
+#define SCB_CFSR_UNSTKERR			(1 << 11)
+/* IMPRECISERR: Imprecise data bus error */
+#define SCB_CFSR_IMPRECISERR			(1 << 10)
+/* PRECISERR: Precise data bus error */
+#define SCB_CFSR_PRECISERR			(1 << 9)
+/* IBUSERR: Instruction bus error */
+#define SCB_CFSR_IBUSERR			(1 << 8)
+/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */
+#define SCB_CFSR_MMARVALID			(1 << 7)
+/* Bits [6:5]: reserved - must be kept cleared */
+/* MSTKERR: Memory manager fault on stacking for exception entry */
+#define SCB_CFSR_MSTKERR			(1 << 4)
+/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */
+#define SCB_CFSR_MUNSTKERR			(1 << 3)
+/* Bit 2: reserved - must be kept cleared */
+/* DACCVIOL: Data access violation flag */
+#define SCB_CFSR_DACCVIOL			(1 << 1)
+/* IACCVIOL: Instruction access violation flag */
+#define SCB_CFSR_IACCVIOL			(1 << 0)
+
+/* --- SCB_HFSR values ----------------------------------------------------- */
+
+/* DEBUG_VT: reserved for debug use */
+#define SCB_HFSR_DEBUG_VT			(1 << 31)
+/* FORCED: Forced hard fault */
+#define SCB_HFSR_FORCED				(1 << 30)
+/* Bits [29:2]: reserved - must be kept cleared */
+/* VECTTBL: Vector table hard fault */
+#define SCB_HFSR_VECTTBL			(1 << 1)
+/* Bit 0: reserved - must be kept cleared */
+
+/* --- SCB_MMFAR values ---------------------------------------------------- */
+
+/* MMFAR [31:0]: Memory management fault address */
+
+/* --- SCB_BFAR values ----------------------------------------------------- */
+
+/* BFAR [31:0]: Bus fault address */
+
+/* --- SCB_CPACR values ---------------------------------------------------- */
+
+/* CPACR CPn: Access privileges values */
+#define SCB_CPACR_NONE			0	/* Access denied */
+#define SCB_CPACR_PRIV			1	/* Privileged access only */
+#define SCB_CPACR_FULL			3	/* Full access */
+
+/* CPACR [20:21]: Access privileges for coprocessor 10 */
+#define SCB_CPACR_CP10			(1 << 20)
+/* CPACR [22:23]: Access privileges for coprocessor 11 */
+#define SCB_CPACR_CP11			(1 << 22)
+#endif
+
+/* --- SCB functions ------------------------------------------------------- */
+
+BEGIN_DECLS
+
+struct scb_exception_stack_frame {
+	uint32_t r0;
+	uint32_t r1;
+	uint32_t r2;
+	uint32_t r3;
+	uint32_t r12;
+	uint32_t lr;
+	uint32_t pc;
+	uint32_t xpsr;
+} __attribute__((packed));
+
+#define SCB_GET_EXCEPTION_STACK_FRAME(f)				\
+	do {								\
+		asm volatile ("mov %[frameptr], sp"			\
+			      : [frameptr]"=r" (f));			\
+	} while (0)
+
+void scb_reset_system(void) __attribute__((noreturn));
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+void scb_reset_core(void) __attribute__((noreturn));
+void scb_set_priority_grouping(uint32_t prigroup);
+#endif
+
+END_DECLS
+
+/**@}*/
+
+#endif

3rd/libopencm3/include/libopencm3/cm3/scs.h

@@ -0,0 +1,155 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
+ * Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_CM3_SCS_H
+#define LIBOPENCM3_CM3_SCS_H
+
+/**
+ * @defgroup cm_scs Cortex-M System Control Space
+ * @ingroup CM3_defines
+ * The System Control Space (SCS) is a memory-mapped 4KB address space that
+ * provides 32-bit registers for configuration, status reporting and control.
+ * The SCS registers divide into the following groups:
+ * - system control and identification
+ * - the CPUID processor identification space
+ * - system configuration and status
+ * - fault reporting
+ * - a system timer, SysTick
+ * - a Nested Vectored Interrupt Controller (NVIC)
+ * - a Protected Memory System Architecture (PMSA)
+ * - system debug.
+ *
+ * Most portions of the SCS are covered by their own header files, eg
+ * systick.h, dwt.h, scb.h, itm.h, fpb.h
+ * @{
+ */
+
+/** @defgroup cm_scs_registers SCS Registers
+ * @ingroup cm_scs
+ * @{
+ */
+
+/**
+ * Debug Halting Control and Status Register (DHCSR).
+ *
+ * Purpose Controls halting debug.
+ * Usage constraints: The effect of modifying the C_STEP or C_MASKINTS bit when
+ * the system is running with halting debug enabled is UNPREDICTABLE.
+ * Halting debug is enabled when C_DEBUGEN is set to 1. The system is running
+ * when S_HALT is set to 0.
+ * - When C_DEBUGEN is set to 0, the processor ignores the values of all other
+ *   bits in this register.
+ * - For more information about the use of DHCSR see Debug stepping on page
+ *   C1-824.
+ * Configurations Always implemented.
+ */
+#define SCS_DHCSR		MMIO32(SCS_BASE + 0xDF0)
+/**
+ * Debug Core Register Selector Register (DCRSR).
+ *
+ * Purpose With the DCRDR, the DCRSR provides debug access to the ARM core
+ * registers, special-purpose registers, and Floating-point extension
+ * registers. A write to DCRSR specifies the register to transfer, whether the
+ * transfer is a read or a write, and starts the transfer.
+ * Usage constraints: Only accessible in Debug state.
+ * Configurations Always implemented.
+ *
+ */
+#define SCS_DCRSR		MMIO32(SCS_BASE + 0xDF4)
+/**
+ * Debug Core Register Data Register (DCRDR)
+ *
+ * Purpose With the DCRSR, see Debug Core Register Selector Register, the DCRDR
+ * provides debug access to the ARM core registers, special-purpose registers,
+ * and Floating-point extension registers. The DCRDR is the data register for
+ * these accesses.
+ * - Used on its own, the DCRDR provides a message passing resource between an
+ *   external debugger and a debug agent running on the processor.
+ * Note:
+ * The architecture does not define any handshaking mechanism for this use of
+ * DCRDR.
+ * Usage constraints: See Use of DCRSR and DCRDR for constraints that apply to
+ * particular transfers using the DCRSR and DCRDR.
+ * Configurations Always implemented.
+ *
+ */
+#define SCS_DCRDR		MMIO32(SCS_BASE + 0xDF8)
+/**
+ * Debug Exception and Monitor Control Register (DEMCR).
+ *
+ * Purpose Manages vector catch behavior and DebugMonitor handling when
+ * debugging.
+ * Usage constraints:
+ * - Bits [23:16] provide DebugMonitor exception control.
+ * - Bits [15:0] provide Debug state, halting debug, control.
+ * Configurations Always implemented.
+ *
+ */
+#define SCS_DEMCR		MMIO32(SCS_BASE + 0xDFC)
+
+/**@}*/
+
+/* Debug Halting Control and Status Register (DHCSR) */
+#define SCS_DHCSR_DBGKEY	0xA05F0000
+#define SCS_DHCSR_C_DEBUGEN	0x00000001
+#define SCS_DHCSR_C_HALT	0x00000002
+#define SCS_DHCSR_C_STEP	0x00000004
+#define SCS_DHCSR_C_MASKINTS	0x00000008
+#define SCS_DHCSR_C_SNAPSTALL	0x00000020
+#define SCS_DHCSR_S_REGRDY	0x00010000
+#define SCS_DHCSR_S_HALT	0x00020000
+#define SCS_DHCSR_S_SLEEP	0x00040000
+#define SCS_DHCSR_S_LOCKUP	0x00080000
+#define SCS_DHCSR_S_RETIRE_ST	0x01000000
+#define SCS_DHCSR_S_RESET_ST	0x02000000
+
+/* Debug Core Register Selector Register (DCRSR) */
+#define SCS_DCRSR_REGSEL_MASK	0x0000001F
+#define SCS_DCRSR_REGSEL_XPSR	0x00000010
+#define SCS_DCRSR_REGSEL_MSP	0x00000011
+#define SCS_DCRSR_REGSEL_PSP	0x00000012
+
+/* Debug Exception and Monitor Control Register (DEMCR) */
+/* Bits 31:25 - Reserved */
+#define SCS_DEMCR_TRCENA	(1 << 24)
+/* Bits 23:20 - Reserved */
+#define SCS_DEMCR_MON_REQ	(1 << 19)
+#define SCS_DEMCR_MON_STEP	(1 << 18)
+#define SCS_DEMCR_VC_MON_PEND	(1 << 17)
+#define SCS_DEMCR_VC_MON_EN	(1 << 16)
+/* Bits 15:11 - Reserved */
+#define SCS_DEMCR_VC_HARDERR	(1 << 10)
+#define SCS_DEMCR_VC_INTERR	(1 << 9)
+#define SCS_DEMCR_VC_BUSERR	(1 << 8)
+#define SCS_DEMCR_VC_STATERR	(1 << 7)
+#define SCS_DEMCR_VC_CHKERR	(1 << 6)
+#define SCS_DEMCR_VC_NOCPERR	(1 << 5)
+#define SCS_DEMCR_VC_MMERR	(1 << 4)
+/* Bits 3:1 - Reserved */
+#define SCS_DEMCR_VC_CORERESET	(1 << 0)
+
+/* CoreSight Lock Status Register for this peripheral */
+#define SCS_DWT_LSR		MMIO32(SCS_DWT_BASE + 0xFB4)
+/* CoreSight Lock Access Register for this peripheral */
+#define SCS_DWT_LAR		MMIO32(SCS_DWT_BASE + 0xFB0)
+
+
+/**@}*/
+#endif

3rd/libopencm3/include/libopencm3/cm3/sync.h

@@ -0,0 +1,59 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Fergus Noble <fergusnoble@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_CM3_SYNC_H
+#define LIBOPENCM3_CM3_SYNC_H
+
+#include "common.h"
+
+BEGIN_DECLS
+
+void __dmb(void);
+
+/* Implements synchronisation primitives as discussed in the ARM document
+ * DHT0008A (ID081709) "ARM Synchronization Primitives" and the ARM v7-M
+ * Architecture Reference Manual.
+*/
+
+/* --- Exclusive load and store instructions ------------------------------- */
+
+/* Those are defined only on CM3 or CM4 */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+
+uint32_t __ldrex(volatile uint32_t *addr);
+uint32_t __strex(uint32_t val, volatile uint32_t *addr);
+
+/* --- Convenience functions ----------------------------------------------- */
+
+/* Here we implement some simple synchronisation primitives. */
+
+typedef uint32_t mutex_t;
+
+#define MUTEX_UNLOCKED 0
+#define MUTEX_LOCKED	 1
+
+void mutex_lock(mutex_t *m);
+uint32_t mutex_trylock(mutex_t *m);
+void mutex_unlock(mutex_t *m);
+
+#endif
+
+END_DECLS
+
+#endif

3rd/libopencm3/include/libopencm3/cm3/systick.h

@@ -0,0 +1,198 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ * Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/** @defgroup CM3_systick_defines Cortex-M SysTick Defines
+ *
+ * @brief <b>libopencm3 Defined Constants and Types for the Cortex SysTick </b>
+ *
+ * @ingroup CM3_defines
+ *
+ * @version 1.0.0
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * @date 19 August 2012
+ *
+ * System Control Space (SCS) => System timer register support in the SCS.
+ * To configure SysTick, load the interval required between SysTick events to
+ * the SysTick Reload Value register. The timer interrupt, or COUNTFLAG bit in
+ * the SysTick Control and Status register, is activated on the transition from
+ * 1 to 0, therefore it activates every n+1 clock ticks.  If you require a
+ * period of 100, write 99 to the SysTick Reload Value register. The SysTick
+ * Reload Value register supports values between 0x1 and 0x00FFFFFF.
+ *
+ * If you want to use SysTick to generate an event at a timed interval, for
+ * example 1ms, you can use the SysTick Calibration Value Register to scale
+ * your value for the Reload register. The SysTick Calibration Value Register
+ * is a read-only register that contains the number of pulses for a period of
+ * 10ms, in the TENMS field, bits[23:0].
+ *
+ * This register also has a SKEW bit. Bit[30] == 1 indicates that the
+ * calibration for 10ms in the TENMS section is not exactly 10ms due to clock
+ * frequency. Bit[31] == 1 indicates that the reference clock is not provided.
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+
+/**@{*/
+
+#ifndef LIBOPENCM3_SYSTICK_H
+#define LIBOPENCM3_SYSTICK_H
+
+#include <libopencm3/cm3/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/** SysTick Control and Status Register (CSR).
+ * Controls the system timer and provides status data.
+ * Usage constraints: There are no usage constraints.
+ * Configurations Always implemented.
+ */
+#define STK_CSR				MMIO32(SYS_TICK_BASE + 0x00)
+
+/** SysTick Reload Value Register (RVR).
+ * Reads or clears the value that will be loaded to the counter.
+ * Usage constraints:
+ * - Any write to the register clears the register to zero.
+ * - The counter does not provide read-modify-write protection.
+ * - Unsupported bits are read as zero
+ * Configurations Always implemented.
+ */
+#define STK_RVR				MMIO32(SYS_TICK_BASE + 0x04)
+
+/** SysTick Current Value Register (CVR).
+ * Holds the current value of the counter.
+ * Usage constraints: There are no usage constraints.
+ * Configurations Always implemented.
+ */
+#define STK_CVR				MMIO32(SYS_TICK_BASE + 0x08)
+
+/** SysTick Calibration Value Register(Read Only) (CALIB)
+ * Reads the calibration value and parameters for SysTick.
+ * Usage constraints: There are no usage constraints.
+ * Configurations Always implemented.
+ */
+#define STK_CALIB			MMIO32(SYS_TICK_BASE + 0x0C)
+
+/** @defgroup STK_CSR_VALUES STK_CSR Values
+ * @{
+ */
+/** COUNTFLAG
+ * Indicates whether the counter has counted to 0 since the last read of this
+ * register:
+ *  0 = Timer has not counted to 0
+ *  1 = Timer has counted to 0.
+ */
+#define STK_CSR_COUNTFLAG		(1 << 16)
+
+#define STK_CSR_CLKSOURCE_LSB		2
+/** CLKSOURCE: Clock source selection
+ * for 0, SysTick uses the IMPLEMENTATION DEFINED external reference clock.
+ * for 1, SysTick uses the processor clock.
+ * If no external clock is provided, this bit reads as 1 and ignores writes.
+ */
+#define STK_CSR_CLKSOURCE		(1 << STK_CSR_CLKSOURCE_LSB)
+
+/** @defgroup systick_clksource Clock source selection
+@ingroup CM3_systick_defines
+
+@{*/
+#if defined(__ARM_ARCH_6M__)
+#define STK_CSR_CLKSOURCE_EXT		(0 << STK_CSR_CLKSOURCE_LSB)
+#define STK_CSR_CLKSOURCE_AHB		(1 << STK_CSR_CLKSOURCE_LSB)
+#else
+#define STK_CSR_CLKSOURCE_AHB_DIV8	(0 << STK_CSR_CLKSOURCE_LSB)
+#define STK_CSR_CLKSOURCE_AHB		(1 << STK_CSR_CLKSOURCE_LSB)
+#endif
+/**@}*/
+
+/** TICKINT: SysTick exception request enable */
+#define STK_CSR_TICKINT			(1 << 1)
+/** ENABLE: Counter enable */
+#define STK_CSR_ENABLE			(1 << 0)
+/**@}*/
+
+/** @defgroup STK_RVR_VALUES STK_RVR Values
+ * @{
+ */
+/** RELOAD[23:0]: RELOAD value */
+#define STK_RVR_RELOAD			0x00FFFFFF
+
+/**@}*/
+
+
+/** @defgroup STK_RVR_VALUES STK_RVR Values
+ * @{
+ */
+/** CURRENT[23:0]: Current counter value */
+#define STK_CVR_CURRENT			0x00FFFFFF
+/**@}*/
+
+
+/** @defgroup STK_CALIB_VALUES STK_CALIB Values
+ * @{
+ */
+/** NOREF: NOREF flag
+ * Bit31 => NOREF Indicates whether the IMPLEMENTATION DEFINED reference clock
+ * is implemented:
+ * 0 = The reference clock is implemented.
+ * 1 = The reference clock is not implemented.
+ * When this bit is 1, the CLKSOURCE bit of the SYST_CSR register is forced to
+ * 1 and cannot be cleared to 0.
+ */
+#define STK_CALIB_NOREF			(1 << 31)
+
+/** SKEW: SKEW flag
+ * Bit30 => SKEW Indicates whether the 10ms calibration value is exact:
+ * 0 = 10ms calibration value is exact.
+ * 1 = 10ms calibration value is inexact, because of the clock frequency
+ */
+#define STK_CALIB_SKEW			(1 << 30)
+
+/* Bits [29:24] Reserved, must be kept cleared. */
+/** TENMS Calibration value for 10ms.
+ * Bit0 to 23 => TENMS Optionally, holds a reload value to be used for 10ms
+ * (100Hz) timing, subject to system clock skew errors. If this field is zero,
+ * the calibration value is not known.
+ */
+#define STK_CALIB_TENMS			0x00FFFFFF
+/**@}*/
+
+/* --- Function Prototypes ------------------------------------------------- */
+
+BEGIN_DECLS
+
+void systick_set_reload(uint32_t value);
+bool systick_set_frequency(uint32_t freq, uint32_t ahb);
+uint32_t systick_get_reload(void);
+uint32_t systick_get_value(void);
+void systick_set_clocksource(uint8_t clocksource);
+void systick_interrupt_enable(void);
+void systick_interrupt_disable(void);
+void systick_counter_enable(void);
+void systick_counter_disable(void);
+uint8_t systick_get_countflag(void);
+void systick_clear(void);
+
+uint32_t systick_get_calib(void);
+
+END_DECLS
+
+#endif
+/**@}*/
+

3rd/libopencm3/include/libopencm3/cm3/tpiu.h

@@ -0,0 +1,103 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_CM3_TPIU_H
+#define LIBOPENCM3_CM3_TPIU_H
+
+/**
+ * @defgroup cm_tpiu Cortex-M Trace Port Interface Unit (TPIU)
+ * @ingroup CM3_defines
+ * @{
+ */
+
+/* Those defined only on ARMv7 and above */
+#if !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__)
+#error "Trace Port Interface Unit not available in CM0"
+#endif
+
+/* --- TPIU registers ------------------------------------------------------ */
+
+/* Supported Synchronous Port Size (TPIU_SSPSR) */
+#define TPIU_SSPSR			MMIO32(TPIU_BASE + 0x000)
+
+/* Current Synchronous Port Size (TPIU_CSPSR) */
+#define TPIU_CSPSR			MMIO32(TPIU_BASE + 0x004)
+
+/* Asynchronous Clock Prescaler (TPIU_ACPR) */
+#define TPIU_ACPR			MMIO32(TPIU_BASE + 0x010)
+
+/* Selected Pin Protocol (TPIU_SPPR) */
+#define TPIU_SPPR			MMIO32(TPIU_BASE + 0x0F0)
+
+/* Formatter and Flush Status Register (TPIU_FFSR) */
+#define TPIU_FFSR			MMIO32(TPIU_BASE + 0x300)
+
+/* Formatter and Flush Control Register (TPIU_FFCR) */
+#define TPIU_FFCR			MMIO32(TPIU_BASE + 0x304)
+
+/* (TPIU_DEVID) */
+#define TPIU_DEVID			MMIO32(TPIU_BASE + 0xFC8)
+
+/* CoreSight Lock Status Register for this peripheral */
+#define TPIU_LSR			MMIO32(TPIU_BASE + CORESIGHT_LSR_OFFSET)
+/* CoreSight Lock Access Register for this peripheral */
+#define TPIU_LAR			MMIO32(TPIU_BASE + CORESIGHT_LAR_OFFSET)
+
+/* TODO: PID, CID */
+
+/* --- TPIU_ACPR values ---------------------------------------------------- */
+
+/* Bits 31:16 - Reserved */
+/* Bits 15:0 - SWO output clock = Asynchronous_Reference_Clock/(value +1) */
+
+/* --- TPIU_SPPR values ---------------------------------------------------- */
+
+/* Bits 31:2 - Reserved */
+#define TPIU_SPPR_SYNC			(0x0)
+#define TPIU_SPPR_ASYNC_MANCHESTER	(0x1)
+#define TPIU_SPPR_ASYNC_NRZ		(0x2)
+
+/* --- TPIU_FFSR values ---------------------------------------------------- */
+
+/* Bits 31:4 - Reserved */
+#define TPIU_FFSR_FTNONSTOP		(1 << 3)
+#define TPIU_FFSR_TCPRESENT		(1 << 2)
+#define TPIU_FFSR_FTSTOPPED		(1 << 1)
+#define TPIU_FFSR_FLINPROG		(1 << 0)
+
+/* --- TPIU_FFCR values ---------------------------------------------------- */
+
+/* Bits 31:9 - Reserved */
+#define TPIU_FFCR_TRIGIN		(1 << 8)
+/* Bits 7:2 - Reserved */
+#define TPIU_FFCR_ENFCONT		(1 << 1)
+/* Bit 0 - Reserved */
+
+/* --- TPIU_DEVID values ---------------------------------------------------- */
+/* Bits 31:16 - Reserved */
+/* Bits 15:12 - Implementation defined */
+#define TPUI_DEVID_NRZ_SUPPORTED	(1 << 11)
+#define TPUI_DEVID_MANCHESTER_SUPPORTED	(1 << 10)
+/* Bit 9 - RAZ, indicated that trace data and clock are supported */
+#define TPUI_DEVID_FIFO_SIZE_MASK	(7 << 6)
+/* Bits 5:0 - Implementation defined */
+
+/**@}*/
+
+#endif

3rd/libopencm3/include/libopencm3/cm3/vector.h

@@ -0,0 +1,68 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 chrysn <chrysn@fsfe.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/** @file
+ *
+ * Definitions for handling vector tables.
+ *
+ * This implements d0002_efm32_cortex-m3_reference_manual.pdf's figure 2.2
+ * (from the EFM32 documentation at
+ * http://www.energymicro.com/downloads/datasheets), and was seen analogously
+ * in other ARM implementations' libopencm3 files.
+ *
+ * The structure of the vector table is implemented independently of the system
+ * vector table starting at memory position 0x0, as it can be relocated to
+ * other memory locations too.
+ *
+ * The exact size of a vector interrupt table depends on the number of
+ * interrupts IRQ_COUNT, which is defined per family.
+ */
+
+#ifndef LIBOPENCM3_VECTOR_H
+#define LIBOPENCM3_VECTOR_H
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/cm3/nvic.h>
+
+/** Type of an interrupt function. Only used to avoid hard-to-read function
+ * pointers in the efm32_vector_table_t struct. */
+typedef void (*vector_table_entry_t)(void);
+
+typedef struct {
+	unsigned int *initial_sp_value; /**< Initial stack pointer value. */
+	vector_table_entry_t reset;
+	vector_table_entry_t nmi;
+	vector_table_entry_t hard_fault;
+	vector_table_entry_t memory_manage_fault; /* not in CM0 */
+	vector_table_entry_t bus_fault;           /* not in CM0 */
+	vector_table_entry_t usage_fault;         /* not in CM0 */
+	vector_table_entry_t reserved_x001c[4];
+	vector_table_entry_t sv_call;
+	vector_table_entry_t debug_monitor;       /* not in CM0 */
+	vector_table_entry_t reserved_x0034;
+	vector_table_entry_t pend_sv;
+	vector_table_entry_t systick;
+	vector_table_entry_t irq[NVIC_IRQ_COUNT];
+} vector_table_t;
+
+/* Common symbols exported by the linker script(s): */
+extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack;
+extern vector_table_t vector_table;
+
+#endif

3rd/libopencm3/include/libopencm3/dispatch/nvic.h

@@ -0,0 +1,93 @@
+#ifndef LIBOPENCM3_NVIC_H
+#error You should not be including this file directly, but <libopencm3/cm3/nvic.h>
+#endif
+
+#if defined(STM32F0)
+#	include <libopencm3/stm32/f0/nvic.h>
+#elif defined(STM32F1)
+#	include <libopencm3/stm32/f1/nvic.h>
+#elif defined(STM32F2)
+#	include <libopencm3/stm32/f2/nvic.h>
+#elif defined(STM32F3)
+#	include <libopencm3/stm32/f3/nvic.h>
+#elif defined(STM32F4)
+#	include <libopencm3/stm32/f4/nvic.h>
+#elif defined(STM32F7)
+#	include <libopencm3/stm32/f7/nvic.h>
+#elif defined(STM32L0)
+#	include <libopencm3/stm32/l0/nvic.h>
+#elif defined(STM32L1)
+#	include <libopencm3/stm32/l1/nvic.h>
+#elif defined(STM32L4)
+#	include <libopencm3/stm32/l4/nvic.h>
+#elif defined(STM32G0)
+#	include <libopencm3/stm32/g0/nvic.h>
+#elif defined(STM32G4)
+#	include <libopencm3/stm32/g4/nvic.h>
+#elif defined(STM32H7)
+#	include <libopencm3/stm32/h7/nvic.h>
+
+#elif defined(GD32F1X0)
+#	include <libopencm3/gd32/f1x0/nvic.h>
+
+#elif defined(EFM32TG)
+#	include <libopencm3/efm32/tg/nvic.h>
+#elif defined(EFM32G)
+#	include <libopencm3/efm32/g/nvic.h>
+#elif defined(EFM32LG)
+#	include <libopencm3/efm32/lg/nvic.h>
+#elif defined(EFM32GG)
+#	include <libopencm3/efm32/gg/nvic.h>
+#elif defined(EFM32HG)
+#	include <libopencm3/efm32/hg/nvic.h>
+#elif defined(EFM32WG)
+#	include <libopencm3/efm32/wg/nvic.h>
+#elif defined(EZR32WG)
+#	include <libopencm3/efm32/ezr32wg/nvic.h>
+
+#elif defined(LPC13XX)
+#	include <libopencm3/lpc13xx/nvic.h>
+#elif defined(LPC17XX)
+#	include <libopencm3/lpc17xx/nvic.h>
+#elif defined(LPC43XX_M4)
+#	include <libopencm3/lpc43xx/m4/nvic.h>
+#elif defined(LPC43XX_M0)
+#	include <libopencm3/lpc43xx/m0/nvic.h>
+
+#elif defined(SAM3A)
+#	include <libopencm3/sam/3a/nvic.h>
+#elif defined(SAM3N)
+#	include <libopencm3/sam/3n/nvic.h>
+#elif defined(SAM3S)
+#	include <libopencm3/sam/3s/nvic.h>
+#elif defined(SAM3U)
+#	include <libopencm3/sam/3u/nvic.h>
+#elif defined(SAM3X)
+#	include <libopencm3/sam/3x/nvic.h>
+#elif defined(SAM4L)
+#	include <libopencm3/sam/4l/nvic.h>
+#elif defined(SAMD)
+#	include <libopencm3/sam/d/nvic.h>
+
+#elif defined(LM3S) || defined(LM4F)
+/* Yes, we use the same interrupt table for both LM3S and LM4F */
+#	include <libopencm3/lm3s/nvic.h>
+
+#elif defined(MSP432E4)
+#   include <libopencm3/msp432/e4/nvic.h>
+
+#elif defined(VF6XX)
+#	include <libopencm3/vf6xx/nvic.h>
+
+#elif defined(SWM050)
+#       include <libopencm3/swm050/nvic.h>
+
+#elif defined(PAC55XX)
+#       include <libopencm3/pac55xx/nvic.h>
+
+#else
+#	warning"no interrupts defined for chipset; NVIC_IRQ_COUNT = 0"
+
+#define NVIC_IRQ_COUNT 0
+
+#endif

3rd/libopencm3/include/libopencm3/docmain.dox

@@ -0,0 +1,21 @@
+/** @mainpage libopencm3 Developer Documentation
+
+@version 1.0.0
+
+@date 7 September 2012
+
+ * The libopencm3 project (previously known as libopenstm32) aims to create
+ * a free/libre/open-source (LGPL v3, or later) firmware library for various
+ * ARM Cortex-M microcontrollers, including ST STM32, Atmel SAM, NXP LPC,
+ * TI Stellaris/Tiva/MSP432, Silabs (Energy Micro) and others.
+ *
+ * @par ""
+ *
+ * See the <a href="http://www.libopencm3.org">libopencm3 wiki</a> for
+ * more information.
+
+LGPL License Terms @ref lgpl_license
+*/
+
+
+

3rd/libopencm3/include/libopencm3/efm32/acmp.h

@@ -0,0 +1,28 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#if defined(EFM32LG)
+#	include <libopencm3/efm32/lg/acmp.h>
+#elif defined(EFM32WG)
+#	include <libopencm3/efm32/wg/acmp.h>
+#elif defined(EZR32WG)
+#	include <libopencm3/efm32/ezr32wg/acmp.h>
+#else
+#	error "efm32 family not defined."
+#endif

3rd/libopencm3/include/libopencm3/efm32/adc.h

@@ -0,0 +1,28 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#if defined(EFM32LG)
+#	include <libopencm3/efm32/lg/adc.h>
+#elif defined(EFM32WG)
+#	include <libopencm3/efm32/wg/adc.h>
+#elif defined(EZR32WG)
+#	include <libopencm3/efm32/ezr32wg/adc.h>
+#else
+#	error "efm32 family not defined."
+#endif

3rd/libopencm3/include/libopencm3/efm32/burtc.h

@@ -0,0 +1,28 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#if defined(EFM32LG)
+#	include <libopencm3/efm32/lg/burtc.h>
+#elif defined(EFM32WG)
+#	include <libopencm3/efm32/wg/burtc.h>
+#elif defined(EZR32WG)
+#	include <libopencm3/efm32/ezr32wg/burtc.h>
+#else
+#	error "efm32 family not defined."
+#endif

3rd/libopencm3/include/libopencm3/efm32/cmu.h

@@ -0,0 +1,30 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#if defined(EFM32LG)
+#	include <libopencm3/efm32/lg/cmu.h>
+#elif defined(EFM32HG)
+#	include <libopencm3/efm32/hg/cmu.h>
+#elif defined(EFM32WG)
+#	include <libopencm3/efm32/wg/cmu.h>
+#elif defined(EZR32WG)
+#	include <libopencm3/efm32/ezr32wg/cmu.h>
+#else
+#	error "efm32 family not defined."
+#endif

3rd/libopencm3/include/libopencm3/efm32/common/acmp_common.h

@@ -0,0 +1,187 @@
+/** @addtogroup acmp_defines
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+/**@{*/
+
+#include <libopencm3/efm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+#define ACMP_CTRL(base)		((base) + 0x000)
+#define ACMP_INPUTSEL(base)	((base) + 0x004)
+#define ACMP_STATUS(base)	((base) + 0x008)
+#define ACMP_IEN(base)		((base) + 0x00C)
+#define ACMP_IF(base)		((base) + 0x010)
+#define ACMP_IFS(base)		((base) + 0x014)
+#define ACMP_IFC(base)		((base) + 0x018)
+#define ACMP_ROUTE(base)	((base) + 0x01C)
+
+/* ACMP_CTRL */
+#define ACMP_CTRL_FULLBIAS	(1 << 31)
+#define ACMP_CTRL_HALFBIAS	(1 << 30)
+
+#define ACMP_CTRL_BIASPROG_SHIFT	(24)
+#define ACMP_CTRL_BIASPROG_MASK		(0xF << ACMP_CTRL_BIASPROG_SHIFT)
+#define ACMP_CTRL_BIASPROG(v)		\
+	(((v) << ACMP_CTRL_BIASPROG_SHIFT) & ACMP_CTRL_BIASPROG_MASK)
+
+#define ACMP_CTRL_IFALL		(1 << 17)
+#define ACMP_CTRL_IRISE		(1 << 16)
+
+#define ACMP_CTRL_WARMTIME_SHIFT	(8)
+#define ACMP_CTRL_WARMTIME_MASK		(0x7 << ACMP_CTRL_WARMTIME_SHIFT)
+#define ACMP_CTRL_WARMTIME(v)		\
+	(((v) << ACMP_CTRL_WARMTIME_SHIFT) & ACMP_CTRL_WARMTIME_MASK)
+#define ACMP_CTRL_WARMTIME_4CYCLES	0
+#define ACMP_CTRL_WARMTIME_8CYCLES	1
+#define ACMP_CTRL_WARMTIME_16CYCLES	2
+#define ACMP_CTRL_WARMTIME_32CYCLES	3
+#define ACMP_CTRL_WARMTIME_64CYCLES	4
+#define ACMP_CTRL_WARMTIME_128CYCLES	5
+#define ACMP_CTRL_WARMTIME_256CYCLES	6
+#define ACMP_CTRL_WARMTIME_512CYCLES	7
+
+#define ACMP_CTRL_HYSTSEL_SHIFT	(8)
+#define ACMP_CTRL_HYSTSEL_MASK		(0x7 << ACMP_CTRL_HYSTSEL_SHIFT)
+#define ACMP_CTRL_HYSTSEL(v)		\
+	(((v) << ACMP_CTRL_HYSTSEL_SHIFT) & ACMP_CTRL_HYSTSEL_MASK)
+#define ACMP_CTRL_HYSTSEL_HYSTx(x)	ACMP_CTRL_HYSTSEL(x)
+#define ACMP_CTRL_HYSTSEL_HYST0		0
+#define ACMP_CTRL_HYSTSEL_HYST1		1
+#define ACMP_CTRL_HYSTSEL_HYST2		2
+#define ACMP_CTRL_HYSTSEL_HYST3		3
+#define ACMP_CTRL_HYSTSEL_HYST4		4
+#define ACMP_CTRL_HYSTSEL_HYST5		5
+#define ACMP_CTRL_HYSTSEL_HYST6		6
+#define ACMP_CTRL_HYSTSEL_HYST7		7
+
+#define ACMP_CTRL_GPIOINV		(1 << 3)
+#define ACMP_CTRL_INACTVAL		(1 << 2)
+#define ACMP_CTRL_MUXEN			(1 << 1)
+#define ACMP_CTRL_EN			(1 << 0)
+
+/* ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESSEL_SHIFT	(28)
+#define ACMP_INPUTSEL_CSRESSEL_MASK	(0x3 << ACMP_INPUTSEL_CSRESSEL_SHIFT)
+#define ACMP_INPUTSEL_CSRESSEL(v)		\
+	(((v) << ACMP_INPUTSEL_CSRESSEL_SHIFT) & ACMP_INPUTSEL_CSRESSEL_MASK)
+#define ACMP_INPUTSEL_CSRESSEL_RESx(x)	ACMP_INPUTSEL_CSRESSEL_RES(x)
+#define ACMP_INPUTSEL_CSRESSEL_RES0	ACMP_INPUTSEL_CSRESSEL_RESx(0)
+#define ACMP_INPUTSEL_CSRESSEL_RES1	ACMP_INPUTSEL_CSRESSEL_RESx(1)
+#define ACMP_INPUTSEL_CSRESSEL_RES2	ACMP_INPUTSEL_CSRESSEL_RESx(2)
+#define ACMP_INPUTSEL_CSRESSEL_RES3	ACMP_INPUTSEL_CSRESSEL_RESx(3)
+
+#define ACMP_INPUTSEL_CSRESEN		(1 << 24)
+#define ACMP_INPUTSEL_LPREF		(1 << 16)
+
+#define ACMP_INPUTSEL_VDDLEVEL_SHIFT	(8)
+#define ACMP_INPUTSEL_VDDLEVEL_MASK	(0x3F << ACMP_INPUTSEL_VDDLEVEL_SHIFT)
+#define ACMP_INPUTSEL_VDDLEVEL(v)	\
+	(((v) << ACMP_INPUTSEL_VDDLEVEL_SHIFT) & ACMP_INPUTSEL_VDDLEVEL_MASK)
+
+#define ACMP_INPUTSEL_NEGSEL_SHIFT	(8)
+#define ACMP_INPUTSEL_NEGSEL_MASK	(0x3F << ACMP_INPUTSEL_NEGSEL_SHIFT)
+#define ACMP_INPUTSEL_NEGSEL(v)		\
+	(((v) << ACMP_INPUTSEL_NEGSEL_SHIFT) & ACMP_INPUTSEL_NEGSEL_MASK)
+#define ACMP_INPUTSEL_NEGSEL_CHx(x)	ACMP_INPUTSEL_NEGSEL(x)
+#define ACMP_INPUTSEL_NEGSEL_CH0	0
+#define ACMP_INPUTSEL_NEGSEL_CH1	1
+#define ACMP_INPUTSEL_NEGSEL_CH2	2
+#define ACMP_INPUTSEL_NEGSEL_CH3	3
+#define ACMP_INPUTSEL_NEGSEL_CH4	4
+#define ACMP_INPUTSEL_NEGSEL_CH5	5
+#define ACMP_INPUTSEL_NEGSEL_CH6	6
+#define ACMP_INPUTSEL_NEGSEL_CH7	7
+#define ACMP_INPUTSEL_NEGSEL_1V25	8
+#define ACMP_INPUTSEL_NEGSEL_2V5	9
+#define ACMP_INPUTSEL_NEGSEL_VDD	10
+#define ACMP_INPUTSEL_NEGSEL_CAPSENSE	11
+#define ACMP_INPUTSEL_NEGSEL_DAC0CH0	12
+#define ACMP_INPUTSEL_NEGSEL_DAC0CH1	13
+
+#define ACMP_INPUTSEL_POSSEL_SHIFT	(0)
+#define ACMP_INPUTSEL_POSSEL_MASK	(0x7 << ACMP_INPUTSEL_POSSEL_SHIFT)
+#define ACMP_INPUTSEL_POSSEL(v)		\
+	(((v) << ACMP_INPUTSEL_LPOSSELL_SHIFT) & ACMP_INPUTSEL_LPOSSELL_MASK)
+#define ACMP_INPUTSEL_POSSEL_CHx(x)	ACMP_INPUTSEL_POSSEL(x)
+#define ACMP_INPUTSEL_POSSEL_CH0	0
+#define ACMP_INPUTSEL_POSSEL_CH1	1
+#define ACMP_INPUTSEL_POSSEL_CH2	2
+#define ACMP_INPUTSEL_POSSEL_CH3	3
+#define ACMP_INPUTSEL_POSSEL_CH4	4
+#define ACMP_INPUTSEL_POSSEL_CH5	5
+#define ACMP_INPUTSEL_POSSEL_CH6	6
+#define ACMP_INPUTSEL_POSSEL_CH7	7
+
+/* ACMP_STATUS */
+#define ACMP_STATUS_ACMPOUT		(1 << 1)
+#define ACMP_STATUS_ACMPACT		(1 << 0)
+
+/* ACMP_IEN */
+#define ACMP_IEN_WARMUP			(1 << 1)
+#define ACMP_IEN_EDGE			(1 << 0)
+
+/* ACMP_IF */
+#define ACMP_IF_WARMUP			(1 << 1)
+#define ACMP_IF_EDGE			(1 << 0)
+
+/* ACMP_IFS */
+#define ACMP_IFS_WARMUP			(1 << 1)
+#define ACMP_IFS_EDGE			(1 << 0)
+
+/* ACMP_IFC */
+#define ACMP_IFC_WARMUP			(1 << 1)
+#define ACMP_IFC_EDGE			(1 << 0)
+
+/* ACMP_ROUTE */
+#define ACMP_ROUTE_LOCATION_SHIFT	(8)
+#define ACMP_ROUTE_LOCATION_MASK	(0x7 << ACMP_ROUTE_LOCATION_SHIFT)
+#define ACMP_ROUTE_LOCATION(v)		\
+	(((v) << ACMP_ROUTE_LOCATION_SHIFT) & ACMP_ROUTE_LOCATION_MASK)
+#define ACMP_ROUTE_LOCATION_LOCx(x)	ACMP_ROUTE_LOCATION(x)
+#define ACMP_ROUTE_LOCATION_LOC0	ACMP_ROUTE_LOCATIONx(0)
+#define ACMP_ROUTE_LOCATION_LOC1	ACMP_ROUTE_LOCATIONx(1)
+#define ACMP_ROUTE_LOCATION_LOC2	ACMP_ROUTE_LOCATIONx(2)
+
+#define ACMP_ROUTE_ACMPPEN		(1 << 0)
+
+#define ACMP0			ACMP0_BASE
+#define ACMP0_CTRL		ACMP_CTRL(ACMP0)
+#define ACMP0_INPUTSEL		ACMP_INPUTSEL(ACMP0)
+#define ACMP0_STATUS		ACMP_STATUS(ACMP0)
+#define ACMP0_IEN		ACMP_IEN(ACMP0)
+#define ACMP0_IF		ACMP_IF(ACMP0)
+#define ACMP0_IFS		ACMP_IFS(ACMP0)
+#define ACMP0_IFC		ACMP_IFC(ACMP0)
+#define ACMP0_ROUTE		ACMP_ROUTE(ACMP0)
+
+#define ACMP1			ACMP1_BASE
+#define ACMP1_CTRL		ACMP_CTRL(ACMP1)
+#define ACMP1_INPUTSEL		ACMP_INPUTSEL(ACMP1)
+#define ACMP1_STATUS		ACMP_STATUS(ACMP1)
+#define ACMP1_IEN		ACMP_IEN(ACMP1)
+#define ACMP1_IF		ACMP_IF(ACMP1)
+#define ACMP1_IFS		ACMP_IFS(ACMP1)
+#define ACMP1_IFC		ACMP_IFC(ACMP1)
+#define ACMP1_ROUTE		ACMP_ROUTE(ACMP1)
+
+/**@}*/

3rd/libopencm3/include/libopencm3/efm32/common/adc_common.h

@@ -0,0 +1,457 @@
+/** @addtogroup adc_defines
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+
+#pragma once
+
+#include <libopencm3/efm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+#define ADC_CTRL(base)		MMIO32((base) + 0x000)
+#define ADC_CMD(base)		MMIO32((base) + 0x004)
+#define ADC_STATUS(base)	MMIO32((base) + 0x008)
+#define ADC_SINGLECTRL(base)	MMIO32((base) + 0x00C)
+#define ADC_SCANCTRL(base)	MMIO32((base) + 0x010)
+#define ADC_IEN(base)		MMIO32((base) + 0x014)
+#define ADC_IF(base)		MMIO32((base) + 0x018)
+#define ADC_IFS(base)		MMIO32((base) + 0x01C)
+#define ADC_IFC(base)		MMIO32((base) + 0x020)
+#define ADC_SINGLEDATA(base)	MMIO32((base) + 0x024)
+#define ADC_SCANDATA(base)	MMIO32((base) + 0x028)
+#define ADC_SINGLEDATAP(base)	MMIO32((base) + 0x02C)
+#define ADC_SCANDATAP(base)	MMIO32((base) + 0x030)
+#define ADC_CAL(base)		MMIO32((base) + 0x034)
+#define ADC_BIASPROG(base)	MMIO32((base) + 0x03C)
+
+/* ADC_CTRL */
+#define ADC_CTRL_OVERSEL_SHIFT	(24)
+#define ADC_CTRL_OVERSEL_MASK	(0xF << ADC_CTRL_OVERSEL_SHIFT)
+#define ADC_CTRL_OVERSEL(v)	\
+	(((v) << ADC_CTRL_OVERSEL_SHIFT) & ADC_CTRL_OVERSEL_MASK)
+#define ADC_CTRL_OVERSEL_X2	0
+#define ADC_CTRL_OVERSEL_X4	1
+#define ADC_CTRL_OVERSEL_X8	2
+#define ADC_CTRL_OVERSEL_X16	3
+#define ADC_CTRL_OVERSEL_X32	4
+#define ADC_CTRL_OVERSEL_X64	5
+#define ADC_CTRL_OVERSEL_X128	6
+#define ADC_CTRL_OVERSEL_X256	7
+#define ADC_CTRL_OVERSEL_X512	8
+#define ADC_CTRL_OVERSEL_X1024	9
+#define ADC_CTRL_OVERSEL_X2048	10
+#define ADC_CTRL_OVERSEL_X4096	11
+
+#define ADC_CTRL_TIMEBASE_SHIFT	(16)
+#define ADC_CTRL_TIMEBASE_MASK	(0x3F << ADC_CTRL_TIMEBASE_SHIFT)
+#define ADC_CTRL_TIMEBASE(v)	\
+	(((v) << ADC_CTRL_TIMEBASE_SHIFT) & ADC_CTRL_TIMEBASE_MASK)
+
+#define ADC_CTRL_PRESC_SHIFT	(8)
+#define ADC_CTRL_PRESC_MASK	(0x3F << ADC_CTRL_PRESC_SHIFT)
+#define ADC_CTRL_PRESC(v)	\
+	(((v) << ADC_CTRL_PRESC_SHIFT) & ADC_CTRL_PRESC_MASK)
+
+#define ADC_CTRL_LPFMODE_SHIFT	(4)
+#define ADC_CTRL_LPFMODE_MASK	(0x3 << ADC_CTRL_LPFMODE_SHIFT)
+#define ADC_CTRL_LPFMODE(v)	\
+	(((v) << ADC_CTRL_LPFMODE_SHIFT) & ADC_CTRL_LPFMODE_MASK)
+#define ADC_CTRL_LPFMODE_BYPASS	0
+#define ADC_CTRL_LPFMODE_DECAP	1
+#define ADC_CTRL_LPFMODE_RCFILT	2
+
+#define ADC_CTRL_TAILGATE	(1 << 3)
+
+#define ADC_CTRL_WARMUPMODE_SHIFT	(0)
+#define ADC_CTRL_WARMUPMODE_MASK	(0x3 << ADC_CTRL_WARMUPMODE_SHIFT)
+#define ADC_CTRL_WARMUPMODE(v)		\
+	(((v) << ADC_CTRL_WARMUPMODE_SHIFT) & ADC_CTRL_WARMUPMODE_MASK)
+#define ADC_CTRL_WARMUPMODE_NORMAL	0
+#define ADC_CTRL_WARMUPMODE_FASTBG	1
+#define ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM	2
+#define ADC_CTRL_WARMUPMODE_KEEPADCWARM		3
+
+/* ADC_CMD */
+#define ADC_CMD_SCANSTOP	(1 << 3)
+#define ADC_CMD_SCANSTART	(1 << 2)
+#define ADC_CMD_SINGLESTOP	(1 << 1)
+#define ADC_CMD_SINGLESTART	(1 << 0)
+
+/* ADC_STATUS */
+#define ADC_STATUS_SCANDATASRC_SHIFT	(0)
+#define ADC_STATUS_SCANDATASRC_MASK	(0x7 << ADC_STATUS_SCANDATASRC_SHIFT)
+#define ADC_STATUS_SCANDATASRC(v)	\
+	(((v) << ADC_STATUS_SCANDATASRC_SHIFT) & ADC_STATUS_SCANDATASRC_MASK)
+
+#define ADC_STATUS_SCANDV		(1 << 17)
+#define ADC_STATUS_SINGLEDV		(1 << 16)
+#define ADC_STATUS_WARM			(1 << 12)
+#define ADC_STATUS_SCANREFWARM		(1 << 9)
+#define ADC_STATUS_SINGLEREFWARM	(1 << 8)
+#define ADC_STATUS_SCANACT		(1 << 1)
+#define ADC_STATUS_SINGLEACT		(1 << 0)
+
+/* ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_PRSSEL_SHIFT	(28)
+#define ADC_SINGLECTRL_PRSSEL_MASK	(0xF << ADC_SINGLECTRL_PRSSEL_SHIFT)
+#define ADC_SINGLECTRL_PRSSEL(v)	\
+	(((v)  << ADC_SINGLECTRL_PRSSEL_SHIFT) & ADC_SINGLECTRL_PRSSEL_MASK)
+#define ADC_SINGLECTRL_PRSSEL_PRSCHx(x)	ADC_SINGLECTRL_PRSSEL(x)
+#define ADC_SINGLECTRL_PRSSEL_PRSCH0	0
+#define ADC_SINGLECTRL_PRSSEL_PRSCH1	1
+#define ADC_SINGLECTRL_PRSSEL_PRSCH2	2
+#define ADC_SINGLECTRL_PRSSEL_PRSCH3	3
+#define ADC_SINGLECTRL_PRSSEL_PRSCH4	4
+#define ADC_SINGLECTRL_PRSSEL_PRSCH5	5
+#define ADC_SINGLECTRL_PRSSEL_PRSCH6	6
+#define ADC_SINGLECTRL_PRSSEL_PRSCH7	7
+#define ADC_SINGLECTRL_PRSSEL_PRSCH8	8
+#define ADC_SINGLECTRL_PRSSEL_PRSCH9	9
+#define ADC_SINGLECTRL_PRSSEL_PRSCH10	10
+#define ADC_SINGLECTRL_PRSSEL_PRSCH11	11
+
+#define ADC_SINGLECTRL_PRSEN	(1 << 24)
+
+#define ADC_SINGLECTRL_AT_SHIFT	(20)
+#define ADC_SINGLECTRL_AT_MASK	(0xF << ADC_SINGLECTRL_AT_SHIFT)
+#define ADC_SINGLECTRL_AT(v)	\
+	(((v) << ADC_SINGLECTRL_AT_SHIFT) & ADC_SINGLECTRL_AT_MASK)
+#define ADC_SINGLECTRL_AT_1CYCLE	0x0
+#define ADC_SINGLECTRL_AT_2CYCLES	0x1
+#define ADC_SINGLECTRL_AT_4CYCLES	0x2
+#define ADC_SINGLECTRL_AT_8CYCLES	0x3
+#define ADC_SINGLECTRL_AT_16CYCLES	0x4
+#define ADC_SINGLECTRL_AT_32CYCLES	0x5
+#define ADC_SINGLECTRL_AT_64CYCLES	0x6
+#define ADC_SINGLECTRL_AT_128CYCLES	0x7
+#define ADC_SINGLECTRL_AT_256CYCLES	0x8
+
+#define ADC_SINGLECTRL_REF_SHIFT	(16)
+#define ADC_SINGLECTRL_REF_MASK		(0xF << ADC_SINGLECTRL_REF_SHIFT)
+#define ADC_SINGLECTRL_REF(v)		\
+	(((v) << ADC_SINGLECTRL_REF_SHIFT) & ADC_SINGLECTRL_REF_MASK)
+#define ADC_SINGLECTRL_REF_1V25		0
+#define ADC_SINGLECTRL_REF_2V5		1
+#define ADC_SINGLECTRL_REF_VDD		2
+#define ADC_SINGLECTRL_REF_5VDIFF	3
+#define ADC_SINGLECTRL_REF_EXTSINGLE	4
+#define ADC_SINGLECTRL_REF_2XEXTDIFF	5
+#define ADC_SINGLECTRL_REF_2XVDD	6
+
+#define ADC_SINGLECTRL_INPUTSEL_SHIFT	(8)
+#define ADC_SINGLECTRL_INPUTSEL_MASK	(0xF << ADC_SINGLECTRL_INPUTSEL_SHIFT)
+#define ADC_SINGLECTRL_INPUTSEL(v)	\
+	(((v) << ADC_SINGLECTRL_INPUTSEL_SHIFT) & ADC_SINGLECTRL_INPUTSEL_MASK)
+/* DIFF=0 */
+#define ADC_SINGLECTRL_INPUTSEL_CHx(x)		ADC_SINGLECTRL_INPUTSEL(x)
+#define ADC_SINGLECTRL_INPUTSEL_CH0		0
+#define ADC_SINGLECTRL_INPUTSEL_CH1		1
+#define ADC_SINGLECTRL_INPUTSEL_CH2		2
+#define ADC_SINGLECTRL_INPUTSEL_CH3		3
+#define ADC_SINGLECTRL_INPUTSEL_CH4		4
+#define ADC_SINGLECTRL_INPUTSEL_CH5		5
+#define ADC_SINGLECTRL_INPUTSEL_CH6		6
+#define ADC_SINGLECTRL_INPUTSEL_CH7		7
+#define ADC_SINGLECTRL_INPUTSEL_TEMP		8
+#define ADC_SINGLECTRL_INPUTSEL_VDDDIV3		9
+#define ADC_SINGLECTRL_INPUTSEL_VDD		10
+#define ADC_SINGLECTRL_INPUTSEL_VSS		11
+#define ADC_SINGLECTRL_INPUTSEL_VREFDIV2	12
+#define ADC_SINGLECTRL_INPUTSEL_DAC0OUT0	13
+#define ADC_SINGLECTRL_INPUTSEL_DAC0OUT1	14
+/* DIFF=1 */
+#define ADC_SINGLECTRL_INPUTSEL_CH0CH1		0
+#define ADC_SINGLECTRL_INPUTSEL_CH2CH3		1
+#define ADC_SINGLECTRL_INPUTSEL_CH4CH5		2
+#define ADC_SINGLECTRL_INPUTSEL_CH6CH7		3
+#define ADC_SINGLECTRL_INPUTSEL_DIFF0		4
+
+#define ADC_SINGLECTRL_RES_SHIFT	(4)
+#define ADC_SINGLECTRL_RES_MASK		(0x3 << ADC_SINGLECTRL_RES_SHIFT)
+#define ADC_SINGLECTRL_RES(v)		\
+	(((v) << ADC_SINGLECTRL_RES_SHIFT) & ADC_SINGLECTRL_RES_MASK)
+#define ADC_SINGLECTRL_RES_12BIT	0
+#define ADC_SINGLECTRL_RES_8BIT		1
+#define ADC_SINGLECTRL_RES_6BIT		2
+#define ADC_SINGLECTRL_RES_OVS		3
+
+#define ADC_SINGLECTRL_ADJ	(1 << 2)
+#define ADC_SINGLECTRL_DIFF	(1 << 1)
+#define ADC_SINGLECTRL_REP	(1 << 0)
+
+/* ADC_SCANCTRL */
+#define ADC_SCANCTRL_PRSSEL_SHIFT	(28)
+#define ADC_SCANCTRL_PRSSEL_MASK	(0xF << ADC_SCANCTRL_PRSSEL_SHIFT)
+#define ADC_SCANCTRL_PRSSEL(v)		\
+	(((v)  << ADC_SCANCTRL_PRSSEL_SHIFT) & ADC_SCANCTRL_PRSSEL_MASK)
+#define ADC_SCANCTRL_PRSSEL_PRSCHx(x)	ADC_SCANCTRL_PRSSEL(x)
+#define ADC_SCANCTRL_PRSSEL_PRSCH0	0
+#define ADC_SCANCTRL_PRSSEL_PRSCH1	1
+#define ADC_SCANCTRL_PRSSEL_PRSCH2	2
+#define ADC_SCANCTRL_PRSSEL_PRSCH3	3
+#define ADC_SCANCTRL_PRSSEL_PRSCH4	4
+#define ADC_SCANCTRL_PRSSEL_PRSCH5	5
+#define ADC_SCANCTRL_PRSSEL_PRSCH6	6
+#define ADC_SCANCTRL_PRSSEL_PRSCH7	7
+#define ADC_SCANCTRL_PRSSEL_PRSCH8	8
+#define ADC_SCANCTRL_PRSSEL_PRSCH9	9
+#define ADC_SCANCTRL_PRSSEL_PRSCH10	10
+#define ADC_SCANCTRL_PRSSEL_PRSCH11	11
+
+#define ADC_SCANCTRL_PRSEN	(1 << 24)
+
+#define ADC_SCANCTRL_AT_SHIFT	(20)
+#define ADC_SCANCTRL_AT_MASK	(0xF << ADC_SCANCTRL_AT_SHIFT)
+#define ADC_SCANCTRL_AT(v)			\
+	(((v) << ADC_SCANCTRL_AT_SHIFT) & ADC_SCANCTRL_AT_MASK)
+#define ADC_SCANCTRL_AT_1CYCLE		0
+#define ADC_SCANCTRL_AT_2CYCLES		1
+#define ADC_SCANCTRL_AT_4CYCLES		2
+#define ADC_SCANCTRL_AT_8CYCLES		3
+#define ADC_SCANCTRL_AT_16CYCLES	4
+#define ADC_SCANCTRL_AT_32CYCLES	5
+#define ADC_SCANCTRL_AT_64CYCLES	6
+#define ADC_SCANCTRL_AT_128CYCLES	7
+#define ADC_SCANCTRL_AT_256CYCLES	8
+
+#define ADC_SCANCTRL_REF_SHIFT	(16)
+#define ADC_SCANCTRL_REF_MASK	(0xF << ADC_SCANCTRL_REF_SHIFT)
+#define ADC_SCANCTRL_REF(v)			\
+	(((v) << ADC_SCANCTRL_REF_SHIFT) & ADC_SCANCTRL_REF_MASK)
+#define ADC_SCANCTRL_REF_1V25		0
+#define ADC_SCANCTRL_REF_2V5		1
+#define ADC_SCANCTRL_REF_VDD		2
+#define ADC_SCANCTRL_REF_5VDIFF		3
+#define ADC_SCANCTRL_REF_EXTSCAN	4
+#define ADC_SCANCTRL_REF_2XEXTDIFF	5
+#define ADC_SCANCTRL_REF_2XVDD		6
+
+
+#define ADC_SCANCTRL_INPUTSEL_SHIFT	(8)
+#define ADC_SCANCTRL_INPUTSEL_MASK	(0xFF << ADC_SCANCTRL_INPUTSEL_SHIFT)
+#define ADC_SCANCTRL_INPUTSEL(v)		\
+	(((v) << ADC_SCANCTRL_INPUTSEL_SHIFT) & ADC_SCANCTRL_INPUTSEL_MASK)
+/* DIFF=0 */
+#define ADC_SCANCTRL_INPUTSEL_CHx(x)	ADC_SCANCTRL_INPUTSEL(1 << (x))
+#define ADC_SCANCTRL_INPUTSEL_CH0	ADC_SCANCTRL_INPUTSEL_CHx(0)
+#define ADC_SCANCTRL_INPUTSEL_CH1	ADC_SCANCTRL_INPUTSEL_CHx(1)
+#define ADC_SCANCTRL_INPUTSEL_CH2	ADC_SCANCTRL_INPUTSEL_CHx(2)
+#define ADC_SCANCTRL_INPUTSEL_CH3	ADC_SCANCTRL_INPUTSEL_CHx(3)
+#define ADC_SCANCTRL_INPUTSEL_CH4	ADC_SCANCTRL_INPUTSEL_CHx(4)
+#define ADC_SCANCTRL_INPUTSEL_CH5	ADC_SCANCTRL_INPUTSEL_CHx(5)
+#define ADC_SCANCTRL_INPUTSEL_CH6	ADC_SCANCTRL_INPUTSEL_CHx(6)
+#define ADC_SCANCTRL_INPUTSEL_CH7	ADC_SCANCTRL_INPUTSEL_CHx(7)
+/* DIFF=1 */
+#define ADC_SCANCTRL_INPUTSEL_CH0CH1	ADC_SCANCTRL_INPUTSEL(1 << 0)
+#define ADC_SCANCTRL_INPUTSEL_CH2CH3	ADC_SCANCTRL_INPUTSEL(1 << 1)
+#define ADC_SCANCTRL_INPUTSEL_CH4CH5	ADC_SCANCTRL_INPUTSEL(1 << 2)
+#define ADC_SCANCTRL_INPUTSEL_CH6CH7	ADC_SCANCTRL_INPUTSEL(1 << 3)
+
+#define ADC_SCANCTRL_RES_SHIFT		(4)
+#define ADC_SCANCTRL_RES_MASK		(0x3 << ADC_SCANCTRL_RES_SHIFT)
+#define ADC_SCANCTRL_RES(v)			\
+	(((v) << ADC_SCANCTRL_RES_SHIFT) & ADC_SCANCTRL_RES_MASK)
+#define ADC_SCANCTRL_RES_12BIT		0
+#define ADC_SCANCTRL_RES_8BIT		1
+#define ADC_SCANCTRL_RES_6BIT		2
+#define ADC_SCANCTRL_RES_OVS		3
+
+#define ADC_SCANCTRL_ADJ	(1 << 2)
+#define ADC_SCANCTRL_DIFF	(1 << 1)
+#define ADC_SCANCTRL_REP	(1 << 0)
+
+/* ADC_IEN */
+#define ADC_IEN_SCANOF		(1 << 9)
+#define ADC_IEN_SINGLEOF	(1 << 8)
+#define ADC_IEN_SCAN		(1 << 1)
+#define ADC_IEN_SINGLE		(1 << 0)
+
+/* ADC_IF */
+#define ADC_IF_SCANOF		(1 << 9)
+#define ADC_IF_SINGLEOF		(1 << 8)
+#define ADC_IF_SCAN		(1 << 1)
+#define ADC_IF_SINGLE		(1 << 0)
+
+/* ADC_IFS */
+#define ADC_IFS_SCANOF		(1 << 9)
+#define ADC_IFS_SINGLEOF	(1 << 8)
+#define ADC_IFS_SCAN		(1 << 1)
+#define ADC_IFS_SINGLE		(1 << 0)
+
+/* ADC_IFC */
+#define ADC_IFC_SCANOF		(1 << 9)
+#define ADC_IFC_SINGLEOF	(1 << 8)
+#define ADC_IFC_SCAN		(1 << 1)
+#define ADC_IFC_SINGLE		(1 << 0)
+
+/* ADC_CAL */
+#define ADC_CAL_SCANGAIN_SHIFT	(24)
+#define ADC_CAL_SCANGAIN_MASK	(0x7F)
+
+#define ADC_CAL_SCANOFF_SHIFT	(16)
+#define ADC_CAL_SCANOFF_MASK	(0x7F)
+
+#define ADC_CAL_SINGLEGAIN_SHIFT (8)
+#define ADC_CAL_SINGLEGAIN_MASK	(0x7F)
+
+#define ADC_CAL_SINGLEOFF_SHIFT	(0)
+#define ADC_CAL_SINGLEOFF_MASK	(0x7F)
+
+/* ADC_BIASPROG */
+#define ADC_BIASPROG_COMPBIAS_SHIFT	(8)
+#define ADC_BIASPROG_COMPBIAS_MASK	(0xF)
+
+#define ADC_BIASPROG_HALFBIAS		(1 << 6)
+
+#define ADC_BIASPROG_BIASPROG_SHIFT	(0)
+#define ADC_BIASPROG_BIASPROG_MASK	(0xF)
+
+/* ADC0 */
+#define ADC0			ADC0_BASE
+#define ADC0_CTRL		ADC_CTRL(ADC0)
+#define ADC0_CMD		ADC_CMD(ADC0)
+#define ADC0_STATUS		ADC_STATUS(ADC0)
+#define ADC0_SINGLECTRL		ADC_SINGLECTRL(ADC0)
+#define ADC0_SCANCTRL		ADC_SCANCTRL(ADC0)
+#define ADC0_IEN		ADC_IEN(ADC0)
+#define ADC0_IF			ADC_IF(ADC0)
+#define ADC0_IFS		ADC_IFS(ADC0)
+#define ADC0_IFC		ADC_IFC(ADC0)
+#define ADC0_SINGLEDATA		ADC_SINGLEDATA(ADC0)
+#define ADC0_SCANDATA		ADC_SCANDATA(ADC0)
+#define ADC0_SINGLEDATAP	ADC_SINGLEDATAP(ADC0)
+#define ADC0_SCANDATAP		ADC_SCANDATAP(ADC0)
+#define ADC0_CAL		ADC_CAL(ADC0)
+#define ADC0_BIASPROG		ADC_BIASPROG(ADC0)
+
+/** @defgroup adc_ch ADC Channel Number
+@{*/
+#define ADC_CH0			0
+#define ADC_CH1			1
+#define ADC_CH2			2
+#define ADC_CH3			3
+#define ADC_CH4			4
+#define ADC_CH5			5
+#define ADC_CH6			6
+#define ADC_CH7			7
+#define ADC_CH_TEMP		8
+#define ADC_CH_VDDDIV3		9
+#define ADC_CH_VDD		10
+#define ADC_CH_VSS		11
+#define ADC_CH_VREFDIV2		12
+#define ADC_CH_DAC0OUT0		13
+#define ADC_CH_DAC0OUT1		14
+
+#define ADC_CH_CH0CH1		0
+#define ADC_CH_CH2CH3		1
+#define ADC_CH_CH4CH5		2
+#define ADC_CH_CH6CH7		3
+#define ADC_CH_DIFF0		4
+/**@}*/
+
+BEGIN_DECLS
+
+void adc_set_oversampling(uint32_t adc, uint32_t oversamp);
+void adc_set_warm_up(uint32_t adc, uint8_t clocks);
+void adc_set_clock_prescaler(uint32_t adc, uint8_t factor);
+void adc_set_lowpass_filter(uint32_t adc, uint32_t lpfmode);
+
+void adc_enable_tailgating(uint32_t adc);
+void adc_disable_tailgating(uint32_t adc);
+
+void adc_set_warm_up_mode(uint32_t adc, uint32_t warmupmode);
+
+void adc_single_start(uint32_t adc);
+void adc_single_stop(uint32_t adc);
+
+void adc_scan_start(uint32_t adc);
+void adc_scan_stop(uint32_t adc);
+
+/* TODO: ADC_STATUS */
+
+void adc_set_single_prs_trigger(uint32_t adc, uint8_t prssel);
+void adc_enable_single_prs_trigger(uint32_t adc);
+void adc_disable_single_prs_trigger(uint32_t adc);
+void adc_set_single_acquisition_cycle(uint32_t adc, uint32_t at);
+void adc_set_single_reference(uint32_t adc, uint32_t ref);
+void adc_set_single_channel(uint32_t adc, uint8_t ch);
+void adc_set_single_resolution(uint32_t adc, uint32_t res);
+void adc_set_single_left_aligned(uint32_t adc);
+void adc_set_single_right_aligned(uint32_t adc);
+void adc_set_single_single_ended(uint32_t adc);
+void adc_set_single_differential(uint32_t adc);
+void adc_enable_single_repeat_conv(uint32_t adc);
+void adc_disable_single_repeat_conv(uint32_t adc);
+
+void adc_set_scan_prs_trigger(uint32_t adc, uint8_t prssel);
+void adc_enable_scan_prs_trigger(uint32_t adc);
+void adc_disable_scan_prs_trigger(uint32_t adc);
+void adc_set_scan_acquisition_cycle(uint32_t adc, uint32_t at);
+void adc_set_scan_reference(uint32_t adc, uint32_t ref);
+void adc_set_scan_channel(uint32_t adc, uint8_t length,
+			  uint8_t channel[]);
+void adc_set_scan_resolution(uint32_t adc, uint32_t res);
+void adc_set_scan_left_aligned(uint32_t adc);
+void adc_set_scan_right_aligned(uint32_t adc);
+void adc_set_scan_single_ended(uint32_t adc);
+void adc_set_scan_differential(uint32_t adc);
+void adc_enable_scan_repeat_conv(uint32_t adc);
+void adc_disable_scan_repeat_conv(uint32_t adc);
+
+void adc_enable_single_result_overflow_interrupt(uint32_t adc);
+void adc_disable_single_result_overflow_interrupt(uint32_t adc);
+void adc_enable_single_conversion_complete_interrupt(uint32_t adc);
+void adc_disable_single_conversion_complete_interrupt(uint32_t adc);
+void adc_enable_scan_result_overflow_interrupt(uint32_t adc);
+void adc_disable_scan_result_overflow_interrupt(uint32_t adc);
+void adc_enable_scan_conversion_complete_interrupt(uint32_t adc);
+void adc_disable_scan_conversion_complete_interrupt(uint32_t adc);
+
+bool adc_get_single_result_overflow_flag(uint32_t adc);
+bool adc_get_single_conversion_complete_flag(uint32_t adc);
+bool adc_get_scan_result_overflow_flag(uint32_t adc);
+bool adc_get_scan_conversion_complete_flag(uint32_t adc);
+
+void adc_set_single_result_overflow_flag(uint32_t adc);
+void adc_set_single_conversion_complete_flag(uint32_t adc);
+void adc_set_scan_result_overflow_flag(uint32_t adc);
+void adc_set_scan_conversion_complete_flag(uint32_t adc);
+
+void adc_clear_single_result_overflow_flag(uint32_t adc);
+void adc_clear_single_conversion_complete_flag(uint32_t adc);
+void adc_clear_scan_result_overflow_flag(uint32_t adc);
+void adc_clear_scan_conversion_complete_flag(uint32_t adc);
+
+uint32_t adc_single_data(uint32_t adc);
+uint32_t adc_scan_data(uint32_t adc);
+
+uint32_t adc_single_data_peak(uint32_t adc);
+uint32_t adc_scan_data_peak(uint32_t adc);
+
+void adc_set_calibration_scan_gain(uint32_t adc, uint8_t scan_gain);
+void adc_set_calibration_scan_offset(uint32_t adc, uint8_t scan_offset);
+
+void adc_set_calibration_single_gain(uint32_t adc, uint8_t single_gain);
+void adc_set_calibration_single_offset(uint32_t adc, uint8_t single_offset);
+
+END_DECLS
+
+/**@}*/

3rd/libopencm3/include/libopencm3/efm32/common/burtc_common.h

@@ -0,0 +1,173 @@
+/** @addtogroup burtc_defines
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/efm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/**@{*/
+
+#define BURTC_CTRL	MMIO32(BURTC_BASE + 0x000)
+#define BURTC_LPMODE	MMIO32(BURTC_BASE + 0x004)
+#define BURTC_CNT	MMIO32(BURTC_BASE + 0x008)
+#define BURTC_COMP0	MMIO32(BURTC_BASE + 0x00C)
+#define BURTC_TIMESTAMP	MMIO32(BURTC_BASE + 0x010)
+#define BURTC_LFXOFDET	MMIO32(BURTC_BASE + 0x014)
+#define BURTC_STATUS	MMIO32(BURTC_BASE + 0x018)
+#define BURTC_CMD	MMIO32(BURTC_BASE + 0x01C)
+#define BURTC_POWERDOWN	MMIO32(BURTC_BASE + 0x020)
+#define BURTC_LOCK	MMIO32(BURTC_BASE + 0x024)
+#define BURTC_IF	MMIO32(BURTC_BASE + 0x028)
+#define BURTC_IFS	MMIO32(BURTC_BASE + 0x02C)
+#define BURTC_IFC	MMIO32(BURTC_BASE + 0x030)
+#define BURTC_IEN	MMIO32(BURTC_BASE + 0x034)
+#define BURTC_FREEZE	MMIO32(BURTC_BASE + 0x038)
+#define BURTC_SYNCBUSY	MMIO32(BURTC_BASE + 0x03C)
+
+#define RETx_REG(x)	MMIO32(BURTC_BASE + 0x100 + (4 * (x)))
+/* [for ease] */
+#define BURTC_RETx(x)	RETx_REG(x)
+
+/* BURTC_CTRL */
+#define BURTC_CTRL_BUMODETSEN		(1 << 14)
+
+#define BURTC_CTRL_CLKSEL_SHIFT		(8)
+#define BURTC_CTRL_CLKSEL_MASK		(0x3 << BURTC_CTRL_CLKSEL_SHIFT)
+#define BURTC_CTRL_CLKSEL(v)		\
+	(((v) << BURTC_CTRL_CLKSEL_SHIFT) & BURTC_CTRL_CLKSEL_MASK)
+#define BURTC_CTRL_CLKSEL_NONE		0
+#define BURTC_CTRL_CLKSEL_LFRCO		1
+#define BURTC_CTRL_CLKSEL_LFXO		2
+#define BURTC_CTRL_CLKSEL_ULFRCO	3
+
+#define BURTC_CTRL_PRESC_SHIFT	(12)
+#define BURTC_CTRL_PRESC_MASK	(0x7 << BURTC_CTRL_PRESC_SHIFT)
+#define BURTC_CTRL_PRESC(v)	\
+	(((v) << BURTC_CTRL_PRESC_SHIFT) & BURTC_CTRL_PRESC_MASK)
+#define BURTC_CTRL_PRESC_DIV1	0
+#define BURTC_CTRL_PRESC_DIV2	1
+#define BURTC_CTRL_PRESC_DIV4	2
+#define BURTC_CTRL_PRESC_DIV8	3
+#define BURTC_CTRL_PRESC_DIV16	4
+#define BURTC_CTRL_PRESC_DIV32	5
+#define BURTC_CTRL_PRESC_DIV64	6
+#define BURTC_CTRL_PRESC_DIV128	7
+#define BURTC_CTRL_PRESC_NODIV	BURTC_CTRL_PRESC_DIV1
+
+#define BURTC_CTRL_LPCOMPC_SHIFT	(5)
+#define BURTC_CTRL_LPCOMPC_MASK		(0x7 << BURTC_CTRL_LPCOMPC_SHIFT)
+#define BURTC_CTRL_LPCOMPC(v)		\
+	(((v) << BURTC_CTRL_LPCOMPC_SHIFT) & BURTC_CTRL_LPCOMPC_MASK)
+#define BURTC_CTRL_LPCOMPC_IGNxLSB(x)	BURTC_CTRL_LPCOMPC(x)
+#define BURTC_CTRL_LPCOMPC_IGN0LSB	0
+#define BURTC_CTRL_LPCOMPC_IGN1LSB	1
+#define BURTC_CTRL_LPCOMPC_IGN2LSB	2
+#define BURTC_CTRL_LPCOMPC_IGN3LSB	3
+#define BURTC_CTRL_LPCOMPC_IGN4LSB	4
+#define BURTC_CTRL_LPCOMPC_IGN5LSB	5
+#define BURTC_CTRL_LPCOMPC_IGN6LSB	6
+#define BURTC_CTRL_LPCOMPC_IGN7LSB	7
+
+#define BURTC_CTRL_COMP0TOP	(1 << 4)
+#define BURTC_CTRL_RSTEN	(1 << 3)
+#define BURTC_CTRL_DEBUGRUN	(1 << 2)
+
+#define BURTC_CTRL_MODE_SHIFT		(0)
+#define BURTC_CTRL_MODE_MASK		(0x3 << BURTC_CTRL_MODE_SHIFT)
+#define BURTC_CTRL_MODE(v)		\
+	(((v) << BURTC_CTRL_MODE_SHIFT) & BURTC_CTRL_MODE_MASK)
+#define BURTC_CTRL_MODE_DISABLE		0
+#define BURTC_CTRL_MODE_EM2EN		1
+#define BURTC_CTRL_MODE_EM3EN		2
+#define BURTC_CTRL_MODE_EM4EN		3
+
+/* BURTC_LPMODE */
+#define BURTC_LPMODE_LPMODE_SHIFT	(0)
+#define BURTC_LPMODE_LPMODE_MASK	(0x3 << BURTC_LPMODE_LPMODE_SHIFT)
+#define BURTC_LPMODE_LPMODE(v)		\
+	(((v) << BURTC_LPMODE_LPMODE_SHIFT) & BURTC_LPMODE_LPMODE_MASK)
+#define BURTC_LPMODE_LPMODE_DISABLE	0
+#define BURTC_LPMODE_LPMODE_ENABLE	1
+#define BURTC_LPMODE_LPMODE_BUEN	2
+
+/* BURTC_LFXOFDET */
+#define BURTC_LFXOFDET_TOP_SHIFT	(4)
+#define BURTC_LFXOFDET_TOP_MASK		(0xF << BURTC_LFXOFDET_TOP_SHIFT)
+#define BURTC_LFXOFDET_TOP(v)		\
+	(((v) << BURTC_LFXOFDET_TOP_SHIFT) & BURTC_LFXOFDET_TOP_MASK)
+
+#define BURTC_LFXOFDET_OSC_SHIFT	(0)
+#define BURTC_LFXOFDET_OSC_MASK		(0x3 << BURTC_LFXOFDET_OSC_SHIFT)
+#define BURTC_LFXOFDET_OSC(v)		\
+	(((v) << BURTC_LFXOFDET_OSC_SHIFT) & BURTC_LFXOFDET_OSC_MASK)
+#define BURTC_LFXOFDET_OSC_DISABLE	0
+#define BURTC_LFXOFDET_OSC_LFRCO	1
+#define BURTC_LFXOFDET_OSC_ULFRCO	2
+
+/* BURTC_STATUS */
+#define BURTC_STATUS_RAMWERR		(1 << 2)
+#define BURTC_STATUS_BUMODETS		(1 << 1)
+#define BURTC_STATUS_LPMODEACT		(1 << 0)
+
+/* BURTC_CMD */
+#define BURTC_CMD_CLRSTATUS		(1 << 0)
+
+/* BURTC_POWERDOWN */
+#define BURTC_POWERDOWN_RAM		(1 << 0)
+
+/* BURTC_LOCK */
+#define BURTC_LOCK_LOCKKEY_SHIFT	(0)
+#define BURTC_LOCK_LOCKKEY_MASK		(0xFFFF << BURTC_LOCK_LOCKKEY_SHIFT)
+#define BURTC_LOCK_LOCKKEY_UNLOCKED	(0x0000 << BURTC_LOCK_LOCKKEY_SHIFT)
+#define BURTC_LOCK_LOCKKEY_LOCKED	(0x0001 << BURTC_LOCK_LOCKKEY_SHIFT)
+#define BURTC_LOCK_LOCKKEY_LOCK		(0x0000 << BURTC_LOCK_LOCKKEY_SHIFT)
+#define BURTC_LOCK_LOCKKEY_UNLOCK	(0xAEE8 << BURTC_LOCK_LOCKKEY_SHIFT)
+
+/* BURTC_IF */
+#define BURTC_IF_LFXOFAIL		(1 << 2)
+#define BURTC_IF_COMP0			(1 << 1)
+#define BURTC_IF_OF			(1 << 0)
+
+/* BURTC_IFS */
+#define BURTC_IFS_LFXOFAIL		(1 << 2)
+#define BURTC_IFS_COMP0			(1 << 1)
+#define BURTC_IFS_OF			(1 << 0)
+
+/* BURTC_IFC */
+#define BURTC_IFC_LFXOFAIL		(1 << 2)
+#define BURTC_IFC_COMP0			(1 << 1)
+#define BURTC_IFC_OF			(1 << 0)
+
+/* BURTC_IEN */
+#define BURTC_IEN_LFXOFAIL		(1 << 2)
+#define BURTC_IEN_COMP0			(1 << 1)
+#define BURTC_IEN_OF			(1 << 0)
+
+/* BURTC_FREEZE */
+#define BURTC_FREEZE_REGFREEZE		(1 << 0)
+
+/* BURTC_SYNCBUSY */
+#define BURTC_SYNCBUSY_COMP0		(1 << 1)
+#define BURTC_SYNCBUSY_LPMODE		(1 << 0)
+
+/**@}*/
+

3rd/libopencm3/include/libopencm3/efm32/common/cmu_common.h

@@ -0,0 +1,707 @@
+/** @addtogroup cmu_defines
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+/**@{*/
+
+#include <libopencm3/efm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+#define CMU_CTRL		MMIO32(CMU_BASE + 0x000)
+#define CMU_HFCORECLKDIV	MMIO32(CMU_BASE + 0x004)
+#define CMU_HFPERCLKDIV		MMIO32(CMU_BASE + 0x008)
+#define CMU_HFRCOCTRL		MMIO32(CMU_BASE + 0x00C)
+#define CMU_LFRCOCTRL		MMIO32(CMU_BASE + 0x010)
+#define CMU_AUXHFRCOCTRL	MMIO32(CMU_BASE + 0x014)
+#define CMU_CALCTRL		MMIO32(CMU_BASE + 0x018)
+#define CMU_CALCNT		MMIO32(CMU_BASE + 0x01C)
+#define CMU_OSCENCMD		MMIO32(CMU_BASE + 0x020)
+#define CMU_CMD			MMIO32(CMU_BASE + 0x024)
+#define CMU_LFCLKSEL		MMIO32(CMU_BASE + 0x028)
+#define CMU_STATUS		MMIO32(CMU_BASE + 0x02C)
+#define CMU_IF			MMIO32(CMU_BASE + 0x030)
+#define CMU_IFS			MMIO32(CMU_BASE + 0x034)
+#define CMU_IFC			MMIO32(CMU_BASE + 0x038)
+#define CMU_IEN			MMIO32(CMU_BASE + 0x03C)
+#define CMU_HFCORECLKEN0	MMIO32(CMU_BASE + 0x040)
+#define CMU_HFPERCLKEN0		MMIO32(CMU_BASE + 0x044)
+#define CMU_SYNCBUSY		MMIO32(CMU_BASE + 0x050)
+#define CMU_FREEZE		MMIO32(CMU_BASE + 0x054)
+#define CMU_LFACLKEN0		MMIO32(CMU_BASE + 0x058)
+#define CMU_LFBCLKEN0		MMIO32(CMU_BASE + 0x060)
+#define CMU_LFAPRESC0		MMIO32(CMU_BASE + 0x068)
+#define CMU_LFBPRESC0		MMIO32(CMU_BASE + 0x070)
+#define CMU_PCNTCTRL		MMIO32(CMU_BASE + 0x078)
+#define CMU_LCDCTRL		MMIO32(CMU_BASE + 0x07C)
+#define CMU_ROUTE		MMIO32(CMU_BASE + 0x080)
+#define CMU_LOCK		MMIO32(CMU_BASE + 0x084)
+
+/* CMU_CTRL */
+#define CMU_CTRL_HFLE		(1 << 30)
+#define CMU_CTRL_DBGCLK		(1 << 28)
+
+
+#define CMU_CTRL_CLKOUTSEL1_SHIFT	(23)
+#define CMU_CTRL_CLKOUTSEL1_MASK	(0x7 << CMU_CTRL_CLKOUTSEL1_SHIFT)
+#define CMU_CTRL_CLKOUTSEL1(v)		\
+	(((v) << CMU_CTRL_CLKOUTSEL1_SHIFT) & CMU_CTRL_CLKOUTSEL1_MASK)
+#define CMU_CTRL_CLKOUTSEL1_LFRCO	0
+#define CMU_CTRL_CLKOUTSEL1_LFXO	1
+#define CMU_CTRL_CLKOUTSEL1_HFCLK	2
+#define CMU_CTRL_CLKOUTSEL1_LFXOQ	3
+#define CMU_CTRL_CLKOUTSEL1_HFXOQ	4
+#define CMU_CTRL_CLKOUTSEL1_LFRCOQ	5
+#define CMU_CTRL_CLKOUTSEL1_HFRCOQ	6
+#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ	7
+
+#define CMU_CTRL_CLKOUTSEL0_SHIFT	(23)
+#define CMU_CTRL_CLKOUTSEL0_MASK	(0x7 << CMU_CTRL_CLKOUTSEL0_SHIFT)
+#define CMU_CTRL_CLKOUTSEL0(v)		\
+	(((v) << CMU_CTRL_CLKOUTSEL0_SHIFT) & CMU_CTRL_CLKOUTSEL0_MASK)
+#define CMU_CTRL_CLKOUTSEL0_HFRCO	0
+#define CMU_CTRL_CLKOUTSEL0_HFXO	1
+#define CMU_CTRL_CLKOUTSEL0_HFCLK2	2
+#define CMU_CTRL_CLKOUTSEL0_HFCLK4	3
+#define CMU_CTRL_CLKOUTSEL0_HFCLK8	4
+#define CMU_CTRL_CLKOUTSEL0_HFCLK16	5
+#define CMU_CTRL_CLKOUTSEL0_ULFRCO	6
+#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO	7
+
+#define CMU_CTRL_LFXOTIMEOUT_SHIFT	(18)
+#define CMU_CTRL_LFXOTIMEOUT_MASK	(0x3 << CMU_CTRL_LFXOTIMEOUT_SHIFT)
+#define CMU_CTRL_LFXOTIMEOUT(v)		\
+	(((v) << CMU_CTRL_LFXOTIMEOUT_SHIFT) & CMU_CTRL_LFXOTIMEOUT_MASK)
+#define CMU_CTRL_LFXOTIMEOUT_8CYCLES	0
+#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES	1
+#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES	2
+#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES	3
+
+#define CMU_CTRL_LFXOBUFCUR		(1 << 17)
+
+#define CMU_CTRL_HFCLKDIV_SHIFT		(14)
+#define CMU_CTRL_HFCLKDIV_MASK		(0x7 << CMU_CTRL_HFCLKDIV_SHIFT)
+#define CMU_CTRL_HFCLKDIV(v)		\
+	(((v) << CMU_CTRL_HFCLKDIV_SHIFT) & CMU_CTRL_HFCLKDIV_MASK)
+#define CMU_CTRL_HFCLKDIV_NODIV		0
+#define CMU_CTRL_HFCLKDIV_DIV2		1
+#define CMU_CTRL_HFCLKDIV_DIV3		2
+#define CMU_CTRL_HFCLKDIV_DIV4		3
+#define CMU_CTRL_HFCLKDIV_DIV5		4
+#define CMU_CTRL_HFCLKDIV_DIV6		5
+#define CMU_CTRL_HFCLKDIV_DIV7		6
+#define CMU_CTRL_HFCLKDIV_DIV8		7
+
+#define CMU_CTRL_LFXOBOOST		(1 << 13)
+
+#define CMU_CTRL_LFXOMODE_SHIFT		(11)
+#define CMU_CTRL_LFXOMODE_MASK		(0x3 << CMU_CTRL_LFXOMODE_SHIFT)
+#define CMU_CTRL_LFXOMODE(v)		\
+	(((v) << CMU_CTRL_LFXOMODE_SHIFT) & CMU_CTRL_LFXOMODE_MASK)
+#define CMU_CTRL_LFXOMODE_XTAL		0
+#define CMU_CTRL_LFXOMODE_BUFEXTCLK	1
+#define CMU_CTRL_LFXOMODE_DIGEXTCLK	2
+
+#define CMU_CTRL_HFXOTIMEOUT_SHIFT	(9)
+#define CMU_CTRL_HFXOTIMEOUT_MASK	(0x3 << CMU_CTRL_HFXOTIMEOUT_SHIFT)
+#define CMU_CTRL_HFXOTIMEOUT(v)		\
+	(((v) << CMU_CTRL_HFXOTIMEOUT_SHIFT) & CMU_CTRL_HFXOTIMEOUT_MASK)
+#define CMU_CTRL_HFXOTIMEOUT_8CYCLES	0
+#define CMU_CTRL_HFXOTIMEOUT_256CYCLES	1
+#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES	2
+#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES	3
+
+#define CMU_CTRL_HFXOGLITCHDETEN	(1 << 7)
+
+#define CMU_CTRL_HFXOBUFCUR_SHIFT	(5)
+#define CMU_CTRL_HFXOBUFCUR_MASK	(0x3 << CMU_CTRL_HFXOBUFCUR_SHIFT)
+#define CMU_CTRL_HFXOBUFCUR(v)		\
+	(((v) << CMU_CTRL_HFXOBUFCUR_SHIFT) & CMU_CTRL_HFXOBUFCUR_MASK)
+#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ	1
+#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ	3
+
+#define CMU_CTRL_HFXOBOOST_SHIFT	(2)
+#define CMU_CTRL_HFXOBOOST_MASK		(0x3 << CMU_CTRL_HFXOBOOST_SHIFT)
+#define CMU_CTRL_HFXOBOOST(v)		\
+	(((v) << CMU_CTRL_HFXOBOOST_SHIFT) & CMU_CTRL_HFXOBOOST_MASK)
+#define CMU_CTRL_HFXOBOOST_50PCENT	0
+#define CMU_CTRL_HFXOBOOST_70PCENT	1
+#define CMU_CTRL_HFXOBOOST_80PCENT	2
+#define CMU_CTRL_HFXOBOOST_100PCENT	3
+
+#define CMU_CTRL_HFXOMODE_SHIFT		(0)
+#define CMU_CTRL_HFXOMODE_MASK		(0x3 << CMU_CTRL_HFXOMODE_SHIFT)
+#define CMU_CTRL_HFXOMODE(v)		\
+	(((v) << CMU_CTRL_HFXOMODE_SHIFT) & CMU_CTRL_HFXOMODE_MASK)
+#define CMU_CTRL_HFXOMODE_XTAL		0
+#define CMU_CTRL_HFXOMODE_BUFEXTCLK	1
+#define CMU_CTRL_HFXOMODE_DIGEXTCLK	2
+
+/* CMU_HFCORECLKDIV */
+#define CMU_HFCORECLKDIV_HFCORECLKLEDIV		(1 << 8)
+
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT	(0)
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_MASK	\
+	(0xF << CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT)
+#define CMU_HFCORECLKDIV_HFCORECLKDIV(v)	\
+	(((v) << CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT) & \
+	CMU_HFCORECLKDIV_HFCORECLKDIV_MASK)
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK	\
+	CMU_HFCORECLKDIV_HFCORECLKDIV(0)
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2	\
+	CMU_HFCORECLKDIV_HFCORECLKDIV(1)
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4	\
+	CMU_HFCORECLKDIV_HFCORECLKDIV(2)
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8	\
+	CMU_HFCORECLKDIV_HFCORECLKDIV(3)
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16	\
+	CMU_HFCORECLKDIV_HFCORECLKDIV(4)
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32	\
+	CMU_HFCORECLKDIV_HFCORECLKDIV(5)
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64	\
+	CMU_HFCORECLKDIV_HFCORECLKDIV(6)
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128	\
+	CMU_HFCORECLKDIV_HFCORECLKDIV(7)
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256	\
+	CMU_HFCORECLKDIV_HFCORECLKDIV(8)
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512	\
+	CMU_HFCORECLKDIV_HFCORECLKDIV(9)
+
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_NODIV	\
+	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV2	\
+	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV4	\
+	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV8	\
+	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV16	\
+	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV32	\
+	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV64	\
+	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV128	\
+	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV256	\
+	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV512	\
+	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512
+
+/* CMU_HFPERCLKDIV */
+#define CMU_HFPERCLKDIV_HFPERCLKEN (1 << 8)
+
+#define CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT	(0)
+#define CMU_HFPERCLKDIV_HFPERCLKDIV_MASK	\
+	(0xF << CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT)
+#define CMU_HFPERCLKDIV_HFPERCLKDIV(v)		\
+	(((v) << CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT) & \
+	 CMU_HFPERCLKDIV_HFPERCLKDIV_MASK)
+#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK	CMU_HFPERCLKDIV_HFPERCLKDIV(0)
+#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK2	CMU_HFPERCLKDIV_HFPERCLKDIV(1)
+#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK4	CMU_HFPERCLKDIV_HFPERCLKDIV(2)
+#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK8	CMU_HFPERCLKDIV_HFPERCLKDIV(3)
+#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK16	CMU_HFPERCLKDIV_HFPERCLKDIV(4)
+#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK32	CMU_HFPERCLKDIV_HFPERCLKDIV(5)
+#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK64	CMU_HFPERCLKDIV_HFPERCLKDIV(6)
+#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK128	CMU_HFPERCLKDIV_HFPERCLKDIV(7)
+#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK256	CMU_HFPERCLKDIV_HFPERCLKDIV(8)
+#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK512	CMU_HFPERCLKDIV_HFPERCLKDIV(9)
+
+/* CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK* to CMU_HFPERCLKDIV_HFPERCLKHFCLK_DIV* */
+#define CMU_HFPERCLKDIV_HFPERCLKDIV_NODIV	\
+	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK
+#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV2	\
+	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2
+#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV4	\
+	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4
+#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV8	\
+	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8
+#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV16	\
+	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16
+#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV32	\
+	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32
+#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV64	\
+	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64
+#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV128	\
+	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128
+#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV256	\
+	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256
+#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV512	\
+	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512
+
+/* CMU_HFRCOCTRL */
+#define CMU_HFRCOCTRL_SUDELAY_SHIFT	(12)
+#define CMU_HFRCOCTRL_SUDELAY_MASK	(0x1F << CMU_HFRCOCTRL_SUDELAY_SHIFT)
+#define CMU_HFRCOCTRL_SUDELAY(v)	\
+	((((v) << CMU_HFRCOCTRL_SUDELAY_SHIFT) & CMU_HFRCOCTRL_SUDELAY_MASK))
+
+#define CMU_HFRCOCTRL_BAND_SHIFT	(8)
+#define CMU_HFRCOCTRL_BAND_MASK		(0x7 << CMU_HFRCOCTRL_BAND_SHIFT)
+#define CMU_HFRCOCTRL_BAND(v)		\
+	(((v) << CMU_HFRCOCTRL_BAND_SHIFT) & CMU_HFRCOCTRL_BAND_MASK)
+#define CMU_HFRCOCTRL_BAND_1MHZ		0
+#define CMU_HFRCOCTRL_BAND_7MHZ		1
+#define CMU_HFRCOCTRL_BAND_11MHZ	2
+#define CMU_HFRCOCTRL_BAND_14MHZ	3
+#define CMU_HFRCOCTRL_BAND_21MHZ	4
+#define CMU_HFRCOCTRL_BAND_28MHZ	5
+
+#define CMU_HFRCOCTRL_TUNING_SHIFT	(0)
+#define CMU_HFRCOCTRL_TUNING_MASK	(0xFF << CMU_HFRCOCTRL_TUNING_SHIFT)
+#define CMU_HFRCOCTRL_TUNING(v)		\
+	(((v) << CMU_HFRCOCTRL_TUNING_SHIFT) & CMU_HFRCOCTRL_TUNING_MASK)
+
+/* CMU_LFRCOCTRL */
+#define CMU_LFRCOCTRL_TUNING_SHIFT	(0)
+#define CMU_LFRCOCTRL_TUNING_MASK	(0xFF << CMU_LFRCOCTRL_TUNING_SHIFT)
+#define CMU_LFRCOCTRL_TUNING(v)			\
+	(((v) << CMU_LFRCOCTRL_TUNING_SHIFT) & CMU_LFRCOCTRL_TUNING_MASK)
+
+/* CMU_AUXHFRCOCTRL */
+#define CMU_AUXHFRCOCTRL_BAND_SHIFT	(8)
+#define CMU_AUXHFRCOCTRL_BAND_MASK	(0x7 << CMU_AUXHFRCOCTRL_BAND_SHIFT)
+#define CMU_AUXHFRCOCTRL_BAND(v)	\
+	(((v) << CMU_AUXHFRCOCTRL_BAND_SHIFT) & CMU_AUXHFRCOCTRL_BAND_MASK)
+#define CMU_AUXHFRCOCTRL_BAND_1MHZ	0
+#define CMU_AUXHFRCOCTRL_BAND_7MHZ	1
+#define CMU_AUXHFRCOCTRL_BAND_11MHZ	2
+#define CMU_AUXHFRCOCTRL_BAND_14MHZ	3
+#define CMU_AUXHFRCOCTRL_BAND_28MHZ	4
+#define CMU_AUXHFRCOCTRL_BAND_21MHZ	5
+
+#define CMU_AUXHFRCOCTRL_TUNING_SHIFT	(0)
+#define CMU_AUXHFRCOCTRL_TUNING_MASK	(0xFF << CMU_AUXHFRCOCTRL_TUNING_SHIFT)
+#define CMU_AUXHFRCOCTRL_TUNING(v)	\
+	(((v) << CMU_AUXHFRCOCTRL_TUNING_SHIFT) & CMU_AUXHFRCOCTRL_TUNING_MASK)
+
+/* CMU_CALCTRL */
+#define CMU_CALCTRL_CONT		(1 << 6)
+
+#define CMU_CALCTRL_DOWNSEL_SHIFT	(3)
+#define CMU_CALCTRL_DOWNSEL_MASK	(0x7 << CMU_CALCTRL_DOWNSEL_SHIFT)
+#define CMU_CALCTRL_DOWNSEL(v)		\
+	(((v) << CMU_CALCTRL_DOWNSEL_SHIFT) & CMU_CALCTRL_DOWNSEL_MASK)
+#define CMU_CALCTRL_DOWNSEL_HFCLK	0
+#define CMU_CALCTRL_DOWNSEL_HFXO	1
+#define CMU_CALCTRL_DOWNSEL_LFXO	2
+#define CMU_CALCTRL_DOWNSEL_HFRCO	3
+#define CMU_CALCTRL_DOWNSEL_LFRCO	4
+#define CMU_CALCTRL_DOWNSEL_AUXHFRCO	5
+
+#define CMU_CALCTRL_UPSEL_SHIFT		(3)
+#define CMU_CALCTRL_UPSEL_MASK		(0x7 << CMU_CALCTRL_UPSEL_SHIFT)
+#define CMU_CALCTRL_UPSEL(v)		\
+	(((v) << CMU_CALCTRL_UPSEL_SHIFT) & CMU_CALCTRL_UPSEL_MASK)
+#define CMU_CALCTRL_UPSEL_HFXO		0
+#define CMU_CALCTRL_UPSEL_LFXO		1
+#define CMU_CALCTRL_UPSEL_HFRCO		2
+#define CMU_CALCTRL_UPSEL_LFRCO		3
+#define CMU_CALCTRL_UPSEL_AUXHFRCO	4
+
+/* CMU_CALCNT */
+#define CMU_CALCNT_CALCNT_SHIFT		(0)
+#define CMU_CALCNT_CALCNT_MASK		(0xFFFFF << CMU_CALCNT_CALCNT_SHIFT)
+#define CMU_CALCNT_CALCNT(v)		\
+	(((v) << CMU_CALCNT_CALCNT_SHIFT) & CMU_CALCNT_CALCNT_MASK)
+
+/* CMU_OSCENCMD */
+#define CMU_OSCENCMD_LFXODIS		(1 << 9)
+#define CMU_OSCENCMD_LFXOEN		(1 << 8)
+#define CMU_OSCENCMD_LFRCODIS		(1 << 7)
+#define CMU_OSCENCMD_LFRCOEN		(1 << 6)
+#define CMU_OSCENCMD_AUXHFRCODIS	(1 << 5)
+#define CMU_OSCENCMD_AUXHFRCOEN		(1 << 4)
+#define CMU_OSCENCMD_HFXODIS		(1 << 3)
+#define CMU_OSCENCMD_HFXOEN		(1 << 2)
+#define CMU_OSCENCMD_HFRCODIS		(1 << 1)
+#define CMU_OSCENCMD_HFRCOEN		(1 << 0)
+
+/* CMU_CMD */
+#define CMU_CMD_USBCCLKSEL_SHIFT	(5)
+#define CMU_CMD_USBCCLKSEL_MASK		(0x3 << CMU_CMD_USBCCLKSEL_SHIFT)
+#define CMU_CMD_USBCCLKSEL(v)		\
+	(((v) << CMU_CMD_USBCCLKSEL_SHIFT) & CMU_CMD_USBCCLKSEL_MASK)
+#define CMU_CMD_USBCCLKSEL_HFCLKNODIV	1
+#define CMU_CMD_USBCCLKSEL_LFXO		2
+#define CMU_CMD_USBCCLKSEL_LFRCO	3
+
+#define CMU_CMD_CALSTOP		(1 << 4)
+#define CMU_CMD_CALSTART	(1 << 3)
+
+#define CMU_CMD_HFCLKSEL_SHIFT	(0)
+#define CMU_CMD_HFCLKSEL_MASK	(0x7 << CMU_CMD_HFCLKSEL_SHIFT)
+#define CMU_CMD_HFCLKSEL(v)	\
+	(((v) << CMU_CMD_HFCLKSEL_SHIFT) & CMU_CMD_HFCLKSEL_MASK)
+#define CMU_CMD_HFCLKSEL_HFRCO	1
+#define CMU_CMD_HFCLKSEL_HFXO	2
+#define CMU_CMD_HFCLKSEL_LFRCO	3
+#define CMU_CMD_HFCLKSEL_LFXO	4
+
+/* CMU_LFCLKSEL */
+#define CMU_LFCLKSEL_LFBE (1 << 20)
+#define CMU_LFCLKSEL_LFAE (1 << 16)
+
+#define CMU_LFCLKSEL_LFB_SHIFT	(2)
+#define CMU_LFCLKSEL_LFB_MASK	(0x3 << CMU_LFCLKSEL_LFB_MASK)
+#define CMU_LFCLKSEL_LFB(v)	\
+	(((v) << CMU_LFCLKSEL_LFB_MASK) & CMU_LFCLKSEL_LFB_MASK)
+
+#define CMU_LFCLKSEL_LFA_SHIFT	(0)
+#define CMU_LFCLKSEL_LFA_MASK	(0x3 << CMU_LFCLKSEL_LFA_MASK)
+#define CMU_LFCLKSEL_LFA(v)	\
+	(((v) << CMU_LFCLKSEL_LFA_MASK) & CMU_LFCLKSEL_LFA_MASK)
+
+/* CMU_STATUS */
+#define CMU_STATUS_USBCLFRCOSEL	(1 << 17)
+#define CMU_STATUS_USBCLFXOSEL	(1 << 16)
+#define CMU_STATUS_USBCHFCLKSEL	(1 << 15)
+#define CMU_STATUS_CALBSY	(1 << 14)
+#define CMU_STATUS_LFXOSEL	(1 << 13)
+#define CMU_STATUS_LFRCOSEL	(1 << 12)
+#define CMU_STATUS_HFXOSEL	(1 << 11)
+#define CMU_STATUS_HFRCOSEL	(1 << 10)
+#define CMU_STATUS_LFXORDY	(1 << 9)
+#define CMU_STATUS_LFXOENS	(1 << 8)
+#define CMU_STATUS_LFRCORDY	(1 << 7)
+#define CMU_STATUS_LFRCOENS	(1 << 6)
+#define CMU_STATUS_AUXHFRCORDY	(1 << 5)
+#define CMU_STATUS_AUXHFRCOENS	(1 << 4)
+#define CMU_STATUS_HFXORDY	(1 << 3)
+#define CMU_STATUS_HFXOENS	(1 << 2)
+#define CMU_STATUS_HFRCORDY	(1 << 1)
+#define CMU_STATUS_HFRCOENS	(1 << 0)
+
+/* CMU_IF */
+#define CMU_IF_USBCHFCLKSEL	(1 << 7)
+#define CMU_IF_CALOF		(1 << 6)
+#define CMU_IF_CALRDY		(1 << 5)
+#define CMU_IF_AUXHFRCORDY	(1 << 4)
+#define CMU_IF_LFXORDY		(1 << 3)
+#define CMU_IF_LFRCORDY		(1 << 2)
+#define CMU_IF_HFXORDY		(1 << 1)
+#define CMU_IF_HFRCORDY		(1 << 0)
+
+/* CMU_IFS */
+#define CMU_IFS_USBCHFCLKSEL	(1 << 7)
+#define CMU_IFS_CALOF		(1 << 6)
+#define CMU_IFS_CALRDY		(1 << 5)
+#define CMU_IFS_AUXHFRCORDY	(1 << 4)
+#define CMU_IFS_LFXORDY		(1 << 3)
+#define CMU_IFS_LFRCORDY	(1 << 2)
+#define CMU_IFS_HFXORDY		(1 << 1)
+#define CMU_IFS_HFRCORDY	(1 << 0)
+
+/* CMU_IFC */
+#define CMU_IFC_USBCHFCLKSEL	(1 << 7)
+#define CMU_IFC_CALOF		(1 << 6)
+#define CMU_IFC_CALRDY		(1 << 5)
+#define CMU_IFC_AUXHFRCORDY	(1 << 4)
+#define CMU_IFC_LFXORDY		(1 << 3)
+#define CMU_IFC_LFRCORDY	(1 << 2)
+#define CMU_IFC_HFXORDY		(1 << 1)
+#define CMU_IFC_HFRCORDY	(1 << 0)
+
+/* CMU_IEN */
+#define CMU_IEN_USBCHFCLKSEL	(1 << 7)
+#define CMU_IEN_CALOF		(1 << 6)
+#define CMU_IEN_CALRDY		(1 << 5)
+#define CMU_IEN_AUXHFRCORDY	(1 << 4)
+#define CMU_IEN_LFXORDY		(1 << 3)
+#define CMU_IEN_LFRCORDY	(1 << 2)
+#define CMU_IEN_HFXORDY		(1 << 1)
+#define CMU_IEN_HFRCORDY	(1 << 0)
+
+/* CMU_HFCORECLKEN0 */
+#define CMU_HFCORECLKEN0_EBI	(1 << 5)
+#define CMU_HFCORECLKEN0_LE	(1 << 4)
+#define CMU_HFCORECLKEN0_USB	(1 << 3)
+#define CMU_HFCORECLKEN0_USBC	(1 << 2)
+#define CMU_HFCORECLKEN0_AES	(1 << 1)
+#define CMU_HFCORECLKEN0_DMA	(1 << 0)
+
+/* CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_DAC0	(1 << 17)
+#define CMU_HFPERCLKEN0_ADC0	(1 << 16)
+#define CMU_HFPERCLKEN0_PRS	(1 << 15)
+#define CMU_HFPERCLKEN0_VCMP	(1 << 14)
+#define CMU_HFPERCLKEN0_GPIO	(1 << 13)
+#define CMU_HFPERCLKEN0_I2C1	(1 << 12)
+#define CMU_HFPERCLKEN0_I2C0	(1 << 11)
+#define CMU_HFPERCLKEN0_ACMP1	(1 << 10)
+#define CMU_HFPERCLKEN0_ACMP0	(1 << 9)
+#define CMU_HFPERCLKEN0_TIMER3	(1 << 8)
+#define CMU_HFPERCLKEN0_TIMER2	(1 << 7)
+#define CMU_HFPERCLKEN0_TIMER1	(1 << 6)
+#define CMU_HFPERCLKEN0_TIMER0	(1 << 5)
+#define CMU_HFPERCLKEN0_UART1	(1 << 4)
+#define CMU_HFPERCLKEN0_UART0	(1 << 3)
+#define CMU_HFPERCLKEN0_USART2	(1 << 2)
+#define CMU_HFPERCLKEN0_USART1	(1 << 1)
+#define CMU_HFPERCLKEN0_USART0	(1 << 0)
+
+/* CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFBPRESC0	(1 << 6)
+#define CMU_SYNCBUSY_LFBCLKEN0	(1 << 4)
+#define CMU_SYNCBUSY_LFAPRESC0	(1 << 2)
+#define CMU_SYNCBUSY_LFACLKEN0	(1 << 0)
+
+/* CMU_FREEZE */
+#define CMU_FREEZE_REGFREEZE	(1 << 0)
+
+/* CMU_LFACLKEN0 */
+#define CMU_LFACLKEN0_LCD	(1 << 3)
+#define CMU_LFACLKEN0_LETIMER0	(1 << 2)
+#define CMU_LFACLKEN0_RTC	(1 << 1)
+#define CMU_LFACLKEN0_LESENSE	(1 << 0)
+
+/* CMU_LFBCLKEN0 */
+#define CMU_LFBCLKEN0_LEUART1	(1 << 1)
+#define CMU_LFBCLKEN0_LEUART0	(1 << 0)
+
+/* CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LCD_SHIFT		(12)
+#define CMU_LFAPRESC0_LCD_MASK		(0x3 << CMU_LFAPRESC0_LCD_SHIFT)
+#define CMU_LFAPRESC0_LCD(v)		\
+	(((v) << CMU_LFAPRESC0_LCD_SHIFT) & CMU_LFAPRESC0_LCD_MASK)
+#define CMU_LFAPRESC0_LCD_DIV16		0
+#define CMU_LFAPRESC0_LCD_DIV32		1
+#define CMU_LFAPRESC0_LCD_DIV64		2
+#define CMU_LFAPRESC0_LCD_DIV128	3
+
+#define CMU_LFAPRESC0_LETIMER0_SHIFT	(8)
+#define CMU_LFAPRESC0_LETIMER0_MASK	(0xF << CMU_LFAPRESC0_LETIMER0_SHIFT)
+#define CMU_LFAPRESC0_LETIMER0(v)	\
+	(((v) << CMU_LFAPRESC0_LETIMER0_SHIFT) & CMU_LFAPRESC0_LETIMER0_MASK)
+#define CMU_LFAPRESC0_LETIMER0_DIV1	0
+#define CMU_LFAPRESC0_LETIMER0_DIV2	1
+#define CMU_LFAPRESC0_LETIMER0_DIV4	2
+#define CMU_LFAPRESC0_LETIMER0_DIV8	3
+#define CMU_LFAPRESC0_LETIMER0_DIV16	4
+#define CMU_LFAPRESC0_LETIMER0_DIV32	5
+#define CMU_LFAPRESC0_LETIMER0_DIV64	6
+#define CMU_LFAPRESC0_LETIMER0_DIV128	7
+#define CMU_LFAPRESC0_LETIMER0_DIV256	8
+#define CMU_LFAPRESC0_LETIMER0_DIV512	9
+#define CMU_LFAPRESC0_LETIMER0_DIV1024	10
+#define CMU_LFAPRESC0_LETIMER0_DIV2048	11
+#define CMU_LFAPRESC0_LETIMER0_DIV4096	12
+#define CMU_LFAPRESC0_LETIMER0_DIV8192	13
+#define CMU_LFAPRESC0_LETIMER0_DIV16384	14
+#define CMU_LFAPRESC0_LETIMER0_DIV32768	15
+#define CMU_LFAPRESC0_LETIMER0_NODIV	CMU_LFAPRESC0_LETIMER0_DIV1
+
+#define CMU_LFAPRESC0_RTC_SHIFT		(4)
+#define CMU_LFAPRESC0_RTC_MASK		(0xF << CMU_LFAPRESC0_RTC_SHIFT)
+#define CMU_LFAPRESC0_RTC(v)		\
+	(((v) << CMU_LFAPRESC0_RTC_SHIFT) & CMU_LFAPRESC0_RTC_MASK)
+#define CMU_LFAPRESC0_RTC_DIV1		0
+#define CMU_LFAPRESC0_RTC_DIV2		1
+#define CMU_LFAPRESC0_RTC_DIV4		2
+#define CMU_LFAPRESC0_RTC_DIV8		3
+#define CMU_LFAPRESC0_RTC_DIV16		4
+#define CMU_LFAPRESC0_RTC_DIV32		5
+#define CMU_LFAPRESC0_RTC_DIV64		6
+#define CMU_LFAPRESC0_RTC_DIV128	7
+#define CMU_LFAPRESC0_RTC_DIV256	8
+#define CMU_LFAPRESC0_RTC_DIV512	9
+#define CMU_LFAPRESC0_RTC_DIV1024	10
+#define CMU_LFAPRESC0_RTC_DIV2048	11
+#define CMU_LFAPRESC0_RTC_DIV4096	12
+#define CMU_LFAPRESC0_RTC_DIV8192	13
+#define CMU_LFAPRESC0_RTC_DIV16384	14
+#define CMU_LFAPRESC0_RTC_DIV32768	15
+#define CMU_LFAPRESC0_RTC_NODIV		CMU_LFAPRESC0_RTC_DIV1
+
+#define CMU_LFAPRESC0_LESENSE_SHIFT	(12)
+#define CMU_LFAPRESC0_LESENSE_MASK	(0x3 << CMU_LFAPRESC0_LESENSE_SHIFT)
+#define CMU_LFAPRESC0_LESENSE(v)	\
+	(((v) << CMU_LFAPRESC0_LESENSE_SHIFT) & CMU_LFAPRESC0_LESENSE_MASK)
+#define CMU_LFAPRESC0_LESENSE_DIV1	0
+#define CMU_LFAPRESC0_LESENSE_DIV2	1
+#define CMU_LFAPRESC0_LESENSE_DIV4	2
+#define CMU_LFAPRESC0_LESENSE_DIV8	3
+#define CMU_LFAPRESC0_LESENSE_NODIV	CMU_LFAPRESC0_LESENSE_DIV1
+
+/* CMU_LFBPRESC0 */
+#define CMU_LFBPRESC0_LEUART1_SHIFT	(4)
+#define CMU_LFBPRESC0_LEUART1_MASK	(0x3 << CMU_LFBPRESC0_LEUART1_SHIFT)
+#define CMU_LFBPRESC0_LEUART1(v)	\
+	(((v) << CMU_LFBPRESC0_LEUART1_SHIFT) & CMU_LFBPRESC0_LEUART1_MASK)
+#define CMU_LFBPRESC0_LEUART1_DIV1	0
+#define CMU_LFBPRESC0_LEUART1_DIV2	1
+#define CMU_LFBPRESC0_LEUART1_DIV4	2
+#define CMU_LFBPRESC0_LEUART1_DIV8	3
+#define CMU_LFBPRESC0_LEUART1_NODIV	CMU_LFBPRESC0_LEUART1_DIV1
+
+#define CMU_LFBPRESC0_LEUART0_SHIFT	(0)
+#define CMU_LFBPRESC0_LEUART0_MASK	(0x3 << CMU_LFBPRESC0_LEUART0_SHIFT)
+#define CMU_LFBPRESC0_LEUART0(v)	\
+	(((v) << CMU_LFBPRESC0_LEUART0_SHIFT) & CMU_LFBPRESC0_LEUART0_MASK)
+#define CMU_LFBPRESC0_LEUART0_DIV1	0
+#define CMU_LFBPRESC0_LEUART0_DIV2	1
+#define CMU_LFBPRESC0_LEUART0_DIV4	2
+#define CMU_LFBPRESC0_LEUART0_DIV8	3
+#define CMU_LFBPRESC0_LEUART0_NODIV	CMU_LFBPRESC0_LEUART0_DIV1
+
+/* CMU_PCNTCTRL */
+#define CMU_PCNTCTRL_PCNT2CLKSE		(1 << 5)
+#define CMU_PCNTCTRL_PCNT2CLKEN		(1 << 4)
+#define CMU_PCNTCTRL_PCNT1CLKSEL	(1 << 3)
+#define CMU_PCNTCTRL_PCNT1CLKEN		(1 << 2)
+#define CMU_PCNTCTRL_PCNT0CLKSEL	(1 << 1)
+#define CMU_PCNTCTRL_PCNT0CLKEN		(1 << 0)
+
+/* CMU_LCDCTRL */
+#define CMU_LCDCTRL_VBFDIV_SHIFT	(4)
+#define CMU_LCDCTRL_VBFDIV_MASK		(0xF << CMU_LCDCTRL_VBFDIV_SHIFT)
+#define CMU_LCDCTRL_VBFDIV(v)		\
+	(((v) << CMU_LCDCTRL_VBFDIV_SHIFT) & CMU_LCDCTRL_VBFDIV_MASK)
+#define CMU_LCDCTRL_VBFDIV_DIV1		0
+#define CMU_LCDCTRL_VBFDIV_DIV2		1
+#define CMU_LCDCTRL_VBFDIV_DIV4		2
+#define CMU_LCDCTRL_VBFDIV_DIV8		3
+#define CMU_LCDCTRL_VBFDIV_DIV16	4
+#define CMU_LCDCTRL_VBFDIV_DIV32	5
+#define CMU_LCDCTRL_VBFDIV_DIV64	6
+#define CMU_LCDCTRL_VBFDIV_DIV128	7
+#define CMU_LCDCTRL_VBFDIV_NODIV	CMU_LCDCTRL_VBFDIV_DIV1
+
+#define CMU_LCDCTRL_VBOOSTEN		(1 << 3)
+
+#define CMU_LCDCTRL_FDIV_SHIFT		(0)
+#define CMU_LCDCTRL_FDIV_MASK		(0x3 << CMU_LCDCTRL_FDIV_SHIFT)
+#define CMU_LCDCTRL_FDIV(v)		\
+	(((v) & CMU_LCDCTRL_FDIV_MASK) << CMU_LCDCTRL_FDIV_SHIFT)
+
+/* CMU_ROUTE */
+#define CMU_ROUTE_LOCATION_SHIFT	(2)
+#define CMU_ROUTE_LOCATION_MASK		(0x7 << CMU_ROUTE_LOCATION_SHIFT)
+#define CMU_ROUTE_LOCATION_LOCx(i)	\
+	(((i) << CMU_ROUTE_LOCATION_SHIFT) & CMU_ROUTE_LOCATION_MASK)
+#define CMU_ROUTE_LOCATION_LOC0		0
+#define CMU_ROUTE_LOCATION_LOC1		1
+#define CMU_ROUTE_LOCATION_LOC2		2
+
+#define CMU_ROUTE_CLKOUT1PEN		(1 << 1)
+#define CMU_ROUTE_CLKOUT0PEN		(1 << 0)
+
+/* CMU_LOCK */
+#define CMU_LOCK_LOCKKEY_SHIFT		(0)
+#define CMU_LOCK_LOCKKEY_MASK		(0xFFFF << CMU_LOCK_LOCKKEY_SHIFT)
+#define CMU_LOCK_LOCKKEY_UNLOCKED	(0x0000 << CMU_LOCK_LOCKKEY_SHIFT)
+#define CMU_LOCK_LOCKKEY_LOCKED		(0x0001 << CMU_LOCK_LOCKKEY_SHIFT)
+#define CMU_LOCK_LOCKKEY_LOCK		(0x0000 << CMU_LOCK_LOCKKEY_SHIFT)
+#define CMU_LOCK_LOCKKEY_UNLOCK		(0x580E << CMU_LOCK_LOCKKEY_SHIFT)
+
+#define _REG_BIT(base, bit)		(((base) << 5) + (bit))
+
+enum cmu_periph_clken {
+	/* CMU_PCNTCTRL */
+	CMU_PCNT2 = _REG_BIT(0x078, 4),
+	CMU_PCNT1 = _REG_BIT(0x078, 2),
+	CMU_PCNT0 = _REG_BIT(0x078, 0),
+
+	/* CMU_LFBCLKEN0 */
+	CMU_LEUART1 = _REG_BIT(0x060, 1),
+	CMU_LEUART0 = _REG_BIT(0x060, 0),
+
+	/* CMU_LFACLKEN0 */
+	CMU_LCD		= _REG_BIT(0x058, 3),
+	CMU_LETIMER0	= _REG_BIT(0x058, 2),
+	CMU_RTC		= _REG_BIT(0x058, 1),
+	CMU_LESENSE	= _REG_BIT(0x058, 0),
+
+	/* CMU_HFPERCLKEN0 */
+	CMU_DAC0	= _REG_BIT(0x044, 17),
+	CMU_ADC0	= _REG_BIT(0x044, 16),
+	CMU_PRS		= _REG_BIT(0x044, 15),
+	CMU_VCMP	= _REG_BIT(0x044, 14),
+	CMU_GPIO	= _REG_BIT(0x044, 13),
+	CMU_I2C1	= _REG_BIT(0x044, 12),
+	CMU_I2C0	= _REG_BIT(0x044, 11),
+	CMU_ACMP1	= _REG_BIT(0x044, 10),
+	CMU_ACMP0	= _REG_BIT(0x044, 9),
+	CMU_TIMER3	= _REG_BIT(0x044, 8),
+	CMU_TIMER2	= _REG_BIT(0x044, 7),
+	CMU_TIMER1	= _REG_BIT(0x044, 6),
+	CMU_TIMER0	= _REG_BIT(0x044, 5),
+	CMU_UART1	= _REG_BIT(0x044, 4),
+	CMU_UART0	= _REG_BIT(0x044, 3),
+	CMU_USART2	= _REG_BIT(0x044, 2),
+	CMU_USART1	= _REG_BIT(0x044, 1),
+	CMU_USART0	= _REG_BIT(0x044, 0),
+
+	/* CMU_HFCORECLKEN0 */
+	CMU_EBI		= _REG_BIT(0x040, 5),
+	CMU_LE		= _REG_BIT(0x040, 4),
+	CMU_USB		= _REG_BIT(0x040, 3),
+	CMU_USBC	= _REG_BIT(0x040, 2),
+	CMU_AES		= _REG_BIT(0x040, 1),
+	CMU_DMA		= _REG_BIT(0x040, 0)
+};
+
+enum cmu_osc {
+	HFRCO, /**< Internal, 1 - 28Mhz */
+	LFRCO, /**< Internal, 32.768kHz */
+	ULFRCO, /**< Internal, 1Khz */
+	HFXO, /**< External, 4-48Mhz */
+	LFXO, /**< External, 32.768kHz */
+	AUXHFRCO, /**< Internal, 1-28Mhz */
+};
+
+/* --- Function prototypes ------------------------------------------------- */
+
+BEGIN_DECLS
+
+void cmu_enable_lock(void);
+void cmu_disable_lock(void);
+bool cmu_get_lock_flag(void);
+
+void cmu_periph_clock_enable(enum cmu_periph_clken periph);
+void cmu_periph_clock_disable(enum cmu_periph_clken periph);
+
+/* TODO: CMU_CTRL, CMU_HFCORECLKDIV, CMU_HFPERCLKDIV, CMU_HFRCOCTRL,
+ *       CMU_LFRCOCTRL, CMU_AUXHFRCOCTRL, CMU_CALCTRL, CMU_CALCNT */
+
+void cmu_osc_on(enum cmu_osc osc);
+void cmu_osc_off(enum cmu_osc osc);
+
+/* TODO: CMU_CMD, CMU_LFCLKSEL */
+
+/* TODO: portions of CMU_STATUS */
+bool cmu_osc_ready_flag(enum cmu_osc osc);
+void cmu_wait_for_osc_ready(enum cmu_osc osc);
+void cmu_set_hfclk_source(enum cmu_osc osc);
+void cmu_set_usbclk_source(enum cmu_osc osc);
+enum cmu_osc cmu_get_hfclk_source(void);
+
+/* TODO: CMU_IF, CMU_IFS, CMU_IFC, CMU_IEN */
+
+/* TODO: CMU_SYNCBUSY, CMU_FREEZE, CMU_LFACLKEN0 */
+
+/* TODO: CMU_LFAPRESC0, CMU_LFBPRESC0, CMU_PCNTCTRL, CMU_LCDCTRL, CMU_ROUTE */
+
+void cmu_clock_setup_in_hfxo_out_48mhz(void);
+
+END_DECLS
+
+/**@}*/

3rd/libopencm3/include/libopencm3/efm32/common/dac_common.h

@@ -0,0 +1,514 @@
+/** @addtogroup dac_defines
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/efm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/efm32/prs.h>
+
+/**@{*/
+
+#define DAC_CTRL(base)		MMIO32((base) + 0x00)
+#define DAC_STATUS(base)	MMIO32((base) + 0x04)
+#define DAC_CHx_CTRL(base, x)	MMIO32((base) + 0x08 + (0x04 * (x)))
+#define DAC_CH0CTRL(base)	DAC_CHx_CTRL(base, 0)
+#define DAC_CH1CTRL(base)	DAC_CHx_CTRL(base, 1)
+#define DAC_IEN(base)		MMIO32((base) + 0x010)
+#define DAC_IF(base)		MMIO32((base) + 0x014)
+#define DAC_IFS(base)		MMIO32((base) + 0x018)
+#define DAC_IFC(base)		MMIO32((base) + 0x01C)
+#define DAC_CH0DATA(base)	MMIO32((base) + 0x020)
+#define DAC_CH1DATA(base)	MMIO32((base) + 0x024)
+#define DAC_COMBDATA(base)	MMIO32((base) + 0x028)
+#define DAC_CAL(base)		MMIO32((base) + 0x02C)
+#define DAC_BIASPROG(base)	MMIO32((base) + 0x030)
+#define DAC_OPACTRL(base)	MMIO32((base) + 0x054)
+#define DAC_OPAOFFSET(base) MMIO32((base) + 0x058)
+#define DAC_OPA0MUX(base)	MMIO32((base) + 0x05C)
+#define DAC_OPA1MUX(base)	MMIO32((base) + 0x060)
+#define DAC_OPA2MUX(base)	MMIO32((base) + 0x064)
+
+/* DAC_CTRL */
+#define DAC_CTRL_REFRSEL_SHIFT		(20)
+#define DAC_CTRL_REFRSEL_MASK		(0x3 << DAC_CTRL_REFRSEL_SHIFT)
+#define DAC_CTRL_REFRSEL(v)			\
+	(((v) << DAC_CTRL_REFRSEL_SHIFT) & DAC_CTRL_REFRSEL_MASK)
+#define DAC_CTRL_REFRSEL_8CYCLES	0
+#define DAC_CTRL_REFRSEL_16CYCLES	1
+#define DAC_CTRL_REFRSEL_32CYCLES	2
+#define DAC_CTRL_REFRSEL_64CYCLES	3
+
+#define DAC_CTRL_PRESC_SHIFT		(16)
+#define DAC_CTRL_PRESC_MASK		(0x7 << DAC_CTRL_PRESC_SHIFT)
+#define DAC_CTRL_PRESC(v)		\
+	(((v) << DAC_CTRL_PRESC_SHIFT) & DAC_CTRL_PRESC_MASK)
+#define DAC_CTRL_PRESC_DIV1		0
+#define DAC_CTRL_PRESC_DIV2		1
+#define DAC_CTRL_PRESC_DIV4		2
+#define DAC_CTRL_PRESC_DIV8		3
+#define DAC_CTRL_PRESC_DIV16		4
+#define DAC_CTRL_PRESC_DIV32		5
+#define DAC_CTRL_PRESC_DIV64		6
+#define DAC_CTRL_PRESC_DIV128		7
+#define DAC_CTRL_PRESC_NODIV		DAC_CTRL_PRESC_DIV1
+
+#define DAC_CTRL_REFSEL_SHIFT		(8)
+#define DAC_CTRL_REFSEL_MASK		(0x3 << DAC_CTRL_REFSEL_SHIFT)
+#define DAC_CTRL_REFSEL(v)		\
+	(((v) << DAC_CTRL_REFSEL_SHIFT) & DAC_CTRL_REFSEL_MASK)
+#define DAC_CTRL_REFSEL_1V25		0
+#define DAC_CTRL_REFSEL_2V5		1
+#define DAC_CTRL_REFSEL_VDD		2
+
+#define DAC_CTRL_CH0PRESCRST		(1 << 7)
+#define DAC_CTRL_OUTENPRS		(1 << 6)
+
+#define DAC_CTRL_OUTMODE_SHIFT		(4)
+#define DAC_CTRL_OUTMODE_MASK		(0x3 << DAC_CTRL_OUTMODE_SHIFT)
+#define DAC_CTRL_OUTMODE(v)		\
+	(((v) << DAC_CTRL_OUTMODE_SHIFT) & DAC_CTRL_OUTMODE_MASK)
+#define DAC_CTRL_OUTMODE_DISABLE	0
+#define DAC_CTRL_OUTMODE_PIN		1
+#define DAC_CTRL_OUTMODE_ADC		2
+#define DAC_CTRL_OUTMODE_PINADC		3
+
+#define DAC_CTRL_CONVMODE_SHIFT		(2)
+#define DAC_CTRL_CONVMODE_MASK		(0x3 << DAC_CTRL_CONVMODE_SHIFT)
+#define DAC_CTRL_CONVMODE(v)		\
+	(((v) << DAC_CTRL_CONVMODE_SHIFT) & DAC_CTRL_CONVMODE_MASK)
+#define DAC_CTRL_CONVMODE_CONTINUOUS	0
+#define DAC_CTRL_CONVMODE_SAMPLEHOLD	1
+#define DAC_CTRL_CONVMODE_SAMPLEOFF	2
+
+#define DAC_CTRL_SINMODE		(1 << 1)
+#define DAC_CTRL_DIFF			(1 << 0)
+
+/* DAC_STATUS */
+#define DAC_STATUS_CH1DV		(1 << 1)
+#define DAC_STATUS_CH0DV		(1 << 0)
+
+/* DAC_CH_CTRL */
+#define DAC_CH_CTRL_PRSSEL_SHIFT	(4)
+#define DAC_CH_CTRL_PRSSEL_MASK		(0xF << DAC_CH_CTRL_PRSSEL_SHIFT)
+#define DAC_CH_CTRL_PRSSEL(v)		\
+	(((v) << DAC_CH_CTRL_PRSSEL_SHIFT) & DAC_CH_CTRL_PRSSEL_MASK)
+#define DAC_CH_CTRL_PRSSEL_PRSCHx(x)	DAC_CH_CTRL_PRSSEL(x)
+#define DAC_CH_CTRL_PRSSEL_PRSCH0	0
+#define DAC_CH_CTRL_PRSSEL_PRSCH1	1
+#define DAC_CH_CTRL_PRSSEL_PRSCH2	2
+#define DAC_CH_CTRL_PRSSEL_PRSCH3	3
+#define DAC_CH_CTRL_PRSSEL_PRSCH4	4
+#define DAC_CH_CTRL_PRSSEL_PRSCH5	5
+#define DAC_CH_CTRL_PRSSEL_PRSCH6	6
+#define DAC_CH_CTRL_PRSSEL_PRSCH7	7
+#define DAC_CH_CTRL_PRSSEL_PRSCH8	8
+#define DAC_CH_CTRL_PRSSEL_PRSCH9	9
+#define DAC_CH_CTRL_PRSSEL_PRSCH10	10
+#define DAC_CH_CTRL_PRSSEL_PRSCH11	11
+
+#define DAC_CH_CTRL_PRSEN	(1 << 2)
+#define DAC_CH_CTRL_REFREN	(1 << 1)
+#define DAC_CH_CTRL_EN		(1 << 0)
+
+/* DAC_CH0CTRL */
+#define DAC_CH0CTRL_PRSSEL_SHIFT	DAC_CH_CTRL_PRSSEL_SHIFT
+#define DAC_CH0CTRL_PRSSEL_MASK		DAC_CH_CTRL_PRSSEL_MASK
+#define DAC_CH0CTRL_PRSSEL(v)		DAC_CH_CTRL_PRSSEL(v)
+#define DAC_CH0CTRL_PRSSEL_PRSCHx(x)	DAC_CH_CTRL_PRSSEL_PRSCHx(x)
+#define DAC_CH0CTRL_PRSSEL_PRSCH0	DAC_CH0CTRL_PRSSEL_PRSCH0
+#define DAC_CH0CTRL_PRSSEL_PRSCH1	DAC_CH_CTRL_PRSSEL_PRSCH1
+#define DAC_CH0CTRL_PRSSEL_PRSCH2	DAC_CH_CTRL_PRSSEL_PRSCH2
+#define DAC_CH0CTRL_PRSSEL_PRSCH3	DAC_CH_CTRL_PRSSEL_PRSCH3
+#define DAC_CH0CTRL_PRSSEL_PRSCH4	DAC_CH_CTRL_PRSSEL_PRSCH4
+#define DAC_CH0CTRL_PRSSEL_PRSCH5	DAC_CH_CTRL_PRSSEL_PRSCH5
+#define DAC_CH0CTRL_PRSSEL_PRSCH6	DAC_CH_CTRL_PRSSEL_PRSCH6
+#define DAC_CH0CTRL_PRSSEL_PRSCH7	DAC_CH_CTRL_PRSSEL_PRSCH7
+#define DAC_CH0CTRL_PRSSEL_PRSCH8	DAC_CH_CTRL_PRSSEL_PRSCH8
+#define DAC_CH0CTRL_PRSSEL_PRSCH9	DAC_CH_CTRL_PRSSEL_PRSCH9
+#define DAC_CH0CTRL_PRSSEL_PRSCH10	DAC_CH_CTRL_PRSSEL_PRSCH10
+#define DAC_CH0CTRL_PRSSEL_PRSCH11	DAC_CH_CTRL_PRSSEL_PRSCH11
+
+#define DAC_CH0CTRL_PRSEN	DAC_CH_CTRL_PRSEN
+#define DAC_CH0CTRL_REFREN	DAC_CH_CTRL_REFREN
+#define DAC_CH0CTRL_EN		DAC_CH_CTRL_EN
+
+/* DAC_CH1CTRL */
+#define DAC_CH1CTRL_PRSSEL_SHIFT	DAC_CH_CTRL_PRSSEL_SHIFT
+#define DAC_CH1CTRL_PRSSEL_MASK		DAC_CH_CTRL_PRSSEL_MASK
+#define DAC_CH1CTRL_PRSSEL(v)		DAC_CH_CTRL_PRSSEL(v)
+#define DAC_CH1CTRL_PRSSEL_PRSCHx(x)	DAC_CH_CTRL_PRSSEL_PRSCHx(x)
+#define DAC_CH1CTRL_PRSSEL_PRSCH0	DAC_CH_CTRL_PRSSEL_PRSCH0
+#define DAC_CH1CTRL_PRSSEL_PRSCH1	DAC_CH_CTRL_PRSSEL_PRSCH1
+#define DAC_CH1CTRL_PRSSEL_PRSCH2	DAC_CH_CTRL_PRSSEL_PRSCH2
+#define DAC_CH1CTRL_PRSSEL_PRSCH3	DAC_CH_CTRL_PRSSEL_PRSCH3
+#define DAC_CH1CTRL_PRSSEL_PRSCH4	DAC_CH_CTRL_PRSSEL_PRSCH4
+#define DAC_CH1CTRL_PRSSEL_PRSCH5	DAC_CH_CTRL_PRSSEL_PRSCH5
+#define DAC_CH1CTRL_PRSSEL_PRSCH6	DAC_CH_CTRL_PRSSEL_PRSCH6
+#define DAC_CH1CTRL_PRSSEL_PRSCH7	DAC_CH_CTRL_PRSSEL_PRSCH7
+#define DAC_CH1CTRL_PRSSEL_PRSCH8	DAC_CH_CTRL_PRSSEL_PRSCH8
+#define DAC_CH1CTRL_PRSSEL_PRSCH9	DAC_CH_CTRL_PRSSEL_PRSCH9
+#define DAC_CH1CTRL_PRSSEL_PRSCH10	DAC_CH_CTRL_PRSSEL_PRSCH10
+#define DAC_CH1CTRL_PRSSEL_PRSCH11	DAC_CH_CTRL_PRSSEL_PRSCH11
+
+#define DAC_CH1CTRL_PRSEN	DAC_CH_CTRL_PRSEN
+#define DAC_CH1CTRL_REFREN	DAC_CH_CTRL_REFREN
+#define DAC_CH1CTRL_EN		DAC_CH_CTRL_EN
+
+/* DAC_IEN */
+#define DAC_IEN_CH1UF	(5 << 0)
+#define DAC_IEN_CH0UF	(4 << 0)
+#define DAC_IEN_CH1	(1 << 1)
+#define DAC_IEN_CH0	(1 << 0)
+
+/* DAC_IF */
+#define DAC_IF_CH1UF	(5 << 0)
+#define DAC_IF_CH0UF	(4 << 0)
+#define DAC_IF_CH1	(1 << 1)
+#define DAC_IF_CH0	(1 << 0)
+
+/* DAC_IFS */
+#define DAC_IFS_CH1UF	(5 << 0)
+#define DAC_IFS_CH0UF	(4 << 0)
+#define DAC_IFS_CH1	(1 << 1)
+#define DAC_IFS_CH0	(1 << 0)
+
+/* DAC_IFC */
+#define DAC_IFC_CH1UF	(5 << 0)
+#define DAC_IFC_CH0UF	(4 << 0)
+#define DAC_IFC_CH1	(1 << 1)
+#define DAC_IFC_CH0	(1 << 0)
+
+/* DAC_CAL */
+#define DAC_CAL_GAIN_SHIFT	(16)
+#define DAC_CAL_GAIN_MASK	(0x7F << DAC_CAL_GAIN_SHIFT)
+#define DAC_CAL_GAIN(v)		\
+	(((v) << DAC_CAL_GAIN_SHIFT) & DAC_CAL_GAIN_MASK)
+
+#define DAC_CAL_CH1OFFSET_SHIFT	(8)
+#define DAC_CAL_CH1OFFSET_MASK	(0x3F << DAC_CAL_CH1OFFSET_SHIFT)
+#define DAC_CAL_CH1OFFSET(v)	\
+	(((v) << DAC_CAL_CH1OFFSET_SHIFT) & DAC_CAL_CH1OFFSET_MASK)
+
+#define DAC_CAL_CH0OFFSET_SHIFT	(0)
+#define DAC_CAL_CH0OFFSET_MASK	(0x3F << DAC_CAL_CH0OFFSET_SHIFT)
+#define DAC_CAL_CH0OFFSET(v)	\
+	(((v) << DAC_CAL_CH0OFFSET_SHIFT) & DAC_CAL_CH0OFFSET_MASK)
+
+/* DAC_BIASPROG */
+#define DAC_BIASPROG_OPA2HALFBIAS	(1 << 14)
+
+#define DAC_BIASPROG_OPA2BIASPROG_SHIFT	(8)
+#define DAC_BIASPROG_OPA2BIASPROG_MASK	(0xF << DAC_BIASPROG_OPA2BIASPROG_SHIFT)
+#define DAC_BIASPROG_OPA2BIASPROG(v)		\
+	((((v) << DAC_BIASPROG_OPA2BIASPROG_SHIFT)) & \
+	DAC_BIASPROG_OPA2BIASPROG_MASK)
+
+#define DAC_BIASPROG_HALFBIAS		(1 << 6)
+
+#define DAC_BIASPROG_BIASPROG_SHIFT	(0)
+#define DAC_BIASPROG_BIASPROG_MASK	(0xF << DAC_BIASPROG_BIASPROG_SHIFT)
+#define DAC_BIASPROG_BIASPROG(v)	\
+	((((v) << DAC_BIASPROG_BIASPROG_SHIFT)) & DAC_BIASPROG_BIASPROG_MASK)
+
+/* DAC_OPACTRL */
+#define DAC_OPACTRL_OPA2SHORT		(1 << 24)
+#define DAC_OPACTRL_OPA1SHORT		(1 << 23)
+#define DAC_OPACTRL_OPA0SHORT		(1 << 22)
+
+#define DAC_OPACTRL_OPA2LPFDIS_SHIFT	(16)
+#define DAC_OPACTRL_OPA2LPFDIS_MASK	(0x3 << DAC_OPACTRL_OPA2LPFDIS_SHIFT)
+#define DAC_OPACTRL_OPA2LPFDIS(v)	\
+	(((v) << DAC_OPACTRL_OPA2LPFDIS_SHIFT) & DAC_OPACTRL_OPA2LPFDIS_MASK)
+#define DAC_OPACTRL_OPA2LPFDIS_PLPFDIS	0b01
+#define DAC_OPACTRL_OPA2LPFDIS_NLPFDIS	0b10
+
+#define DAC_OPACTRL_OPA1LPFDIS_SHIFT	(14)
+#define DAC_OPACTRL_OPA1LPFDIS_MASK	(0x3 << DAC_OPACTRL_OPA1LPFDIS_SHIFT)
+#define DAC_OPACTRL_OPA1LPFDIS(v)	\
+	(((v) << DAC_OPACTRL_OPA1LPFDIS_SHIFT) & DAC_OPACTRL_OPA1LPFDIS_MASK)
+#define DAC_OPACTRL_OPA1LPFDIS_PLPFDIS	0b01
+#define DAC_OPACTRL_OPA1LPFDIS_NLPFDIS	0b10
+
+#define DAC_OPACTRL_OPA0LPFDIS_SHIFT	(14)
+#define DAC_OPACTRL_OPA0LPFDIS_MASK	(0x3 << DAC_OPACTRL_OPA0LPFDIS_SHIFT)
+#define DAC_OPACTRL_OPA0LPFDIS(v)	\
+	(((v) << DAC_OPACTRL_OPA0LPFDIS_SHIFT) & DAC_OPACTRL_OPA0LPFDIS_MASK)
+#define DAC_OPACTRL_OPA0LPFDIS_PLPFDIS	0b01
+#define DAC_OPACTRL_OPA0LPFDIS_NLPFDIS	0b10
+
+#define DAC_OPACTRL_OPA2HCMDIS		(1 << 8)
+#define DAC_OPACTRL_OPA1HCMDIS		(1 << 7)
+#define DAC_OPACTRL_OPA0HCMDIS		(1 << 6)
+
+#define DAC_OPACTRL_OPA2EN		(1 << 2)
+#define DAC_OPACTRL_OPA1EN		(1 << 1)
+#define DAC_OPACTRL_OPA0EN		(1 << 0)
+
+/* DAC_OPA0MUX */
+#define DAC_OPA0MUX_RESSEL_SHIFT	(28)
+#define DAC_OPA0MUX_RESSEL_MASK		(0x7 << DAC_OPA0MUX_RESSEL_SHIFT)
+#define DAC_OPA0MUX_RESSEL_RESSEL(v)	\
+	((((v) << DAC_OPA0MUX_RESSEL_SHIFT)) & DAC_OPA0MUX_RESSEL_MASK)
+#define DAC_OPA0MUX_RESSEL_RESSEL_RESx(x)	DAC_OPA0MUX_RESSEL_RESSEL(x)
+#define DAC_OPA0MUX_RESSEL_RESSEL_RES0	DAC_OPA0MUX_RESSEL_RESSEL_RESx(0)
+#define DAC_OPA0MUX_RESSEL_RESSEL_RES1	DAC_OPA0MUX_RESSEL_RESSEL_RESx(1)
+#define DAC_OPA0MUX_RESSEL_RESSEL_RES2	DAC_OPA0MUX_RESSEL_RESSEL_RESx(2)
+#define DAC_OPA0MUX_RESSEL_RESSEL_RES3	DAC_OPA0MUX_RESSEL_RESSEL_RESx(3)
+#define DAC_OPA0MUX_RESSEL_RESSEL_RES4	DAC_OPA0MUX_RESSEL_RESSEL_RESx(4)
+#define DAC_OPA0MUX_RESSEL_RESSEL_RES5	DAC_OPA0MUX_RESSEL_RESSEL_RESx(5)
+#define DAC_OPA0MUX_RESSEL_RESSEL_RES6	DAC_OPA0MUX_RESSEL_RESSEL_RESx(6)
+#define DAC_OPA0MUX_RESSEL_RESSEL_RES7	DAC_OPA0MUX_RESSEL_RESSEL_RESx(7)
+
+#define DAC_OPA0MUX_NEXTOUT		(1 << 26)
+
+#define DAC_OPA0MUX_OUTMODE_SHIFT	(22)
+#define DAC_OPA0MUX_OUTMODE_MASK	(0x3 << DAC_OPA0MUX_OUTMODE_SHIFT)
+#define DAC_OPA0MUX_OUTMODE(v)		\
+	(((v) << DAC_OPA0MUX_OUTMODE_SHIFT) & DAC_OPA0MUX_OUTMODE_MASK)
+#define DAC_OPA0MUX_OUTMODE_DISABLE	0
+#define DAC_OPA0MUX_OUTMODE_MAIN	1
+#define DAC_OPA0MUX_OUTMODE_ALT		2
+#define DAC_OPA0MUX_OUTMODE_ALL		3
+
+#define DAC_OPA0MUX_OUTPEN_SHIFT	(18)
+#define DAC_OPA0MUX_OUTPEN_MASK		(0x1F << DAC_OPA0MUX_OUTPEN_SHIFT)
+#define DAC_OPA0MUX_OUTPEN(v)		\
+	(((v) << DAC_OPA0MUX_OUTPEN_SHIFT) & DAC_OPA0MUX_OUTPEN_MASK)
+#define DAC_OPA0MUX_OUTPEN_OUT0		DAC_OPA0MUX_OUTPEN(1 << 0)
+#define DAC_OPA0MUX_OUTPEN_OUT1		DAC_OPA0MUX_OUTPEN(1 << 1)
+#define DAC_OPA0MUX_OUTPEN_OUT2		DAC_OPA0MUX_OUTPEN(1 << 2)
+#define DAC_OPA0MUX_OUTPEN_OUT3		DAC_OPA0MUX_OUTPEN(1 << 3)
+#define DAC_OPA0MUX_OUTPEN_OUT4		DAC_OPA0MUX_OUTPEN(1 << 4)
+
+#define DAC_OPA0MUX_NPEN		(1 << 13)
+#define DAC_OPA0MUX_PPEN		(1 << 12)
+
+#define DAC_OPA0MUX_RESINMUX_SHIFT	(8)
+#define DAC_OPA0MUX_RESINMUX_MASK	(0x7 << DAC_OPA0MUX_RESINMUX_SHIFT)
+#define DAC_OPA0MUX_RESINMUX(v)		\
+	(((v) << DAC_OPA0MUX_RESINMUX_SHIFT) & DAC_OPA0MUX_RESINMUX_MASK)
+#define DAC_OPA0MUX_RESINMUX_DISABLE	0
+#define DAC_OPA0MUX_RESINMUX_OPA0INP	1
+#define DAC_OPA0MUX_RESINMUX_NEGPAD	2
+#define DAC_OPA0MUX_RESINMUX_POSPAD	3
+#define DAC_OPA0MUX_RESINMUX_VSS	4
+
+#define DAC_OPA0MUX_NEGSEL_SHIFT	(4)
+#define DAC_OPA0MUX_NEGSEL_MASK		(0x3 << DAC_OPA0MUX_NEGSEL_SHIFT)
+#define DAC_OPA0MUX_NEGSEL(v)		\
+	(((v) << DAC_OPA0MUX_NEGSEL_SHIFT) & DAC_OPA0MUX_NEGSEL_MASK)
+#define DAC_OPA0MUX_NEGSEL_DISABLE	0
+#define DAC_OPA0MUX_NEGSEL_UG		1
+#define DAC_OPA0MUX_NEGSEL_OPATAP	2
+#define DAC_OPA0MUX_NEGSEL_NEGPAD	3
+
+#define DAC_OPA0MUX_POSSEL_SHIFT	(0)
+#define DAC_OPA0MUX_POSSEL_MASK		(0x7 << DAC_OPA0MUX_POSSEL_SHIFT)
+#define DAC_OPA0MUX_POSSEL(v)		\
+	(((v) << DAC_OPA0MUX_POSSEL_SHIFT) & DAC_OPA0MUX_POSSEL_MASK)
+#define DAC_OPA0MUX_POSSEL_DISABLE	0
+#define DAC_OPA0MUX_POSSEL_DAC		1
+#define DAC_OPA0MUX_POSSEL_POSPAD	2
+#define DAC_OPA0MUX_POSSEL_OPA0INP	3
+#define DAC_OPA0MUX_POSSEL_OPATAP	4
+
+/* DAC_OPA1MUX */
+#define DAC_OPA1MUX_RESSEL_SHIFT	(28)
+#define DAC_OPA1MUX_RESSEL_MASK		(0x7 << DAC_OPA1MUX_RESSEL_SHIFT)
+#define DAC_OPA1MUX_RESSEL_RESSEL(v)	\
+	((((v) << DAC_OPA1MUX_RESSEL_SHIFT)) & DAC_OPA1MUX_RESSEL_MASK)
+#define DAC_OPA1MUX_RESSEL_RESSEL_RESx(x)	DAC_OPA1MUX_RESSEL_RESSEL(x)
+#define DAC_OPA1MUX_RESSEL_RESSEL_RES0	DAC_OPA1MUX_RESSEL_RESSEL_RESx(0)
+#define DAC_OPA1MUX_RESSEL_RESSEL_RES1	DAC_OPA1MUX_RESSEL_RESSEL_RESx(1)
+#define DAC_OPA1MUX_RESSEL_RESSEL_RES2	DAC_OPA1MUX_RESSEL_RESSEL_RESx(2)
+#define DAC_OPA1MUX_RESSEL_RESSEL_RES3	DAC_OPA1MUX_RESSEL_RESSEL_RESx(3)
+#define DAC_OPA1MUX_RESSEL_RESSEL_RES4	DAC_OPA1MUX_RESSEL_RESSEL_RESx(4)
+#define DAC_OPA1MUX_RESSEL_RESSEL_RES5	DAC_OPA1MUX_RESSEL_RESSEL_RESx(5)
+#define DAC_OPA1MUX_RESSEL_RESSEL_RES6	DAC_OPA1MUX_RESSEL_RESSEL_RESx(6)
+#define DAC_OPA1MUX_RESSEL_RESSEL_RES7	DAC_OPA1MUX_RESSEL_RESSEL_RESx(7)
+
+#define DAC_OPA1MUX_NEXTOUT	(1 << 26)
+
+#define DAC_OPA1MUX_OUTMODE_SHIFT	(22)
+#define DAC_OPA1MUX_OUTMODE_MASK	(0x3 << DAC_OPA1MUX_OUTMODE_SHIFT)
+#define DAC_OPA1MUX_OUTMODE(v)		\
+	(((v) << DAC_OPA1MUX_OUTMODE_SHIFT) & DAC_OPA1MUX_OUTMODE_MASK)
+#define DAC_OPA1MUX_OUTMODE_DISABLE	0
+#define DAC_OPA1MUX_OUTMODE_MAIN	1
+#define DAC_OPA1MUX_OUTMODE_ALT		2
+#define DAC_OPA1MUX_OUTMODE_ALL		3
+
+#define DAC_OPA1MUX_OUTPEN_SHIFT	(18)
+#define DAC_OPA1MUX_OUTPEN_MASK		(0x1F << DAC_OPA1MUX_OUTPEN_SHIFT)
+#define DAC_OPA1MUX_OUTPEN(v)		\
+	(((v) << DAC_OPA1MUX_OUTPEN_SHIFT) & DAC_OPA1MUX_OUTPEN_MASK)
+#define DAC_OPA1MUX_OUTPEN_OUT0		DAC_OPA1MUX_OUTPEN(1 << 0)
+#define DAC_OPA1MUX_OUTPEN_OUT1		DAC_OPA1MUX_OUTPEN(1 << 1)
+#define DAC_OPA1MUX_OUTPEN_OUT2		DAC_OPA1MUX_OUTPEN(1 << 2)
+#define DAC_OPA1MUX_OUTPEN_OUT3		DAC_OPA1MUX_OUTPEN(1 << 3)
+#define DAC_OPA1MUX_OUTPEN_OUT4		DAC_OPA1MUX_OUTPEN(1 << 4)
+
+#define DAC_OPA1MUX_NPEN		(1 << 13)
+#define DAC_OPA1MUX_PPEN		(1 << 12)
+
+#define DAC_OPA1MUX_RESINMUX_SHIFT	(8)
+#define DAC_OPA1MUX_RESINMUX_MASK	(0x7 << DAC_OPA1MUX_RESINMUX_SHIFT)
+#define DAC_OPA1MUX_RESINMUX(v)		\
+	(((v) << DAC_OPA1MUX_RESINMUX_SHIFT) & DAC_OPA1MUX_RESINMUX_MASK)
+#define DAC_OPA1MUX_RESINMUX_DISABLE	0
+#define DAC_OPA1MUX_RESINMUX_OPA0INP	1
+#define DAC_OPA1MUX_RESINMUX_NEGPAD	2
+#define DAC_OPA1MUX_RESINMUX_POSPAD	3
+#define DAC_OPA1MUX_RESINMUX_VSS	4
+
+#define DAC_OPA1MUX_NEGSEL_SHIFT	(4)
+#define DAC_OPA1MUX_NEGSEL_MASK		(0x3 << DAC_OPA1MUX_NEGSEL_SHIFT)
+#define DAC_OPA1MUX_NEGSEL(v)		\
+	(((v) << DAC_OPA1MUX_NEGSEL_SHIFT) & DAC_OPA1MUX_NEGSEL_MASK)
+#define DAC_OPA1MUX_NEGSEL_DISABLE	0
+#define DAC_OPA1MUX_NEGSEL_UG		1
+#define DAC_OPA1MUX_NEGSEL_OPATAP	2
+#define DAC_OPA1MUX_NEGSEL_NEGPAD	3
+
+#define DAC_OPA1MUX_POSSEL_SHIFT	(0)
+#define DAC_OPA1MUX_POSSEL_MASK		(0x7 << DAC_OPA1MUX_POSSEL_SHIFT)
+#define DAC_OPA1MUX_POSSEL(v)		\
+	(((v) << DAC_OPA1MUX_POSSEL_SHIFT) & DAC_OPA1MUX_POSSEL_MASK)
+#define DAC_OPA1MUX_POSSEL_DISABLE	0
+#define DAC_OPA1MUX_POSSEL_DAC		1
+#define DAC_OPA1MUX_POSSEL_POSPAD	2
+#define DAC_OPA1MUX_POSSEL_OPA0INP	3
+#define DAC_OPA1MUX_POSSEL_OPATAP	4
+
+
+/* DAC_OPA2MUX */
+#define DAC_OPA2MUX_RESSEL_SHIFT	(28)
+#define DAC_OPA2MUX_RESSEL_MASK		(0x7 << DAC_OPA2MUX_RESSEL_SHIFT)
+#define DAC_OPA2MUX_RESSEL_RESSEL(v)	\
+	((((v) << DAC_OPA2MUX_RESSEL_SHIFT)) & DAC_OPA2MUX_RESSEL_MASK)
+#define DAC_OPA2MUX_RESSEL_RESSEL_RESx(x)	DAC_OPA2MUX_RESSEL_RESSEL(x)
+#define DAC_OPA2MUX_RESSEL_RESSEL_RES0	DAC_OPA2MUX_RESSEL_RESSEL_RESx(0)
+#define DAC_OPA2MUX_RESSEL_RESSEL_RES1	DAC_OPA2MUX_RESSEL_RESSEL_RESx(1)
+#define DAC_OPA2MUX_RESSEL_RESSEL_RES2	DAC_OPA2MUX_RESSEL_RESSEL_RESx(2)
+#define DAC_OPA2MUX_RESSEL_RESSEL_RES3	DAC_OPA2MUX_RESSEL_RESSEL_RESx(3)
+#define DAC_OPA2MUX_RESSEL_RESSEL_RES4	DAC_OPA2MUX_RESSEL_RESSEL_RESx(4)
+#define DAC_OPA2MUX_RESSEL_RESSEL_RES5	DAC_OPA2MUX_RESSEL_RESSEL_RESx(5)
+#define DAC_OPA2MUX_RESSEL_RESSEL_RES6	DAC_OPA2MUX_RESSEL_RESSEL_RESx(6)
+#define DAC_OPA2MUX_RESSEL_RESSEL_RES7	DAC_OPA2MUX_RESSEL_RESSEL_RESx(7)
+
+#define DAC_OPA2MUX_NEXTOUT	(1 << 26)
+
+#define DAC_OPA2MUX_OUTMODE	(1 << 22)
+
+#define DAC_OPA2MUX_OUTPEN_SHIFT	(14)
+#define DAC_OPA2MUX_OUTPEN_MASK		(0x3 << DAC_OPA2MUX_OUTPEN_SHIFT)
+#define DAC_OPA2MUX_OUTPEN(v)		\
+	(((v) << DAC_OPA2MUX_OUTPEN_SHIFT) & DAC_OPA2MUX_OUTPEN_MASK)
+#define DAC_OPA2MUX_OUTPEN_OUT0		0
+#define DAC_OPA2MUX_OUTPEN_OUT1		1
+
+#define DAC_OPA2MUX_NPEN	(1 << 13)
+#define DAC_OPA2MUX_PPEN	(1 << 12)
+
+#define DAC_OPA2MUX_RESINMUX_SHIFT	(8)
+#define DAC_OPA2MUX_RESINMUX_MASK	(0x7 << DAC_OPA2MUX_RESINMUX_SHIFT)
+#define DAC_OPA2MUX_RESINMUX(v)		\
+	(((v) << DAC_OPA2MUX_RESINMUX_SHIFT) & DAC_OPA2MUX_RESINMUX_MASK)
+#define DAC_OPA2MUX_RESINMUX_DISABLE	0
+#define DAC_OPA2MUX_RESINMUX_OPA1INP	1
+#define DAC_OPA2MUX_RESINMUX_NEGPAD		2
+#define DAC_OPA2MUX_RESINMUX_POSPAD		3
+#define DAC_OPA2MUX_RESINMUX_VSS		4
+
+#define DAC_OPA2MUX_NEGSEL_SHIFT	(4)
+#define DAC_OPA2MUX_NEGSEL_MASK		(0x3 << DAC_OPA2MUX_NEGSEL_SHIFT)
+#define DAC_OPA2MUX_NEGSEL(v)		\
+	(((v) << DAC_OPA2MUX_NEGSEL_SHIFT) & DAC_OPA2MUX_NEGSEL_MASK)
+#define DAC_OPA2MUX_NEGSEL_DISABLE	0
+#define DAC_OPA2MUX_NEGSEL_UG		1
+#define DAC_OPA2MUX_NEGSEL_OPATAP	2
+#define DAC_OPA2MUX_NEGSEL_NEGPAD	3
+
+#define DAC_OPA2MUX_POSSEL_SHIFT	(0)
+#define DAC_OPA2MUX_POSSEL_MASK		(0x7 << DAC_OPA2MUX_POSSEL_SHIFT)
+#define DAC_OPA2MUX_POSSEL(v)		\
+	(((v) << DAC_OPA2MUX_POSSEL_SHIFT) & DAC_OPA2MUX_POSSEL_MASK)
+#define DAC_OPA2MUX_POSSEL_DISABLE	0
+#define DAC_OPA2MUX_POSSEL_DAC		1
+#define DAC_OPA2MUX_POSSEL_POSPAD	2
+#define DAC_OPA2MUX_POSSEL_OPA1INP	3
+#define DAC_OPA2MUX_POSSEL_OPATAP	4
+
+/* DAC0 */
+#define DAC0			DAC0_BASE
+#define DAC0_CTRL		DAC_CTRL(DAC0)
+#define DAC0_STATUS		DAC_STATUS(DAC0)
+#define DAC0_CH0CTRL		DAC_CH0CTRL(DAC0)
+#define DAC0_CH1CTRL		DAC_CH1CTRL(DAC0)
+#define DAC0_IEN		DAC_IEN(DAC0)
+#define DAC0_IF			DAC_IF(DAC0)
+#define DAC0_IFS		DAC_IFS(DAC0)
+#define DAC0_IFC		DAC_IFC(DAC0)
+#define DAC0_CH0DATA		DAC_CH0DATA(DAC0)
+#define DAC0_CH1DATA		DAC_CH1DATA(DAC0)
+#define DAC0_COMBDATA		DAC_COMBDATA(DAC0)
+#define DAC0_CAL		DAC_CAL(DAC0)
+#define DAC0_BIASPROG		DAC_BIASPROG(DAC0)
+#define DAC0_OPACTRL		DAC_OPACTRL(DAC0)
+#define DAC0_OPAOFFSET		DAC_OPAOFFSET(DAC0)
+#define DAC0_OPAOFFSET		DAC_OPAOFFSET(DAC0)
+#define DAC0_OPA1MUX		DAC_OPA1MUX(DAC0)
+#define DAC0_OPA2MUX		DAC_OPA2MUX(DAC0)
+
+/** @defgroup dac_ch DAC Channel Number
+@ingroup dac_defines
+
+@{*/
+enum dac_ch {
+	DAC_CH0 = 0,
+	DAC_CH1
+};
+/**@}*/
+
+BEGIN_DECLS
+
+void dac_set_refresh_cycle(uint32_t dac_base, uint32_t refrsel);
+void dac_set_clock_prescaler(uint32_t dac_base, uint32_t presc);
+void dac_set_reference(uint32_t dac_base, uint32_t refsel);
+void dac_set_out_mode(uint32_t dac_base, uint32_t outmode);
+void dac_set_conversion_mode(uint32_t dac_base, uint32_t convmode);
+void dac_enable_sine(uint32_t dac_base);
+void dac_disable_sine(uint32_t dac_base);
+
+void dac_set_prs_trigger(uint32_t dac_base, enum dac_ch dac_chan,
+		enum prs_ch prs_chan);
+void dac_enable_prs_trigger(uint32_t dac_base, enum dac_ch ch);
+void dac_disable_prs_trigger(uint32_t dac_base, enum dac_ch ch);
+void dac_enable_auto_refresh(uint32_t dac_base, enum dac_ch ch);
+void dac_disable_auto_refresh(uint32_t dac_base, enum dac_ch ch);
+
+void dac_enable_channel(uint32_t dac_base, enum dac_ch ch);
+void dac_disable_channel(uint32_t dac_base, enum dac_ch ch);
+
+END_DECLS
+
+/**@}*/

3rd/libopencm3/include/libopencm3/efm32/common/dma_common.h

@@ -0,0 +1,914 @@
+/** @addtogroup dma_defines
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/efm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/**@{*/
+
+/*
+ * As per the datasheet, it is an PL230 (licenced from ARM)
+ *  note: but only implement 12 channel (PL230 can have upto 32 channels)
+ *
+ * in-future: we can move this to a common peripherial directory
+ *   that is idependent of core and as well as uC.
+ * something like device tree in Linux kernel
+ *
+ * note: DMA_STATUS contain the number of PL230 channel are implemented
+ */
+
+#define DMA			DMA_BASE
+
+#define DMA_STATUS		MMIO32(DMA_BASE + 0x000)
+#define DMA_CONFIG		MMIO32(DMA_BASE + 0x004)
+#define DMA_CTRLBASE		MMIO32(DMA_BASE + 0x008)
+#define DMA_ALTCTRLBASE		MMIO32(DMA_BASE + 0x00C)
+
+#define DMA_CHWAITSTATUS	MMIO32(DMA_BASE + 0x010)
+#define DMA_CHSWREQ		MMIO32(DMA_BASE + 0x014)
+#define DMA_CHUSEBURSTS		MMIO32(DMA_BASE + 0x018)
+#define DMA_CHUSEBURSTC		MMIO32(DMA_BASE + 0x01C)
+#define DMA_CHREQMASKS		MMIO32(DMA_BASE + 0x020)
+#define DMA_CHREQMASKC		MMIO32(DMA_BASE + 0x024)
+#define DMA_CHENS		MMIO32(DMA_BASE + 0x028)
+#define DMA_CHENC		MMIO32(DMA_BASE + 0x02C)
+#define DMA_CHALTS		MMIO32(DMA_BASE + 0x030)
+#define DMA_CHALTC		MMIO32(DMA_BASE + 0x034)
+#define DMA_CHPRIS		MMIO32(DMA_BASE + 0x038)
+#define DMA_CHPRIC		MMIO32(DMA_BASE + 0x03C)
+#define DMA_ERRORC		MMIO32(DMA_BASE + 0x04C)
+#define DMA_CHREQSTATUS		MMIO32(DMA_BASE + 0xE10)
+#define DMA_CHSREQSTATUS	MMIO32(DMA_BASE + 0xE18)
+#define DMA_IF			MMIO32(DMA_BASE + 0x1000)
+#define DMA_IFS			MMIO32(DMA_BASE + 0x1004)
+#define DMA_IFC			MMIO32(DMA_BASE + 0x1008)
+#define DMA_IEN			MMIO32(DMA_BASE + 0x100C)
+#define DMA_CTRL		MMIO32(DMA_BASE + 0x1010)
+#define DMA_RDS			MMIO32(DMA_BASE + 0x1014)
+
+#define DMA_LOOPx(i)		MMIO32(DMA_BASE + 0x1020 + ((i) * 0x4))
+#define DMA_LOOP0		DMA_LOOPx(0)
+#define DMA_LOOP1		DMA_LOOPx(1)
+
+#define DMA_RECTx(i)		MMIO32(DMA_BASE + 0x1060 + ((i) * 0x4))
+#define DMA_RECT0		DMA_RECT(0)
+
+#define DMA_CHx_CTRL(i)		MMIO32(DMA_BASE + 0x1100 + ((i) * 0x4))
+#define DMA_CH0_CTRL		DMA_CHx_CTRL(0)
+#define DMA_CH1_CTRL		DMA_CHx_CTRL(1)
+#define DMA_CH2_CTRL		DMA_CHx_CTRL(2)
+#define DMA_CH3_CTRL		DMA_CHx_CTRL(3)
+#define DMA_CH4_CTRL		DMA_CHx_CTRL(4)
+#define DMA_CH5_CTRL		DMA_CHx_CTRL(5)
+#define DMA_CH6_CTRL		DMA_CHx_CTRL(6)
+#define DMA_CH7_CTRL		DMA_CHx_CTRL(7)
+#define DMA_CH8_CTRL		DMA_CHx_CTRL(8)
+#define DMA_CH9_CTRL		DMA_CHx_CTRL(9)
+#define DMA_CH10_CTRL		DMA_CHx_CTRL(10)
+#define DMA_CH11_CTRL		DMA_CHx_CTRL(11)
+
+/* DMA_STATUS */
+#define DMA_STATUS_CHNUM_SHIFT	(16)
+#define DMA_STATUS_CHNUM_MASK	(0x1F << DMA_STATUS_CHNUM_SHIFT)
+
+#define DMA_STATUS_STATE_SHIFT	(4)
+#define DMA_STATUS_STATE_MASK	(0xF << DMA_STATUS_STATE_SHIFT)
+#define DMA_STATUS_STATE(v)				\
+	(((v) << DMA_STATUS_STATE_SHIFT) & DMA_STATUS_STATE_MASK)
+#define DMA_STATUS_STATE_IDLE		0
+#define DMA_STATUS_STATE_RDCHCTRLDATA	1
+#define DMA_STATUS_STATE_RDSRCENDPTR	2
+#define DMA_STATUS_STATE_RDDSTENDPTR	3
+#define DMA_STATUS_STATE_RDSRCDATA	4
+#define DMA_STATUS_STATE_WRDSTDATA	5
+#define DMA_STATUS_STATE_WAITREQCLR	6
+#define DMA_STATUS_STATE_WRCHCTRLDATA	7
+#define DMA_STATUS_STATE_STALLED	8
+#define DMA_STATUS_STATE_DONE		9
+#define DMA_STATUS_STATE_PERSCATTRANS	10
+
+#define DMA_STATUS_EN			(1 << 0)
+
+/* DMA_CONFIG */
+#define DMA_CONFIG_CHPROT		(1 << 5)
+#define DMA_CONFIG_EN			(1 << 0)
+
+/* DMA_CHWAITSTATUS */
+#define DMA_CHWAITSTATUS_CHxWAITSTATUS(i)	(1 << (i))
+#define DMA_CHWAITSTATUS_CH11WAITSTATUS	DMA_CHWAITSTATUS_CHxWAITSTATUS(11)
+#define DMA_CHWAITSTATUS_CH10WAITSTATUS	DMA_CHWAITSTATUS_CHxWAITSTATUS(10)
+#define DMA_CHWAITSTATUS_CH9WAITSTATUS	DMA_CHWAITSTATUS_CHxWAITSTATUS(9)
+#define DMA_CHWAITSTATUS_CH8WAITSTATUS	DMA_CHWAITSTATUS_CHxWAITSTATUS(8)
+#define DMA_CHWAITSTATUS_CH7WAITSTATUS	DMA_CHWAITSTATUS_CHxWAITSTATUS(7)
+#define DMA_CHWAITSTATUS_CH6WAITSTATUS	DMA_CHWAITSTATUS_CHxWAITSTATUS(6)
+#define DMA_CHWAITSTATUS_CH5WAITSTATUS	DMA_CHWAITSTATUS_CHxWAITSTATUS(5)
+#define DMA_CHWAITSTATUS_CH4WAITSTATUS	DMA_CHWAITSTATUS_CHxWAITSTATUS(4)
+#define DMA_CHWAITSTATUS_CH3WAITSTATUS	DMA_CHWAITSTATUS_CHxWAITSTATUS(3)
+#define DMA_CHWAITSTATUS_CH2WAITSTATUS	DMA_CHWAITSTATUS_CHxWAITSTATUS(2)
+#define DMA_CHWAITSTATUS_CH1WAITSTATUS	DMA_CHWAITSTATUS_CHxWAITSTATUS(1)
+#define DMA_CHWAITSTATUS_CH0WAITSTATUS	DMA_CHWAITSTATUS_CHxWAITSTATUS(0)
+
+/* DMA_CHSWREQ */
+#define DMA_CHSWREQ_CHxSWREQ(i)		(1 << (i))
+#define DMA_CHSWREQ_CH11SWREQ		DMA_CHSWREQ_CHxSWREQ(11)
+#define DMA_CHSWREQ_CH10SWREQ		DMA_CHSWREQ_CHxSWREQ(10)
+#define DMA_CHSWREQ_CH9SWREQ		DMA_CHSWREQ_CHxSWREQ(9)
+#define DMA_CHSWREQ_CH8SWREQ		DMA_CHSWREQ_CHxSWREQ(8)
+#define DMA_CHSWREQ_CH7SWREQ		DMA_CHSWREQ_CHxSWREQ(7)
+#define DMA_CHSWREQ_CH6SWREQ		DMA_CHSWREQ_CHxSWREQ(6)
+#define DMA_CHSWREQ_CH5SWREQ		DMA_CHSWREQ_CHxSWREQ(5)
+#define DMA_CHSWREQ_CH4SWREQ		DMA_CHSWREQ_CHxSWREQ(4)
+#define DMA_CHSWREQ_CH3SWREQ		DMA_CHSWREQ_CHxSWREQ(3)
+#define DMA_CHSWREQ_CH2SWREQ		DMA_CHSWREQ_CHxSWREQ(2)
+#define DMA_CHSWREQ_CH1SWREQ		DMA_CHSWREQ_CHxSWREQ(1)
+#define DMA_CHSWREQ_CH0SWREQ		DMA_CHSWREQ_CHxSWREQ(0)
+
+/* DMA_CHUSEBURSTS */
+#define DMA_CHUSEBURSTS_CHxSUSEBURSTS(i)	(1 << (i))
+#define DMA_CHUSEBURSTS_CH11SUSEBURSTS	DMA_CHUSEBURSTS_CHxSUSEBURSTS(11)
+#define DMA_CHUSEBURSTS_CH10SUSEBURSTS	DMA_CHUSEBURSTS_CHxSUSEBURSTS(10)
+#define DMA_CHUSEBURSTS_CH9SUSEBURSTS	DMA_CHUSEBURSTS_CHxSUSEBURSTS(9)
+#define DMA_CHUSEBURSTS_CH8SUSEBURSTS	DMA_CHUSEBURSTS_CHxSUSEBURSTS(8)
+#define DMA_CHUSEBURSTS_CH7SUSEBURSTS	DMA_CHUSEBURSTS_CHxSUSEBURSTS(7)
+#define DMA_CHUSEBURSTS_CH6SUSEBURSTS	DMA_CHUSEBURSTS_CHxSUSEBURSTS(6)
+#define DMA_CHUSEBURSTS_CH5SUSEBURSTS	DMA_CHUSEBURSTS_CHxSUSEBURSTS(5)
+#define DMA_CHUSEBURSTS_CH4SUSEBURSTS	DMA_CHUSEBURSTS_CHxSUSEBURSTS(4)
+#define DMA_CHUSEBURSTS_CH3SUSEBURSTS	DMA_CHUSEBURSTS_CHxSUSEBURSTS(3)
+#define DMA_CHUSEBURSTS_CH2SUSEBURSTS	DMA_CHUSEBURSTS_CHxSUSEBURSTS(2)
+#define DMA_CHUSEBURSTS_CH1SUSEBURSTS	DMA_CHUSEBURSTS_CHxSUSEBURSTS(1)
+#define DMA_CHUSEBURSTS_CH0SUSEBURSTS	DMA_CHUSEBURSTS_CHxSUSEBURSTS(0)
+
+/* DMA_CHUSEBURSTC */
+#define DMA_CHUSEBURSTC_CHxSUSEBURSTC(i)	(1 << (i))
+#define DMA_CHUSEBURSTC_CH11SUSEBURSTC	DMA_CHUSEBURSTC_CHxSUSEBURSTC(11)
+#define DMA_CHUSEBURSTC_CH10SUSEBURSTC	DMA_CHUSEBURSTC_CHxSUSEBURSTC(10)
+#define DMA_CHUSEBURSTC_CH9SUSEBURSTC	DMA_CHUSEBURSTC_CHxSUSEBURSTC(9)
+#define DMA_CHUSEBURSTC_CH8SUSEBURSTC	DMA_CHUSEBURSTC_CHxSUSEBURSTC(8)
+#define DMA_CHUSEBURSTC_CH7SUSEBURSTC	DMA_CHUSEBURSTC_CHxSUSEBURSTC(7)
+#define DMA_CHUSEBURSTC_CH6SUSEBURSTC	DMA_CHUSEBURSTC_CHxSUSEBURSTC(6)
+#define DMA_CHUSEBURSTC_CH5SUSEBURSTC	DMA_CHUSEBURSTC_CHxSUSEBURSTC(5)
+#define DMA_CHUSEBURSTC_CH4SUSEBURSTC	DMA_CHUSEBURSTC_CHxSUSEBURSTC(4)
+#define DMA_CHUSEBURSTC_CH3SUSEBURSTC	DMA_CHUSEBURSTC_CHxSUSEBURSTC(3)
+#define DMA_CHUSEBURSTC_CH2SUSEBURSTC	DMA_CHUSEBURSTC_CHxSUSEBURSTC(2)
+#define DMA_CHUSEBURSTC_CH1SUSEBURSTC	DMA_CHUSEBURSTC_CHxSUSEBURSTC(1)
+#define DMA_CHUSEBURSTC_CH0SUSEBURSTC	DMA_CHUSEBURSTC_CHxSUSEBURSTC(0)
+
+/* DMA_CHREQMASKS */
+#define DMA_CHREQMASKS_CHxSREQMASKS(i)	(1 << (i))
+#define DMA_CHREQMASKS_CH11SREQMASKS	DMA_CHREQMASKS_CHxSREQMASKS(11)
+#define DMA_CHREQMASKS_CH10SREQMASKS	DMA_CHREQMASKS_CHxSREQMASKS(10)
+#define DMA_CHREQMASKS_CH9SREQMASKS	DMA_CHREQMASKS_CHxSREQMASKS(9)
+#define DMA_CHREQMASKS_CH8SREQMASKS	DMA_CHREQMASKS_CHxSREQMASKS(8)
+#define DMA_CHREQMASKS_CH7SREQMASKS	DMA_CHREQMASKS_CHxSREQMASKS(7)
+#define DMA_CHREQMASKS_CH6SREQMASKS	DMA_CHREQMASKS_CHxSREQMASKS(6)
+#define DMA_CHREQMASKS_CH5SREQMASKS	DMA_CHREQMASKS_CHxSREQMASKS(5)
+#define DMA_CHREQMASKS_CH4SREQMASKS	DMA_CHREQMASKS_CHxSREQMASKS(4)
+#define DMA_CHREQMASKS_CH3SREQMASKS	DMA_CHREQMASKS_CHxSREQMASKS(3)
+#define DMA_CHREQMASKS_CH2SREQMASKS	DMA_CHREQMASKS_CHxSREQMASKS(2)
+#define DMA_CHREQMASKS_CH1SREQMASKS	DMA_CHREQMASKS_CHxSREQMASKS(1)
+#define DMA_CHREQMASKS_CH0SREQMASKS	DMA_CHREQMASKS_CHxSREQMASKS(0)
+
+/* DMA_CHREQMASKC */
+#define DMA_CHREQMASKC_CHxSREQMASKC(i)	(1 << (i))
+#define DMA_CHREQMASKC_CH11SREQMASKC	DMA_CHREQMASKC_CHxSREQMASKC(11)
+#define DMA_CHREQMASKC_CH10SREQMASKC	DMA_CHREQMASKC_CHxSREQMASKC(10)
+#define DMA_CHREQMASKC_CH9SREQMASKC	DMA_CHREQMASKC_CHxSREQMASKC(9)
+#define DMA_CHREQMASKC_CH8SREQMASKC	DMA_CHREQMASKC_CHxSREQMASKC(8)
+#define DMA_CHREQMASKC_CH7SREQMASKC	DMA_CHREQMASKC_CHxSREQMASKC(7)
+#define DMA_CHREQMASKC_CH6SREQMASKC	DMA_CHREQMASKC_CHxSREQMASKC(6)
+#define DMA_CHREQMASKC_CH5SREQMASKC	DMA_CHREQMASKC_CHxSREQMASKC(5)
+#define DMA_CHREQMASKC_CH4SREQMASKC	DMA_CHREQMASKC_CHxSREQMASKC(4)
+#define DMA_CHREQMASKC_CH3SREQMASKC	DMA_CHREQMASKC_CHxSREQMASKC(3)
+#define DMA_CHREQMASKC_CH2SREQMASKC	DMA_CHREQMASKC_CHxSREQMASKC(2)
+#define DMA_CHREQMASKC_CH1SREQMASKC	DMA_CHREQMASKC_CHxSREQMASKC(1)
+#define DMA_CHREQMASKC_CH0SREQMASKC	DMA_CHREQMASKC_CHxSREQMASKC(0)
+
+/* DMA_CHENS */
+#define DMA_CHENS_CHxSENS(i)		(1 << (i))
+#define DMA_CHENS_CH11SENS		DMA_CHENS_CHxSENS(11)
+#define DMA_CHENS_CH10SENS		DMA_CHENS_CHxSENS(10)
+#define DMA_CHENS_CH9SENS		DMA_CHENS_CHxSENS(9)
+#define DMA_CHENS_CH8SENS		DMA_CHENS_CHxSENS(8)
+#define DMA_CHENS_CH7SENS		DMA_CHENS_CHxSENS(7)
+#define DMA_CHENS_CH6SENS		DMA_CHENS_CHxSENS(6)
+#define DMA_CHENS_CH5SENS		DMA_CHENS_CHxSENS(5)
+#define DMA_CHENS_CH4SENS		DMA_CHENS_CHxSENS(4)
+#define DMA_CHENS_CH3SENS		DMA_CHENS_CHxSENS(3)
+#define DMA_CHENS_CH2SENS		DMA_CHENS_CHxSENS(2)
+#define DMA_CHENS_CH1SENS		DMA_CHENS_CHxSENS(1)
+#define DMA_CHENS_CH0SENS		DMA_CHENS_CHxSENS(0)
+
+/* DMA_CHENC */
+#define DMA_CHENC_CHxSENC(i)		(1 << (i))
+#define DMA_CHENC_CH11SENC		DMA_CHENC_CHxSENC(11)
+#define DMA_CHENC_CH10SENC		DMA_CHENC_CHxSENC(10)
+#define DMA_CHENC_CH9SENC		DMA_CHENC_CHxSENC(9)
+#define DMA_CHENC_CH8SENC		DMA_CHENC_CHxSENC(8)
+#define DMA_CHENC_CH7SENC		DMA_CHENC_CHxSENC(7)
+#define DMA_CHENC_CH6SENC		DMA_CHENC_CHxSENC(6)
+#define DMA_CHENC_CH5SENC		DMA_CHENC_CHxSENC(5)
+#define DMA_CHENC_CH4SENC		DMA_CHENC_CHxSENC(4)
+#define DMA_CHENC_CH3SENC		DMA_CHENC_CHxSENC(3)
+#define DMA_CHENC_CH2SENC		DMA_CHENC_CHxSENC(2)
+#define DMA_CHENC_CH1SENC		DMA_CHENC_CHxSENC(1)
+#define DMA_CHENC_CH0SENC		DMA_CHENC_CHxSENC(0)
+
+/* DMA_CHALTS */
+#define DMA_CHALTS_CHxSALTS(i)	(1 << (i))
+#define DMA_CHALTS_CH11SALTS	DMA_CHALTS_CHxSALTS(11)
+#define DMA_CHALTS_CH10SALTS	DMA_CHALTS_CHxSALTS(10)
+#define DMA_CHALTS_CH9SALTS	DMA_CHALTS_CHxSALTS(9)
+#define DMA_CHALTS_CH8SALTS	DMA_CHALTS_CHxSALTS(8)
+#define DMA_CHALTS_CH7SALTS	DMA_CHALTS_CHxSALTS(7)
+#define DMA_CHALTS_CH6SALTS	DMA_CHALTS_CHxSALTS(6)
+#define DMA_CHALTS_CH5SALTS	DMA_CHALTS_CHxSALTS(5)
+#define DMA_CHALTS_CH4SALTS	DMA_CHALTS_CHxSALTS(4)
+#define DMA_CHALTS_CH3SALTS	DMA_CHALTS_CHxSALTS(3)
+#define DMA_CHALTS_CH2SALTS	DMA_CHALTS_CHxSALTS(2)
+#define DMA_CHALTS_CH1SALTS	DMA_CHALTS_CHxSALTS(1)
+#define DMA_CHALTS_CH0SALTS	DMA_CHALTS_CHxSALTS(0)
+
+/* DMA_CHALTC */
+#define DMA_CHALTC_CHxSALTC(i)	(1 << (i))
+#define DMA_CHALTC_CH11SALTC	DMA_CHALTC_CHxSALTC(11)
+#define DMA_CHALTC_CH10SALTC	DMA_CHALTC_CHxSALTC(10)
+#define DMA_CHALTC_CH9SALTC	DMA_CHALTC_CHxSALTC(9)
+#define DMA_CHALTC_CH8SALTC	DMA_CHALTC_CHxSALTC(8)
+#define DMA_CHALTC_CH7SALTC	DMA_CHALTC_CHxSALTC(7)
+#define DMA_CHALTC_CH6SALTC	DMA_CHALTC_CHxSALTC(6)
+#define DMA_CHALTC_CH5SALTC	DMA_CHALTC_CHxSALTC(5)
+#define DMA_CHALTC_CH4SALTC	DMA_CHALTC_CHxSALTC(4)
+#define DMA_CHALTC_CH3SALTC	DMA_CHALTC_CHxSALTC(3)
+#define DMA_CHALTC_CH2SALTC	DMA_CHALTC_CHxSALTC(2)
+#define DMA_CHALTC_CH1SALTC	DMA_CHALTC_CHxSALTC(1)
+#define DMA_CHALTC_CH0SALTC	DMA_CHALTC_CHxSALTC(0)
+
+/* DMA_CHPRIS */
+#define DMA_CHPRIS_CHxSPRIC(i)	(1 << (i))
+#define DMA_CHPRIS_CH11SPRIC	DMA_CHPRIS_CHxSPRIC(11)
+#define DMA_CHPRIS_CH10SPRIC	DMA_CHPRIS_CHxSPRIC(10)
+#define DMA_CHPRIS_CH9SPRIC	DMA_CHPRIS_CHxSPRIC(9)
+#define DMA_CHPRIS_CH8SPRIC	DMA_CHPRIS_CHxSPRIC(8)
+#define DMA_CHPRIS_CH7SPRIC	DMA_CHPRIS_CHxSPRIC(7)
+#define DMA_CHPRIS_CH6SPRIC	DMA_CHPRIS_CHxSPRIC(6)
+#define DMA_CHPRIS_CH5SPRIC	DMA_CHPRIS_CHxSPRIC(5)
+#define DMA_CHPRIS_CH4SPRIC	DMA_CHPRIS_CHxSPRIC(4)
+#define DMA_CHPRIS_CH3SPRIC	DMA_CHPRIS_CHxSPRIC(3)
+#define DMA_CHPRIS_CH2SPRIC	DMA_CHPRIS_CHxSPRIC(2)
+#define DMA_CHPRIS_CH1SPRIC	DMA_CHPRIS_CHxSPRIC(1)
+#define DMA_CHPRIS_CH0SPRIC	DMA_CHPRIS_CHxSPRIC(0)
+
+/* DMA_CHPRIC */
+#define DMA_CHPRIC_CHxSPRIC(i)	(1 << (i))
+#define DMA_CHPRIC_CH11SPRIC	DMA_CHPRIC_CHxSPRIC(11)
+#define DMA_CHPRIC_CH10SPRIC	DMA_CHPRIC_CHxSPRIC(10)
+#define DMA_CHPRIC_CH9SPRIC	DMA_CHPRIC_CHxSPRIC(9)
+#define DMA_CHPRIC_CH8SPRIC	DMA_CHPRIC_CHxSPRIC(8)
+#define DMA_CHPRIC_CH7SPRIC	DMA_CHPRIC_CHxSPRIC(7)
+#define DMA_CHPRIC_CH6SPRIC	DMA_CHPRIC_CHxSPRIC(6)
+#define DMA_CHPRIC_CH5SPRIC	DMA_CHPRIC_CHxSPRIC(5)
+#define DMA_CHPRIC_CH4SPRIC	DMA_CHPRIC_CHxSPRIC(4)
+#define DMA_CHPRIC_CH3SPRIC	DMA_CHPRIC_CHxSPRIC(3)
+#define DMA_CHPRIC_CH2SPRIC	DMA_CHPRIC_CHxSPRIC(2)
+#define DMA_CHPRIC_CH1SPRIC	DMA_CHPRIC_CHxSPRIC(1)
+#define DMA_CHPRIC_CH0SPRIC	DMA_CHPRIC_CHxSPRIC(0)
+
+/* DMA_ERRORC */
+#define DMA_ERRORC_ERRORC	(1 << 0)
+
+/* DMA_CHREQSTATUS */
+#define DMA_CHREQSTATUS_CHxSREQSTATUS(i)	(1 << (i))
+#define DMA_CHREQSTATUS_CH11SREQSTATUS	DMA_CHREQSTATUS_CHxSREQSTATUS(11)
+#define DMA_CHREQSTATUS_CH10SREQSTATUS	DMA_CHREQSTATUS_CHxSREQSTATUS(10)
+#define DMA_CHREQSTATUS_CH9SREQSTATUS	DMA_CHREQSTATUS_CHxSREQSTATUS(9)
+#define DMA_CHREQSTATUS_CH8SREQSTATUS	DMA_CHREQSTATUS_CHxSREQSTATUS(8)
+#define DMA_CHREQSTATUS_CH7SREQSTATUS	DMA_CHREQSTATUS_CHxSREQSTATUS(7)
+#define DMA_CHREQSTATUS_CH6SREQSTATUS	DMA_CHREQSTATUS_CHxSREQSTATUS(6)
+#define DMA_CHREQSTATUS_CH5SREQSTATUS	DMA_CHREQSTATUS_CHxSREQSTATUS(5)
+#define DMA_CHREQSTATUS_CH4SREQSTATUS	DMA_CHREQSTATUS_CHxSREQSTATUS(4)
+#define DMA_CHREQSTATUS_CH3SREQSTATUS	DMA_CHREQSTATUS_CHxSREQSTATUS(3)
+#define DMA_CHREQSTATUS_CH2SREQSTATUS	DMA_CHREQSTATUS_CHxSREQSTATUS(2)
+#define DMA_CHREQSTATUS_CH1SREQSTATUS	DMA_CHREQSTATUS_CHxSREQSTATUS(1)
+#define DMA_CHREQSTATUS_CH0SREQSTATUS	DMA_CHREQSTATUS_CHxSREQSTATUS(0)
+
+/* DMA_CHSREQSTATUS */
+#define DMA_CHSREQSTATUS_CHxSREQSTATUS(i)	(1 << (i))
+#define DMA_CHSREQSTATUS_CH11SREQSTATUS	DMA_CHSREQSTATUS_CHxSREQSTATUS(11)
+#define DMA_CHSREQSTATUS_CH10SREQSTATUS	DMA_CHSREQSTATUS_CHxSREQSTATUS(10)
+#define DMA_CHSREQSTATUS_CH9SREQSTATUS	DMA_CHSREQSTATUS_CHxSREQSTATUS(9)
+#define DMA_CHSREQSTATUS_CH8SREQSTATUS	DMA_CHSREQSTATUS_CHxSREQSTATUS(8)
+#define DMA_CHSREQSTATUS_CH7SREQSTATUS	DMA_CHSREQSTATUS_CHxSREQSTATUS(7)
+#define DMA_CHSREQSTATUS_CH6SREQSTATUS	DMA_CHSREQSTATUS_CHxSREQSTATUS(6)
+#define DMA_CHSREQSTATUS_CH5SREQSTATUS	DMA_CHSREQSTATUS_CHxSREQSTATUS(5)
+#define DMA_CHSREQSTATUS_CH4SREQSTATUS	DMA_CHSREQSTATUS_CHxSREQSTATUS(4)
+#define DMA_CHSREQSTATUS_CH3SREQSTATUS	DMA_CHSREQSTATUS_CHxSREQSTATUS(3)
+#define DMA_CHSREQSTATUS_CH2SREQSTATUS	DMA_CHSREQSTATUS_CHxSREQSTATUS(2)
+#define DMA_CHSREQSTATUS_CH1SREQSTATUS	DMA_CHSREQSTATUS_CHxSREQSTATUS(1)
+#define DMA_CHSREQSTATUS_CH0SREQSTATUS	DMA_CHSREQSTATUS_CHxSREQSTATUS(0)
+
+/* DMA_IF */
+#define DMA_IF_ERR		(1UL << 31)
+#define DMA_IF_CHxDONE(x)	(1 << (x))
+#define DMA_IF_CH11DONE		DMA_IF_CHxDONE(11)
+#define DMA_IF_CH10DONE		DMA_IF_CHxDONE(10)
+#define DMA_IF_CH9DONE		DMA_IF_CHxDONE(9)
+#define DMA_IF_CH8DONE		DMA_IF_CHxDONE(8)
+#define DMA_IF_CH7DONE		DMA_IF_CHxDONE(7)
+#define DMA_IF_CH6DONE		DMA_IF_CHxDONE(6)
+#define DMA_IF_CH5DONE		DMA_IF_CHxDONE(5)
+#define DMA_IF_CH4DONE		DMA_IF_CHxDONE(4)
+#define DMA_IF_CH3DONE		DMA_IF_CHxDONE(3)
+#define DMA_IF_CH2DONE		DMA_IF_CHxDONE(2)
+#define DMA_IF_CH1DONE		DMA_IF_CHxDONE(1)
+#define DMA_IF_CH0DONE		DMA_IF_CHxDONE(0)
+
+
+/* DMA_IFS */
+#define DMA_IFS_ERR		(1 << 31)
+#define DMA_IFS_CHxDONE(x)	(1 << (x))
+#define DMA_IFS_CH11DONE	DMA_IFS_CHxDONE(11)
+#define DMA_IFS_CH10DONE	DMA_IFS_CHxDONE(10)
+#define DMA_IFS_CH9DONE		DMA_IFS_CHxDONE(9)
+#define DMA_IFS_CH8DONE		DMA_IFS_CHxDONE(8)
+#define DMA_IFS_CH7DONE		DMA_IFS_CHxDONE(7)
+#define DMA_IFS_CH6DONE		DMA_IFS_CHxDONE(6)
+#define DMA_IFS_CH5DONE		DMA_IFS_CHxDONE(5)
+#define DMA_IFS_CH4DONE		DMA_IFS_CHxDONE(4)
+#define DMA_IFS_CH3DONE		DMA_IFS_CHxDONE(3)
+#define DMA_IFS_CH2DONE		DMA_IFS_CHxDONE(2)
+#define DMA_IFS_CH1DONE		DMA_IFS_CHxDONE(1)
+#define DMA_IFS_CH0DONE		DMA_IFS_CHxDONE(0)
+
+/* DMA_IFC */
+#define DMA_IFC_ERR		(1 << 31)
+#define DMA_IFC_CHxDONE(x)	(1 << (x))
+#define DMA_IFC_CH11DONE	DMA_IFC_CHxDONE(11)
+#define DMA_IFC_CH10DONE	DMA_IFC_CHxDONE(10)
+#define DMA_IFC_CH9DONE		DMA_IFC_CHxDONE(9)
+#define DMA_IFC_CH8DONE		DMA_IFC_CHxDONE(8)
+#define DMA_IFC_CH7DONE		DMA_IFC_CHxDONE(7)
+#define DMA_IFC_CH6DONE		DMA_IFC_CHxDONE(6)
+#define DMA_IFC_CH5DONE		DMA_IFC_CHxDONE(5)
+#define DMA_IFC_CH4DONE		DMA_IFC_CHxDONE(4)
+#define DMA_IFC_CH3DONE		DMA_IFC_CHxDONE(3)
+#define DMA_IFC_CH2DONE		DMA_IFC_CHxDONE(2)
+#define DMA_IFC_CH1DONE		DMA_IFC_CHxDONE(1)
+#define DMA_IFC_CH0DONE		DMA_IFC_CHxDONE(0)
+
+/* DMA_IEN */
+#define DMA_IEN_ERR		(1 << 31)
+#define DMA_IEN_CHxDONE(x)	(1 << (x))
+#define DMA_IEN_CH11DONE	DMA_IEN_CHxDONE(11)
+#define DMA_IEN_CH10DONE	DMA_IEN_CHxDONE(10)
+#define DMA_IEN_CH9DONE		DMA_IEN_CHxDONE(9)
+#define DMA_IEN_CH8DONE		DMA_IEN_CHxDONE(8)
+#define DMA_IEN_CH7DONE		DMA_IEN_CHxDONE(7)
+#define DMA_IEN_CH6DONE		DMA_IEN_CHxDONE(6)
+#define DMA_IEN_CH5DONE		DMA_IEN_CHxDONE(5)
+#define DMA_IEN_CH4DONE		DMA_IEN_CHxDONE(4)
+#define DMA_IEN_CH3DONE		DMA_IEN_CHxDONE(3)
+#define DMA_IEN_CH2DONE		DMA_IEN_CHxDONE(2)
+#define DMA_IEN_CH1DONE		DMA_IEN_CHxDONE(1)
+#define DMA_IEN_CH0DONE		DMA_IEN_CHxDONE(0)
+
+/* DMA_CTRL */
+#define DMA_CTRL_PRDU		(1 << 1)
+#define DMA_CTRL_DESCRECT	(1 << 0)
+
+/* DMA_RDS */
+#define DMA_RDS_RDSCHx(i)	(1 << (i))
+#define DMA_RDS_RDSCH11		DMA_RDS_RDSCHx(11)
+#define DMA_RDS_RDSCH10		DMA_RDS_RDSCHx(10)
+#define DMA_RDS_RDSCH9		DMA_RDS_RDSCHx(9)
+#define DMA_RDS_RDSCH8		DMA_RDS_RDSCHx(8)
+#define DMA_RDS_RDSCH7		DMA_RDS_RDSCHx(7)
+#define DMA_RDS_RDSCH6		DMA_RDS_RDSCHx(6)
+#define DMA_RDS_RDSCH5		DMA_RDS_RDSCHx(5)
+#define DMA_RDS_RDSCH4		DMA_RDS_RDSCHx(4)
+#define DMA_RDS_RDSCH3		DMA_RDS_RDSCHx(3)
+#define DMA_RDS_RDSCH2		DMA_RDS_RDSCHx(2)
+#define DMA_RDS_RDSCH1		DMA_RDS_RDSCHx(1)
+#define DMA_RDS_RDSCH0		DMA_RDS_RDSCHx(0)
+
+/* DMA_LOOP */
+#define DMA_LOOP_EN		(1 << 16)
+#define DMA_LOOP_WIDTH_SHIFT	(0)
+#define DMA_LOOP_WIDTH_MASK	(0x3FF << DMA_LOOP_WIDTH_SHIFT)
+#define DMA_LOOP_WIDTH(v)	\
+	(((v) << DMA_LOOP_WIDTH_SHIFT) & DMA_LOOP_WIDTH_MASK)
+
+/* DMA_RECT */
+#define DMA_RECT_DSTSTRIDE_SHIFT	(21)
+#define DMA_RECT_DSTSTRIDE_MASK		(0x7FF << DMA_RECT_DSTSTRIDE_SHIFT)
+#define DMA_RECT_DSTSTRIDE(v)		\
+	(((v) << DMA_RECT_DSTSTRIDE_SHIFT) & DMA_RECT_DSTSTRIDE_MASK)
+
+#define DMA_RECT_SRCSTRIDE_SHIFT	(10)
+#define DMA_RECT_SRCSTRIDE_MASK		(0x7FF << DMA_RECT_SRCSTRIDE_SHIFT)
+#define DMA_RECT_SRCSTRIDE(v)		\
+	(((v) << DMA_RECT_SRCSTRIDE_SHIFT) & DMA_RECT_SRCSTRIDE_MASK)
+
+#define DMA_RECT_HEIGHT_SHIFT		(0)
+#define DMA_RECT_HEIGHT_MASK		(0x3FF << DMA_RECT_HEIGHT_SHIFT)
+#define DMA_RECT_HEIGHT(v)		\
+			(((v) << DMA_RECT_HEIGHT_SHIFT) & DMA_RECT_HEIGHT_MASK)
+
+/* DMA_CH_CTRL */
+#define DMA_CH_CTRL_SOURCESEL_SHIFT	(16)
+#define DMA_CH_CTRL_SOURCESEL_MASK	(0x3F << DMA_CH_CTRL_SOURCESEL_SHIFT)
+#define DMA_CH_CTRL_SOURCESEL(v)	\
+	(((v) << DMA_CH_CTRL_SOURCESEL_SHIFT) & DMA_CH_CTRL_SOURCESEL_MASK)
+#define DMA_CH_CTRL_SOURCESEL_NONE	0b000000
+#define DMA_CH_CTRL_SOURCESEL_ADC0	0b001000
+#define DMA_CH_CTRL_SOURCESEL_DAC0	0b001010
+#define DMA_CH_CTRL_SOURCESEL_USART0	0b001100
+#define DMA_CH_CTRL_SOURCESEL_USART1	0b001101
+#define DMA_CH_CTRL_SOURCESEL_USART2	0b001110
+#define DMA_CH_CTRL_SOURCESEL_LEUART0	0b010000
+#define DMA_CH_CTRL_SOURCESEL_LEUART1	0b010001
+#define DMA_CH_CTRL_SOURCESEL_I2C0	0b010100
+#define DMA_CH_CTRL_SOURCESEL_I2C1	0b010101
+#define DMA_CH_CTRL_SOURCESEL_TIMER0	0b011000
+#define DMA_CH_CTRL_SOURCESEL_TIMER1	0b011001
+#define DMA_CH_CTRL_SOURCESEL_TIMER2	0b011010
+#define DMA_CH_CTRL_SOURCESEL_TIMER3	0b011011
+#define DMA_CH_CTRL_SOURCESEL_UART0	0b101100
+#define DMA_CH_CTRL_SOURCESEL_UART1	0b101101
+#define DMA_CH_CTRL_SOURCESEL_MSC	0b110000
+#define DMA_CH_CTRL_SOURCESEL_AES	0b110001
+#define DMA_CH_CTRL_SOURCESEL_LESENSE	0b110010
+#define DMA_CH_CTRL_SOURCESEL_EBI	0b110011
+
+#define DMA_CH_CTRL_SIGSEL_SHIFT	(0)
+#define DMA_CH_CTRL_SIGSEL_MASK		(0xF << DMA_CH_CTRL_SIGSEL_SHIFT)
+#define DMA_CH_CTRL_SIGSEL(v)		\
+	(((v) << DMA_CH_CTRL_SIGSEL_SHIFT) & DMA_CH_CTRL_SIGSEL_MASK)
+
+#define DMA_CH_CTRL_SIGSEL_OFF			0
+#define DMA_CH_CTRL_SIGSEL_ADC0SINGLE		0
+#define DMA_CH_CTRL_SIGSEL_ADC0SCAN		1
+#define DMA_CH_CTRL_SIGSEL_DAC0CH0		0
+#define DMA_CH_CTRL_SIGSEL_DAC0CH1		1
+#define DMA_CH_CTRL_SIGSEL_USART0RXDATAV	0
+#define DMA_CH_CTRL_SIGSEL_USART0TXBL		1
+#define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY	2
+#define DMA_CH_CTRL_SIGSEL_USART1RXDATAV	0
+#define DMA_CH_CTRL_SIGSEL_USART1TXBL		1
+#define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY	2
+#define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT	3
+#define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT	4
+#define DMA_CH_CTRL_SIGSEL_USART2RXDATAV	0
+#define DMA_CH_CTRL_SIGSEL_USART2TXBL		1
+#define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY	2
+#define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT	3
+#define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT	4
+#define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV	0
+#define DMA_CH_CTRL_SIGSEL_LEUART0TXBL		1
+#define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY	2
+#define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV	0
+#define DMA_CH_CTRL_SIGSEL_LEUART1TXBL		1
+#define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY	2
+#define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV		0
+#define DMA_CH_CTRL_SIGSEL_I2C0TXBL		1
+#define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV		0
+#define DMA_CH_CTRL_SIGSEL_I2C1TXBL		1
+#define DMA_CH_CTRL_SIGSEL_TIMER0UFOF		0
+#define DMA_CH_CTRL_SIGSEL_TIMER0CC0		1
+#define DMA_CH_CTRL_SIGSEL_TIMER0CC1		2
+#define DMA_CH_CTRL_SIGSEL_TIMER0CC2		3
+#define DMA_CH_CTRL_SIGSEL_TIMER1UFOF		0
+#define DMA_CH_CTRL_SIGSEL_TIMER1CC0		1
+#define DMA_CH_CTRL_SIGSEL_TIMER1CC1		2
+#define DMA_CH_CTRL_SIGSEL_TIMER1CC2		3
+#define DMA_CH_CTRL_SIGSEL_TIMER2UFOF		0
+#define DMA_CH_CTRL_SIGSEL_TIMER2CC0		1
+#define DMA_CH_CTRL_SIGSEL_TIMER2CC1		2
+#define DMA_CH_CTRL_SIGSEL_TIMER2CC2		3
+#define DMA_CH_CTRL_SIGSEL_TIMER3UFOF		0
+#define DMA_CH_CTRL_SIGSEL_TIMER3CC0		1
+#define DMA_CH_CTRL_SIGSEL_TIMER3CC1		2
+#define DMA_CH_CTRL_SIGSEL_TIMER3CC2		3
+#define DMA_CH_CTRL_SIGSEL_UART0RXDATAV		0
+#define DMA_CH_CTRL_SIGSEL_UART0TXBL		1
+#define DMA_CH_CTRL_SIGSEL_UART0TXEMPTY		2
+#define DMA_CH_CTRL_SIGSEL_UART1RXDATAV		0
+#define DMA_CH_CTRL_SIGSEL_UART1TXBL		1
+#define DMA_CH_CTRL_SIGSEL_UART1TXEMPTY		2
+#define DMA_CH_CTRL_SIGSEL_MSCWDATA		0
+#define DMA_CH_CTRL_SIGSEL_AESDATAWR		0
+#define DMA_CH_CTRL_SIGSEL_AESXORDATAWR		1
+#define DMA_CH_CTRL_SIGSEL_AESDATARD		2
+#define DMA_CH_CTRL_SIGSEL_AESKEYWR		3
+#define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV	0
+#define DMA_CH_CTRL_SIGSEL_EBIPXL0EMPTY		0
+#define DMA_CH_CTRL_SIGSEL_EBIPXL1EMPTY		1
+#define DMA_CH_CTRL_SIGSEL_EBIPXLFULL		2
+#define DMA_CH_CTRL_SIGSEL_EBIDDEMPTY		3
+
+/* generic of above */
+#define DMA_CH_CTRL_SIGSEL_ADC_SINGLE		0
+#define DMA_CH_CTRL_SIGSEL_ADC_SCAN		1
+#define DMA_CH_CTRL_SIGSEL_DAC_CHx(x)		DMA_CH_CTRL_SIGSEL(x)
+#define DMA_CH_CTRL_SIGSEL_DAC_CH0		0
+#define DMA_CH_CTRL_SIGSEL_DAC_CH1		1
+#define DMA_CH_CTRL_SIGSEL_USART_RXDATAV	0
+#define DMA_CH_CTRL_SIGSEL_USART_TXBL		1
+#define DMA_CH_CTRL_SIGSEL_USART_TXEMPTY	2
+#define DMA_CH_CTRL_SIGSEL_USART_RXDATAVRIGHT	3
+#define DMA_CH_CTRL_SIGSEL_USART_TXBLRIGHT	4
+#define DMA_CH_CTRL_SIGSEL_LEUART_RXDATAV	0
+#define DMA_CH_CTRL_SIGSEL_LEUART_TXBL		1
+#define DMA_CH_CTRL_SIGSEL_LEUART_TXEMPTY	2
+#define DMA_CH_CTRL_SIGSEL_I2C_RXDATAV		0
+#define DMA_CH_CTRL_SIGSEL_I2C_TXBL		1
+#define DMA_CH_CTRL_SIGSEL_I2C_RXDATAV		0
+#define DMA_CH_CTRL_SIGSEL_I2C_TXBL		1
+#define DMA_CH_CTRL_SIGSEL_TIMER_UFOF		0
+#define DMA_CH_CTRL_SIGSEL_TIMER_CCx(x)		DMA_CH_CTRL_SIGSEL((x) + 1)
+#define DMA_CH_CTRL_SIGSEL_TIMER_CC0		DMA_CH_CTRL_SIGSEL_TIMER_CCx(0)
+#define DMA_CH_CTRL_SIGSEL_TIMER_CC1		DMA_CH_CTRL_SIGSEL_TIMER_CCx(1)
+#define DMA_CH_CTRL_SIGSEL_TIMER_CC2		DMA_CH_CTRL_SIGSEL_TIMER_CCx(3)
+#define DMA_CH_CTRL_SIGSEL_UART_RXDATAV		0
+#define DMA_CH_CTRL_SIGSEL_UART_TXBL		1
+#define DMA_CH_CTRL_SIGSEL_UART_TXEMPTY		2
+#define DMA_CH_CTRL_SIGSEL_MSC_WDATA		0
+#define DMA_CH_CTRL_SIGSEL_AES_DATA_WR		0
+#define DMA_CH_CTRL_SIGSEL_AES_XOR_DATA_WR	1
+#define DMA_CH_CTRL_SIGSEL_AES_DATA_RD		2
+#define DMA_CH_CTRL_SIGSEL_AES_KEY_WR		3
+#define DMA_CH_CTRL_SIGSEL_LESENSE_BUF_DATAV	0
+#define DMA_CH_CTRL_SIGSEL_EBI_PXLx_EMPTY(x)	DMA_CH_CTRL_SIGSEL(x)
+#define DMA_CH_CTRL_SIGSEL_EBI_PXL0_EMPTY	\
+	0
+#define DMA_CH_CTRL_SIGSEL_EBI_PXL1_EMPTY	\
+	1
+#define DMA_CH_CTRL_SIGSEL_EBI_PXL_FULL		2
+#define DMA_CH_CTRL_SIGSEL_EBI_DD_EMPTY		3
+
+/**
+ * Application needs to allocate (DMA_DESC_CH_SIZE * N) byte
+ *   where N is the number of first N channels to use.
+ * and this allocated memory needs to be assigned to DMA using
+ *   dma_set_desc_address().
+ *
+ * if the application code needs alternate descriptor facility also.
+ *   it needs to allocate the required memory (usually equal to the one above)
+ *  and assign the memory using dma_set_alternate_desc_address()
+ *
+ * rest of the work will be transparently managed by convience functions.
+ *
+ * all the memory above should be aligned to 256bit
+ *   (ie LSB 8bits of array address should be 0)
+ *  use gcc's __attribute__((aligned(256)))
+ */
+#define DMA_DESC_CH_SIZE			(0x4 * 0x4)
+#define DMA_DESC_CHx_BASE(base, x)		\
+	((base) + ((x) * DMA_DESC_CH_SIZE))
+#define DMA_DESC_CHx_SRC_DATA_END_PTR(base, x)	\
+	MMIO32(DMA_DESC_CHx_BASE(base, x) + 0x00)
+#define DMA_DESC_CHx_DEST_DATA_END_PTR(base, x)	\
+	MMIO32(DMA_DESC_CHx_BASE(base, x) + 0x04)
+#define DMA_DESC_CHx_CFG(base, x)		\
+	MMIO32(DMA_DESC_CHx_BASE(base, x) + 0x08)
+#define DMA_DESC_CHx_USER_DATA(base, x)		\
+	MMIO32(DMA_DESC_CHx_BASE(base, x) + 0x0C)
+
+/* DMA_DESC_CH_CFG */
+#define DMA_DESC_CH_CFG_DEST_INC_SHIFT		(30)
+#define DMA_DESC_CH_CFG_DEST_INC_MASK		\
+	(0x3 << DMA_DESC_CH_CFG_DEST_INC_SHIFT)
+#define DMA_DESC_CH_CFG_DEST_INC(v)		\
+	(((v) << DMA_DESC_CH_CFG_DEST_INC_SHIFT) &	\
+	DMA_DESC_CH_CFG_DEST_INC_MASK)
+#define DMA_DESC_CH_CFG_DEST_INC_BYTE		DMA_DESC_CH_CFG_DEST_INC(0)
+#define DMA_DESC_CH_CFG_DEST_INC_HALFWORD	DMA_DESC_CH_CFG_DEST_INC(1)
+#define DMA_DESC_CH_CFG_DEST_INC_WORD		DMA_DESC_CH_CFG_DEST_INC(2)
+#define DMA_DESC_CH_CFG_DEST_INC_NOINC		DMA_DESC_CH_CFG_DEST_INC(3)
+
+#define DMA_DESC_CH_CFG_DEST_SIZE_SHIFT			(28)
+#define DMA_DESC_CH_CFG_DEST_SIZE_MASK		\
+	(0x3 << DMA_DESC_CH_CFG_DEST_SIZE_SHIFT)
+#define DMA_DESC_CH_CFG_DEST_SIZE(v)		\
+	(((v) << DMA_DESC_CH_CFG_DEST_SIZE_SHIFT) &	\
+	DMA_DESC_CH_CFG_DEST_SIZE_MASK)
+#define DMA_DESC_CH_CFG_DEST_SIZE_BYTE		DMA_DESC_CH_CFG_DEST_SIZE(0)
+#define DMA_DESC_CH_CFG_DEST_SIZE_HALFWORD	DMA_DESC_CH_CFG_DEST_SIZE(1)
+#define DMA_DESC_CH_CFG_DEST_SIZE_WORD		DMA_DESC_CH_CFG_DEST_SIZE(2)
+#define DMA_DESC_CH_CFG_DEST_SIZE_NOINC		DMA_DESC_CH_CFG_DEST_SIZE(3)
+
+#define DMA_DESC_CH_CFG_SRC_INC_SHIFT		(26)
+#define DMA_DESC_CH_CFG_SRC_INC_MASK		\
+	(0x3 << DMA_DESC_CH_CFG_SRC_INC_SHIFT)
+#define DMA_DESC_CH_CFG_SRC_INC(v)		\
+	(((v) << DMA_DESC_CH_CFG_SRC_INC_SHIFT) &	\
+	DMA_DESC_CH_CFG_SRC_INC_MASK)
+#define DMA_DESC_CH_CFG_SRC_INC_BYTE		DMA_DESC_CH_CFG_SRC_INC(0)
+#define DMA_DESC_CH_CFG_SRC_INC_HALFWORD	DMA_DESC_CH_CFG_SRC_INC(1)
+#define DMA_DESC_CH_CFG_SRC_INC_WORD		DMA_DESC_CH_CFG_SRC_INC(2)
+#define DMA_DESC_CH_CFG_SRC_INC_NOINC		DMA_DESC_CH_CFG_SRC_INC(3)
+
+#define DMA_DESC_CH_CFG_SRC_SIZE_SHIFT		(24)
+#define DMA_DESC_CH_CFG_SRC_SIZE_MASK		\
+	(0x3 << DMA_DESC_CH_CFG_SRC_SIZE_SHIFT)
+#define DMA_DESC_CH_CFG_SRC_SIZE(v)		\
+	(((v) << DMA_DESC_CH_CFG_SRC_SIZE_SHIFT) &	\
+	DMA_DESC_CH_CFG_SRC_SIZE_MASK)
+#define DMA_DESC_CH_CFG_SRC_SIZE_BYTE		DMA_DESC_CH_CFG_SRC_SIZE(0)
+#define DMA_DESC_CH_CFG_SRC_SIZE_HALFWORD	DMA_DESC_CH_CFG_SRC_SIZE(1)
+#define DMA_DESC_CH_CFG_SRC_SIZE_WORD		DMA_DESC_CH_CFG_SRC_SIZE(2)
+#define DMA_DESC_CH_CFG_SRC_SIZE_NOINC		DMA_DESC_CH_CFG_SRC_SIZE(3)
+
+#define DMA_DESC_CH_CFG_R_POWER_SHIFT		(14)
+#define DMA_DESC_CH_CFG_R_POWER_MASK		\
+	(0xF << DMA_DESC_CH_CFG_R_POWER_SHIFT)
+#define DMA_DESC_CH_CFG_R_POWER(v)			\
+	(((v) << DMA_DESC_CH_CFG_R_POWER_SHIFT) &	\
+	DMA_DESC_CH_CFG_R_POWER_MASK)
+
+#define DMA_DESC_CH_CFG_CYCLE_CTRL_SHIFT	(0)
+#define DMA_DESC_CH_CFG_CYCLE_CTRL_MASK		\
+	(0x7 << DMA_DESC_CH_CFG_CYCLE_CTRL_SHIFT)
+#define DMA_DESC_CH_CFG_CYCLE_CTRL(v)		\
+	(((v) << DMA_DESC_CH_CFG_CYCLE_CTRL_SHIFT) &	\
+	DMA_DESC_CH_CFG_CYCLE_CTRL_MASK)
+#define DMA_DESC_CH_CFG_CYCLE_CTRL_INVALD		\
+	DMA_DESC_CH_CFG_CYCLE_CTRL(0)
+#define DMA_DESC_CH_CFG_CYCLE_CTRL_BASIC		\
+	DMA_DESC_CH_CFG_CYCLE_CTRL(1)
+#define DMA_DESC_CH_CFG_CYCLE_CTRL_AUTOREQUEST		\
+	DMA_DESC_CH_CFG_CYCLE_CTRL(2)
+#define DMA_DESC_CH_CFG_CYCLE_CTRL_PINGPONG		\
+	DMA_DESC_CH_CFG_CYCLE_CTRL(3)
+#define DMA_DESC_CH_CFG_CYCLE_CTRL_MEM_SCAT_GATH_PRIM	\
+	DMA_DESC_CH_CFG_CYCLE_CTRL(4)
+#define DMA_DESC_CH_CFG_CYCLE_CTRL_MEM_SCAT_GATH_ALT	\
+	DMA_DESC_CH_CFG_CYCLE_CTRL(5)
+#define DMA_DESC_CH_CFG_CYCLE_CTRL_PERIPH_SCAT_GATH_PRIM	\
+	DMA_DESC_CH_CFG_CYCLE_CTRL(6)
+#define DMA_DESC_CH_CFG_CYCLE_CTRL_PERIPH_SCAT_GATH_ALT	\
+	DMA_DESC_CH_CFG_CYCLE_CTRL(7)
+
+#define DMA_DESC_CH_CFG_DEST_PROT_CTRL_SHIFT	(21)
+#define DMA_DESC_CH_CFG_DEST_PROT_CTRL_MASK	\
+	(0x7 << DMA_DESC_CH_CFG_DEST_PROT_CTRL_SHIFT)
+#define DMA_DESC_CH_CFG_DEST_PROT_CTRL(v)	\
+	(((v) << DMA_DESC_CH_CFG_DEST_PROT_CTRL_SHIFT) &	\
+	DMA_DESC_CH_CFG_DEST_PROT_CTRL_MASK)
+
+#define DMA_DESC_CH_CFG_SRC_PROT_CTRL_SHIFT	(18)
+#define DMA_DESC_CH_CFG_SRC_PROT_CTRL_MASK	\
+	(0x7 << DMA_DESC_CH_CFG_SRC_PROT_CTRL_SHIFT)
+#define DMA_DESC_CH_CFG_SRC_PROT_CTRL(v)	\
+	(((v) << DMA_DESC_CH_CFG_SRC_PROT_CTRL_SHIFT) &	\
+	DMA_DESC_CH_CFG_SRC_PROT_CTRL_SHIFT)
+
+#define DMA_DESC_CH_CFG_N_MINUS_1_SHIFT		(4)
+#define DMA_DESC_CH_CFG_N_MINUS_1_MASK		\
+	(0x3FF << DMA_DESC_CH_CFG_N_MINUS_1_SHIFT)
+#define DMA_DESC_CH_CFG_N_MINUS_1(v)		\
+	(((v) << DMA_DESC_CH_CFG_N_MINUS_1_SHIFT) &	\
+	DMA_DESC_CH_CFG_N_MINUS_1_MASK)
+
+#define DMA_DESC_CH_CFG_NEXT_USEBURST		(1 << 3)
+
+/* DMA Channel Descriptor in structure style */
+struct dma_chan_desc {
+	uint32_t src_data_end_ptr;
+	uint32_t dst_data_end_ptr;
+	uint32_t cfg;
+	uint32_t user_data;
+} __attribute__((packed));
+
+/** @defgroup dma_ch DMA Channel Number
+@ingroup dma_defines
+
+@{*/
+enum dma_ch {
+	DMA_CH0 = 0,
+	DMA_CH1,
+	DMA_CH2,
+	DMA_CH3,
+	DMA_CH4,
+	DMA_CH5,
+	DMA_CH6,
+	DMA_CH7,
+	DMA_CH8,
+	DMA_CH9,
+	DMA_CH10,
+	DMA_CH11
+};
+/**@}*/
+
+/* API version for {src, dest} * {size, inc} */
+enum dma_mem {
+	DMA_MEM_BYTE = 0,
+	DMA_MEM_HALF_WORD,
+	DMA_MEM_WORD,
+	DMA_MEM_NONE
+};
+
+/* API version of DMA_DESC_CH_CFG_CYCLE_CTRL_* */
+enum dma_mode {
+	DMA_MODE_INVALID = 0,
+	DMA_MODE_BASIC,
+	DMA_MODE_AUTO_REQUEST,
+	DMA_MODE_PING_PONG,
+	DMA_MODE_MEM_SCAT_GATH_PRIM,
+	DMA_MODE_MEM_SCAT_GATH_ALT,
+	DMA_MODE_PERIPH_SCAT_GATH_PRIM,
+	DMA_MODE_PERIPH_SCAT_GATH_ALT,
+};
+
+/* API version of DMA_DESC_CH_CFG_R_POWER() */
+enum dma_r_power {
+	DMA_R_POWER_1 = 0,
+	DMA_R_POWER_2,
+	DMA_R_POWER_4,
+	DMA_R_POWER_8,
+	DMA_R_POWER_16,
+	DMA_R_POWER_32,
+	DMA_R_POWER_64,
+	DMA_R_POWER_128,
+	DMA_R_POWER_256,
+	DMA_R_POWER_512,
+	DMA_R_POWER_1024
+};
+
+BEGIN_DECLS
+
+void dma_enable(void);
+void dma_disable(void);
+
+bool dma_get_wait_on_request_flag(enum dma_ch ch);
+
+/*bool dma_get_wait_flag(enum dma_ch ch);*/
+
+void dma_enable_with_unprivileged_access(void);
+void dma_enable_with_privileged_access(void);
+
+void dma_set_desc_address(uint32_t desc_base);
+
+void dma_generate_software_request(enum dma_ch ch);
+
+void dma_enable_burst_only(enum dma_ch ch);
+void dma_enable_single_and_burst(enum dma_ch ch);
+
+void dma_enable_periph_request(enum dma_ch ch);
+void dma_disable_periph_request(enum dma_ch ch);
+
+void dma_enable_channel(enum dma_ch ch);
+void dma_disable_channel(enum dma_ch ch);
+
+void dma_disable_alternate_structure(enum dma_ch ch);
+void dma_enable_alternate_structure(enum dma_ch ch);
+
+void dma_enable_priority(enum dma_ch ch);
+void dma_disable_priority(enum dma_ch ch);
+
+bool dma_get_bus_error_flag(void);
+void dma_clear_bus_error_flag(void);
+
+bool dma_get_request_flag(enum dma_ch ch);
+
+/*bool dma_get_single_request_flag(enum dma_ch ch);*/
+
+bool dma_get_bus_error_interrupt_flag(void);
+bool dma_get_done_interrupt_flag(enum dma_ch ch);
+
+void dma_set_bus_error_interrupt_flag(void);
+void dma_set_done_interrupt_flag(enum dma_ch ch);
+
+void dma_clear_bus_error_interrupt_flag(void);
+void dma_clear_done_interrupt_flag(enum dma_ch ch);
+
+void dma_enable_bus_error_interrupt(void);
+void dma_disable_bus_error_interrupt(void);
+void dma_enable_done_interrupt(enum dma_ch ch);
+void dma_disable_done_interrupt(enum dma_ch ch);
+
+/* TODO: DMA_CTRL, DMA_RDS, DMA_LOOP0, DMA_LOOP1, DMA_RECT0 */
+
+void dma_set_source(enum dma_ch ch, uint32_t source);
+void dma_set_signal(enum dma_ch ch, uint32_t signal);
+
+void dma_channel_reset(enum dma_ch ch);
+
+void dma_set_loop_count(enum dma_ch ch, uint16_t count);
+void dma_enable_loop(enum dma_ch ch);
+void dma_disable_loop(enum dma_ch ch);
+
+/* descriptor convient function. (prefix "dma_desc_") */
+void dma_desc_set_dest_size(uint32_t desc_base, enum dma_ch ch,
+		enum dma_mem size);
+void dma_desc_set_dest_inc(uint32_t desc_base, enum dma_ch ch,
+		enum dma_mem inc);
+void dma_desc_set_src_size(uint32_t desc_base, enum dma_ch ch,
+		enum dma_mem size);
+void dma_desc_set_src_inc(uint32_t desc_base, enum dma_ch ch,
+		enum dma_mem inc);
+
+void dma_desc_set_r_power(uint32_t desc_base, enum dma_ch ch,
+		enum dma_r_power r_power);
+
+void dma_desc_enable_next_useburst(uint32_t desc_base, enum dma_ch ch);
+void dma_desc_disable_next_useburst(uint32_t desc_base, enum dma_ch ch);
+
+void dma_desc_set_count(uint32_t desc_base, enum dma_ch ch, uint16_t count);
+
+void dma_desc_set_user_data(uint32_t desc_base, enum dma_ch ch,
+		uint32_t user_data);
+uint32_t dma_desc_get_user_data(uint32_t desc_base, enum dma_ch ch);
+
+void dma_desc_set_src_address(uint32_t desc_base, enum dma_ch ch,
+		uint32_t src);
+void dma_desc_set_dest_address(uint32_t desc_base, enum dma_ch ch,
+		uint32_t dest);
+
+void dma_desc_set_mode(uint32_t desc_base, enum dma_ch ch, enum dma_mode mode);
+
+/* based on descriptor convient, macro are passing
+ *  {DMA_CTRLBASE, CTRL_ALTCTRLBASE} as per naming */
+#define dma_set_dest_size(ch, size)	\
+	dma_desc_set_dest_size(DMA_CTRLBASE, ch, size)
+#define dma_set_dest_inc(ch, inc)	\
+	dma_desc_set_dest_inc(DMA_CTRLBASE, ch, inc)
+#define dma_set_src_size(ch, size)	\
+	dma_desc_set_src_size(DMA_CTRLBASE, ch, size)
+#define dma_set_src_inc(ch, inc)	\
+	dma_desc_set_src_inc(DMA_CTRLBASE, ch, inc)
+
+#define dma_set_alt_dest_size(ch, size)	\
+	dma_desc_set_dest_size(DMA_ALTCTRLBASE, ch, size)
+#define dma_set_alt_dest_inc(ch, inc)	\
+	dma_desc_set_dest_inc(DMA_ALTCTRLBASE, ch, inc)
+#define dma_set_alt_src_size(ch, size)	\
+	dma_desc_set_src_size(DMA_ALTCTRLBASE, ch, size)
+#define dma_set_alt_src_inc(ch, inc)	\
+	dma_desc_set_src_inc(DMA_ALTCTRLBASE, ch, inc)
+
+#define dma_set_r_power(ch, r_power)				\
+			dma_desc_set_r_power(DMA_CTRLBASE, ch, r_power)
+#define dma_set_alt_r_power(ch, r_power)			\
+			dma_desc_set_r_power(DMA_ALTCTRLBASE, ch, r_power)
+
+#define dma_enable_next_useburst(ch)				\
+			dma_desc_enable_next_useburst(DMA_CTRLBASE, ch)
+#define dma_disable_next_useburst(ch)				\
+			dma_desc_disable_next_useburst(DMA_CTRLBASE, ch)
+#define dma_enable_alt_next_useburst(ch)			\
+			dma_desc_enable_alt_next_useburst(DMA_CTRLBASE, ch)
+#define dma_disable_alt_next_useburst(ch)			\
+			dma_desc_disable_alt_next_useburst(DMA_CTRLBASE, ch)
+
+#define dma_set_count(ch, count)				\
+			dma_desc_set_count(DMA_CTRLBASE, ch, count)
+#define dma_set_alt_count(ch, count)				\
+			dma_desc_set_count(DMA_ALTCTRLBASE, ch, count)
+
+#define dma_set_user_data(ch, user_data)			\
+			dma_desc_set_user_data(DMA_CTRLBASE, ch, user_data)
+#define dma_set_alt_user_data(ch, user_data)		\
+			dma_desc_set_user_data(DMA_ALTCTRLBASE, ch, user_data)
+
+#define dma_get_user_data(ch)	\
+	dma_desc_get_user_data(DMA_CTRLBASE, ch)
+#define dma_get_alt_user_data(ch)	\
+	dma_desc_get_user_data(DMA_ALTCTRLBASE, ch)
+
+#define dma_set_src_address(ch, src)				\
+			dma_desc_set_src_address(DMA_CTRLBASE, ch, src)
+#define dma_set_alt_src_address(ch, src)			\
+			dma_desc_set_src_address(DMA_ALTCTRLBASE, ch, src)
+#define dma_set_dest_address(ch, dest)				\
+			dma_desc_set_dest_address(DMA_CTRLBASE, ch, dest)
+#define dma_set_alt_dest_address(ch, dest)			\
+			dma_desc_set_dest_address(DMA_ALTCTRLBASE, ch, dest)
+
+#define dma_set_mode(ch, mode)	\
+	dma_desc_set_mode(DMA_CTRLBASE, ch, mode)
+#define dma_set_alt_mode(ch, mode)	\
+	dma_desc_set_mode(DMA_ALTCTRLBASE, ch, mode)
+
+END_DECLS
+
+/**@}*/

3rd/libopencm3/include/libopencm3/efm32/common/emu_common.h

@@ -0,0 +1,191 @@
+/** @addtogroup emu_defines
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/efm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/**@{*/
+
+#define EMU_CTRL			MMIO32(EMU_BASE + 0x000)
+#define EMU_LOCK			MMIO32(EMU_BASE + 0x008)
+#define EMU_AUXCTRL			MMIO32(EMU_BASE + 0x024)
+#define EMU_EM4CONF			MMIO32(EMU_BASE + 0x02C)
+#define EMU_BUCTRL			MMIO32(EMU_BASE + 0x030)
+#define EMU_PWRCONF			MMIO32(EMU_BASE + 0x034)
+#define EMU_BUINACT			MMIO32(EMU_BASE + 0x038)
+#define EMU_BUACT			MMIO32(EMU_BASE + 0x03C)
+#define EMU_STATUS			MMIO32(EMU_BASE + 0x040)
+#define EMU_ROUTE			MMIO32(EMU_BASE + 0x044)
+#define EMU_IF				MMIO32(EMU_BASE + 0x048)
+#define EMU_IFS				MMIO32(EMU_BASE + 0x04C)
+#define EMU_IFC				MMIO32(EMU_BASE + 0x050)
+#define EMU_IEN				MMIO32(EMU_BASE + 0x054)
+#define EMU_BUBODBUVINCAL		MMIO32(EMU_BASE + 0x058)
+#define EMU_BUBODUNREGCAL		MMIO32(EMU_BASE + 0x05C)
+
+/* EMU_CTRL */
+#define EMU_CTRL_EM4CTRL_SHIFT		(2)
+#define EMU_CTRL_EM4CTRL_MASK		(0x3 << EMU_CTRL_EM4CTRL_SHIFT)
+#define EMU_CTLR_EM4CTRL(v)		\
+	(((v) << EMU_CTRL_EM4CTRL_SHIFT) & EMU_CTRL_EM4CTRL_MASK)
+
+#define EMU_CTRL_EM2BLOCK		(1 << 1)
+#define EMU_CTRL_EMVREG			(1 << 0)
+
+/* EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_MASK		(0xFFFF)
+#define EMU_LOCK_LOCKKEY_LOCK		(0)
+#define EMU_LOCK_LOCKKEY_UNLOCK		(0xADE8)
+
+/* EMU_AUXCTRL */
+#define EMU_AUXCTRL_HRCCLR		(1 << 0)
+
+/* EMU_EM4CONF */
+#define EMU_EM4CONF_LOCKCONF		(1 << 16)
+#define EMU_EM4CONF_BUBODRSTDIS		(1 << 4)
+
+#define EMU_EM4CONF_OSC_SHIFT		(2)
+#define EMU_EM4CONF_OSC_MASK		(0x3 << EMU_EM4CONF_OSC_SHIFT)
+#define EMU_EM4CONF_OSC(v)		\
+	(((v) << EMU_EM4CONF_OSC_SHIFT) & EMU_EM4CONF_OSC_MASK)
+#define EMU_EM4CONF_OSC_ULFRCO	0
+#define EMU_EM4CONF_OSC_LFRCO	1
+#define EMU_EM4CONF_OSC_LFXO	2
+
+#define EMU_EM4CONF_BURTCWU		(1 << 1)
+#define EMU_EM4CONF_VREGEN		(1 << 0)
+
+/* EMU_BUCTRL */
+#define EMU_BUCTRL_PROBE_SHIFT		(5)
+#define EMU_BUCTRL_PROBE_MASK		(0x3 << EMU_BUCTRL_PROBE_SHIFT)
+#define EMU_BUCTRL_PROBE(v)		\
+	(((v) << EMU_BUCTRL_PROBE_SHIFT) & EMU_BUCTRL_PROBE_MASK)
+#define EMU_BUCTRL_PROBE_DISABLE	0
+#define EMU_BUCTRL_PROBE_VDDDREG	1
+#define EMU_BUCTRL_PROBE_BUIN		2
+#define EMU_BUCTRL_PROBE_BUOUT		3
+
+#define EMU_BUCTRL_BUMODEBODEN		(1 << 3)
+#define EMU_BUCTRL_BODCAL		(1 << 2)
+#define EMU_BUCTRL_STATEN		(1 << 1)
+#define EMU_BUCTRL_EN			(1 << 0)
+
+/* EMU_PWRCONF */
+#define EMU_PWRCONF_PWRRES_SHIFT	(3)
+#define EMU_PWRCONF_PWRRES_MASK		(0x3 << EMU_PWRCONF_PWRRES_SHIFT)
+#define EMU_PWRCONF_PWRRES(v)		\
+	(((v) << EMU_PWRCONF_PWRRES_SHIFT) & EMU_PWRCONF_PWRRES_MASK)
+#define EMU_PWRCONF_PWRRES_DISABLE	0
+#define EMU_PWRCONF_PWRRES_VDDDREG	1
+#define EMU_PWRCONF_PWRRES_BUIN		2
+#define EMU_PWRCONF_PWRRES_BUOUT	3
+
+#define EMU_PWRCONF_VOUTSTRONG		(1 << 2)
+#define EMU_PWRCONF_VOUTMED		(1 << 1)
+#define EMU_PWRCONF_VOUTWEAK		(1 << 0)
+
+/* EMU_BUINACT */
+#define EMU_BUINACT_PWRCON_SHIFT	(5)
+#define EMU_BUINACT_PWRCON_MASK		(0x3 << EMU_BUINACT_PWRCON_SHIFT)
+#define EMU_BUINACT_PWRCON(v)		\
+	(((v) << EMU_BUINACT_PWRCON_SHIFT) & EMU_BUINACT_PWRCON_MASK)
+#define EMU_BUINACT_PWRCON_NONE		0
+#define EMU_BUINACT_PWRCON_BUMAIN	1
+#define EMU_BUINACT_PWRCON_MAINBU	2
+#define EMU_BUINACT_PWRCON_NODIODE	3
+
+#define EMU_BUINACT_BUENRANGE_SHIFT	(3)
+#define EMU_BUINACT_BUENRANGE_MASK	(0x3 << EMU_BUINACT_BUENRANGE_SHIFT)
+#define EMU_BUINACT_BUENRANGE(v)	\
+	(((v) << EMU_BUINACT_BUENRANGE_SHIFT) & EMU_BUINACT_BUENRANGE_MASK)
+
+#define EMU_BUINACT_BUENTHRES_SHIFT	(0)
+#define EMU_BUINACT_BUENTHRES_MASK	(0x7 << EMU_BUINACT_BUENTHRES_SHIFT)
+#define EMU_BUINACT_BUENTHRES(v)	\
+	(((v) << EMU_BUINACT_BUENTHRES_SHIFT) & EMU_BUINACT_BUENTHRES_MASK)
+
+/* EMU_BUACT */
+#define EMU_BUACT_PWRCON_SHIFT		(5)
+#define EMU_BUACT_PWRCON_MASK		(0x3 << EMU_BUACT_PWRCON_SHIFT)
+#define EMU_BUACT_PWRCON(v)			\
+	(((v) << EMU_BUACT_PWRCON_SHIFT) & EMU_BUACT_PWRCON_MASK)
+#define EMU_BUACT_PWRCON_NONE		0
+#define EMU_BUACT_PWRCON_BUMAIN		1
+#define EMU_BUACT_PWRCON_MAINBU		2
+#define EMU_BUACT_PWRCON_NODIODE	3
+
+#define EMU_BUACT_BUEXRANGE_SHIFT	(3)
+#define EMU_BUACT_BUEXRANGE_MASK	(0x3 << EMU_BUACT_BUEXRANGE_SHIFT)
+#define EMU_BUACT_BUEXRANGE(v)		\
+	(((v) << EMU_BUACT_BUEXRANGE_SHIFT) & EMU_BUACT_BUEXRANGE_MASK)
+
+#define EMU_BUACT_BUEXTHRES_SHIFT	(0)
+#define EMU_BUACT_BUEXTHRES_MASK	(0x7 << EMU_BUACT_BUEXTHRES_SHIFT)
+#define EMU_BUACT_BUEXTHRES(v)		\
+	(((v) << EMU_BUACT_BUEXTHRES_SHIFT) & EMU_BUACT_BUEXTHRES_MASK)
+
+/* EMU_STATUS */
+#define EMU_STATUS_BURDY		(1 << 0)
+
+/* EMU_ROUTE */
+#define EMU_ROUTE_BUVINPEN		(1 << 0)
+
+/* EMU_IF */
+#define EMU_IF_BURDY			(1 << 0)
+
+/* EMU_IFS */
+#define EMU_IFS_BURDY			(1 << 0)
+
+/* EMU_IFC */
+#define EMU_IFC_BURDY			(1 << 0)
+
+/* EMU_IEN */
+#define EMU_IEN_BURDY			(1 << 0)
+
+/* EMU_BUBODBUVINCAL */
+#define EMU_BUBODBUVINCAL_RANGE_SHIFT	(3)
+#define EMU_BUBODBUVINCAL_RANGE_MASK	(0x3 << EMU_BUBODBUVINCAL_RANGE_SHIFT)
+#define EMU_BUBODBUVINCAL_RANGE(v)	\
+	(((v) << EMU_BUBODBUVINCAL_RANGE_SHIFT) & \
+	 EMU_BUBODBUVINCAL_RANGE_MASK)
+
+#define EMU_BUBODBUVINCAL_THRES_SHIFT	(0)
+#define EMU_BUBODBUVINCAL_THRES_MASK	(0x7 << EMU_BUBODBUVINCAL_THRES_SHIFT)
+#define EMU_BUBODBUVINCAL_THRES(v)	\
+	(((v) << EMU_BUBODBUVINCAL_THRES_SHIFT) & \
+	 EMU_BUBODBUVINCAL_THRES_MASK)
+
+/* EMU_BUBODUNREGCAL */
+#define EMU_BUBODUNREGCAL_RANGE_SHIFT	(3)
+#define EMU_BUBODUNREGCAL_RANGE_MASK	(0x3 << EMU_BUBODUNREGCAL_RANGE_SHIFT)
+#define EMU_BUBODUNREGCAL_RANGE(v)	\
+	(((v) << EMU_BUBODUNREGCAL_RANGE_SHIFT) & \
+	 EMU_BUBODUNREGCAL_RANGE_MASK)
+
+#define EMU_BUBODUNREGCAL_THRES_SHIFT	(0)
+#define EMU_BUBODUNREGCAL_THRES_MASK	(0x7 << EMU_BUBODUNREGCAL_THRES_SHIFT)
+#define EMU_BUBODUNREGCAL_THRES(v)	\
+	(((v) << EMU_BUBODUNREGCAL_THRES_SHIFT) & \
+	 EMU_BUBODUNREGCAL_THRES_MASK)
+
+/**@}*/

3rd/libopencm3/include/libopencm3/efm32/common/gpio_common.h

@@ -0,0 +1,332 @@
+/** @addtogroup gpio_defines
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/efm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/**@{*/
+
+#define GPIO_P(i)		(GPIO_BASE + (0x24 * (i)))
+#define GPIO_PA			GPIO_P(0)
+#define GPIO_PB			GPIO_P(1)
+#define GPIO_PC			GPIO_P(2)
+#define GPIO_PD			GPIO_P(3)
+#define GPIO_PE			GPIO_P(4)
+#define GPIO_PF			GPIO_P(5)
+
+#define GPIO_P_CTRL(port)	MMIO32((port) + 0x00)
+#define GPIO_PA_CTRL		GPIO_P_CTRL(GPIO_PA)
+#define GPIO_PB_CTRL		GPIO_P_CTRL(GPIO_PB)
+#define GPIO_PC_CTRL		GPIO_P_CTRL(GPIO_PC)
+#define GPIO_PD_CTRL		GPIO_P_CTRL(GPIO_PD)
+#define GPIO_PE_CTRL		GPIO_P_CTRL(GPIO_PE)
+#define GPIO_PF_CTRL		GPIO_P_CTRL(GPIO_PF)
+
+#define GPIO_P_CTRL_DRIVEMODE_SHIFT	(0)
+#define GPIO_P_CTRL_DRIVEMODE_MASK	(0x03 << GPIO_P_CTRL_DRIVEMODE_SHIFT)
+#define GPIO_P_CTRL_DRIVEMODE(v)	\
+	(((v) << GPIO_P_CTRL_DRIVEMODE_SHIFT) & GPIO_P_CTRL_DRIVEMODE_MASK)
+#define GPIO_P_CTRL_DRIVEMODE_STANDARD	0
+#define GPIO_P_CTRL_DRIVEMODE_LOWEST	1
+#define GPIO_P_CTRL_DRIVEMODE_HIGH	2
+#define GPIO_P_CTRL_DRIVEMODE_LOW	3
+
+/* NOTE: GPIO_MODE and GPIO_MODE_MASK is generic.
+ * it is used with both GPIO_Px_MODEL and GPIO_Px_MODEH */
+#define GPIO_P_MODE_MODEx_MASK(x)	(0x0F << (((x) & 0x7) * 4))
+/* for mode: use GPIO_MODE_* */
+#define GPIO_P_MODE_MODEx(x, mode)	\
+	(((mode) << (((x) & 0x7) * 4)) & GPIO_P_MODE_MODEx_MASK(x))
+
+#define GPIO_P_MODEL(port)	MMIO32((port) + 0x04)
+#define GPIO_PA_MODEL		GPIO_P_MODEL(GPIO_PA)
+#define GPIO_PB_MODEL		GPIO_P_MODEL(GPIO_PB)
+#define GPIO_PC_MODEL		GPIO_P_MODEL(GPIO_PC)
+#define GPIO_PD_MODEL		GPIO_P_MODEL(GPIO_PD)
+#define GPIO_PE_MODEL		GPIO_P_MODEL(GPIO_PE)
+
+#define GPIO_P_MODEL_MODEx_MASK(x)	GPIO_P_MODE_MODEx_MASK(x)
+#define GPIO_P_MODEL_MODEx(x, mode)	GPIO_P_MODE_MODEx(x, mode)
+
+#define GPIO_P_MODEL_MODE0_MASK		GPIO_P_MODEL_MODEx_MASK(0)
+#define GPIO_P_MODEL_MODE0(mode)	GPIO_P_MODEL_MODEx(0, mode)
+
+#define GPIO_P_MODEL_MODE1_MASK		GPIO_P_MODEL_MODEx_MASK(1)
+#define GPIO_P_MODEL_MODE1(mode)	GPIO_P_MODEL_MODEx(1, mode)
+
+#define GPIO_P_MODEL_MODE2_MASK		GPIO_P_MODEL_MODEx_MASK(2)
+#define GPIO_P_MODEL_MODE2(mode)	GPIO_P_MODEL_MODEx(2, mode)
+
+#define GPIO_P_MODEL_MODE3_MASK		GPIO_P_MODEL_MODEx_MASK(3)
+#define GPIO_P_MODEL_MODE3(mode)	GPIO_P_MODEL_MODEx(3, mode)
+
+#define GPIO_P_MODEL_MODE4_MASK		GPIO_P_MODEL_MODEx_MASK(4)
+#define GPIO_P_MODEL_MODE4(mode)	GPIO_P_MODEL_MODEx(4, mode)
+
+#define GPIO_P_MODEL_MODE5_MASK		GPIO_P_MODEL_MODEx_MASK(5)
+#define GPIO_P_MODEL_MODE5(mode)	GPIO_P_MODEL_MODEx(5, mode)
+
+#define GPIO_P_MODEL_MODE6_MASK		GPIO_P_MODEL_MODEx_MASK(6)
+#define GPIO_P_MODEL_MODE6(mode)	GPIO_P_MODEL_MODEx(6, mode)
+
+#define GPIO_P_MODEL_MODE7_MASK		GPIO_P_MODEL_MODEx_MASK(7)
+#define GPIO_P_MODEL_MODE7(mode)	GPIO_P_MODEL_MODEx(7, mode)
+
+#define GPIO_P_MODEH(port)		MMIO32((port) + 0x08)
+#define GPIO_PA_MODEH			GPIO_P_MODEH(GPIO_PA)
+#define GPIO_PB_MODEH			GPIO_P_MODEH(GPIO_PB)
+#define GPIO_PC_MODEH			GPIO_P_MODEH(GPIO_PC)
+#define GPIO_PD_MODEH			GPIO_P_MODEH(GPIO_PD)
+#define GPIO_PE_MODEH			GPIO_P_MODEH(GPIO_PE)
+
+/* note: (x - 8) is because for MODEH, MODE8 refers to offset 0 */
+#define GPIO_P_MODEH_MODEx_MASK(x)	GPIO_P_MODE_MODEx_MASK((x) - 8)
+#define GPIO_P_MODEH_MODEx(x, mode)	GPIO_P_MODE_MODEx((x) - 8, mode)
+
+#define GPIO_P_MODEH_MODE8_MASK		GPIO_P_MODEH_MODEx_MASK(8)
+#define GPIO_P_MODEH_MODE8(mode)	GPIO_P_MODEH_MODEx(8, mode)
+
+#define GPIO_P_MODEH_MODE9_MASK		GPIO_P_MODEH_MODEx_MASK(9)
+#define GPIO_P_MODEH_MODE9(mode)	GPIO_P_MODEH_MODEx(9, mode)
+
+#define GPIO_P_MODEH_MODE10_MASK	GPIO_P_MODEH_MODEx_MASK(10)
+#define GPIO_P_MODEH_MODE10(mode)	GPIO_P_MODEH_MODEx(10, mode)
+
+#define GPIO_P_MODEH_MODE11_MASK	GPIO_P_MODEH_MODEx_MASK(11)
+#define GPIO_P_MODEH_MODE11(mode)	GPIO_P_MODEH_MODEx(11, mode)
+
+#define GPIO_P_MODEH_MODE12_MASK	GPIO_P_MODEH_MODEx_MASK(12)
+#define GPIO_P_MODEH_MODE12(mode)	GPIO_P_MODEH_MODEx(12, mode)
+
+#define GPIO_P_MODEH_MODE13_MASK	GPIO_P_MODEH_MODEx_MASK(13)
+#define GPIO_P_MODEH_MODE13(mode)	GPIO_P_MODEH_MODEx(13, mode)
+
+#define GPIO_P_MODEH_MODE14_MASK	GPIO_P_MODEH_MODEx_MASK(14)
+#define GPIO_P_MODEH_MODE14(mode)	GPIO_P_MODEH_MODEx(14, mode)
+
+#define GPIO_P_MODEH_MODE15_MASK	GPIO_P_MODEH_MODEx_MASK(15)
+#define GPIO_P_MODEH_MODE15(mode)	GPIO_P_MODEH_MODEx(15, mode)
+
+#define GPIO_P_DOUT(port)		MMIO32((port) + 0x0C)
+#define GPIO_PA_DOUT			GPIO_P_DOUT(GPIO_PA)
+#define GPIO_PB_DOUT			GPIO_P_DOUT(GPIO_PB)
+#define GPIO_PC_DOUT			GPIO_P_DOUT(GPIO_PC)
+#define GPIO_PD_DOUT			GPIO_P_DOUT(GPIO_PD)
+#define GPIO_PE_DOUT			GPIO_P_DOUT(GPIO_PE)
+
+#define GPIO_P_DOUTSET(port)		MMIO32((port) + 0x10)
+#define GPIO_PA_DOUTSET			GPIO_P_DOUTSET(GPIO_PA)
+#define GPIO_PB_DOUTSET			GPIO_P_DOUTSET(GPIO_PB)
+#define GPIO_PC_DOUTSET			GPIO_P_DOUTSET(GPIO_PC)
+#define GPIO_PD_DOUTSET			GPIO_P_DOUTSET(GPIO_PD)
+#define GPIO_PE_DOUTSET			GPIO_P_DOUTSET(GPIO_PE)
+
+#define GPIO_P_DOUTCLR(port)		MMIO32((port) + 0x14)
+#define GPIO_PA_DOUTCLR			GPIO_P_DOUTCLR(GPIO_PA)
+#define GPIO_PB_DOUTCLR			GPIO_P_DOUTCLR(GPIO_PB)
+#define GPIO_PC_DOUTCLR			GPIO_P_DOUTCLR(GPIO_PC)
+#define GPIO_PD_DOUTCLR			GPIO_P_DOUTCLR(GPIO_PD)
+#define GPIO_PE_DOUTCLR			GPIO_P_DOUTCLR(GPIO_PE)
+
+#define GPIO_P_DOUTTGL(port)		MMIO32((port) + 0x18)
+#define GPIO_PA_DOUTTGL			GPIO_P_DOUTTGL(GPIO_PA)
+#define GPIO_PB_DOUTTGL			GPIO_P_DOUTTGL(GPIO_PB)
+#define GPIO_PC_DOUTTGL			GPIO_P_DOUTTGL(GPIO_PC)
+#define GPIO_PD_DOUTTGL			GPIO_P_DOUTTGL(GPIO_PD)
+#define GPIO_PE_DOUTTGL			GPIO_P_DOUTTGL(GPIO_PE)
+
+#define GPIO_P_DIN(port)		MMIO32((port) + 0x1C)
+#define GPIO_PA_DIN			GPIO_P_DIN(GPIO_PA)
+#define GPIO_PB_DIN			GPIO_P_DIN(GPIO_PB)
+#define GPIO_PC_DIN			GPIO_P_DIN(GPIO_PC)
+#define GPIO_PD_DIN			GPIO_P_DIN(GPIO_PD)
+#define GPIO_PE_DIN			GPIO_P_DIN(GPIO_PE)
+
+#define GPIO_P_PINLOCKN(port)		MMIO32((port) + 0x20)
+#define GPIO_PA_PINLOCKN		GPIO_P_PINLOCKN(GPIO_PA)
+#define GPIO_PB_PINLOCKN		GPIO_P_PINLOCKN(GPIO_PB)
+#define GPIO_PC_PINLOCKN		GPIO_P_PINLOCKN(GPIO_PC)
+#define GPIO_PD_PINLOCKN		GPIO_P_PINLOCKN(GPIO_PD)
+#define GPIO_PE_PINLOCKN		GPIO_P_PINLOCKN(GPIO_PE)
+
+#define GPIO_EXTIPSELL			MMIO32(GPIO_BASE + 0x100)
+#define GPIO_EXTIPSELH			MMIO32(GPIO_BASE + 0x104)
+#define GPIO_EXTIRISE			MMIO32(GPIO_BASE + 0x108)
+#define GPIO_EXTIFALL			MMIO32(GPIO_BASE + 0x10C)
+#define GPIO_IEN			MMIO32(GPIO_BASE + 0x110)
+#define GPIO_IF				MMIO32(GPIO_BASE + 0x114)
+#define GPIO_IFS			MMIO32(GPIO_BASE + 0x118)
+#define GPIO_IFC			MMIO32(GPIO_BASE + 0x11C)
+#define GPIO_ROUTE			MMIO32(GPIO_BASE + 0x120)
+#define GPIO_INSENSE			MMIO32(GPIO_BASE + 0x124)
+#define GPIO_LOCK			MMIO32(GPIO_BASE + 0x128)
+#define GPIO_CTRL			MMIO32(GPIO_BASE + 0x12C)
+#define GPIO_CMD			MMIO32(GPIO_BASE + 0x130)
+#define GPIO_EM4WUEN			MMIO32(GPIO_BASE + 0x134)
+#define GPIO_EM4WUPOL			MMIO32(GPIO_BASE + 0x138)
+#define GPIO_EM4WUCAUSE			MMIO32(GPIO_BASE + 0x13C)
+
+/* mask is performed so that can be used with L and H */
+#define GPIO_EXTIPSEL_MASK(n)		(0x7 << ((n) & 0xF))
+#define GPIO_EXTIPSEL_PORTMASK(n, v)	((v) << ((n) & 0xF))
+#define GPIO_EXTIPSEL_PORTA		0x0
+#define GPIO_EXTIPSEL_PORTB		0x1
+#define GPIO_EXTIPSEL_PORTC		0x2
+#define GPIO_EXTIPSEL_PORTD		0x3
+#define GPIO_EXTIPSEL_PORTE		0x4
+#define GPIO_EXTIPSEL_PORTF		0x5
+
+#define GPIO_ROUTE_SWCLKPEN		(1 << 0)
+#define GPIO_ROUTE_SWDIOPEN		(1 << 1)
+#define GPIO_ROUTE_SWOPEN		(1 << 3)
+
+#define GPIO_ROUTE_SWLOCATION_SHIFT	(8)
+#define GPIO_ROUTE_SWLOCATION_MASK	(0x3 << GPIO_ROUTE_SWLOCATION_SHIFT)
+#define GPIO_ROUTE_SWLOCATION(v)	\
+	(((v) << GPIO_ROUTE_SWLOCATION_SHIFT) & GPIO_ROUTE_SWLOCATION_MASK)
+
+#define GPIO_ROUTE_TCLKPEN		(1 << 12)
+#define GPIO_ROUTE_TD0PEN		(1 << 13)
+#define GPIO_ROUTE_TD1PEN		(1 << 14)
+#define GPIO_ROUTE_TD2PEN		(1 << 15)
+#define GPIO_ROUTE_TD3PEN		(1 << 16)
+
+#define GPIO_ROUTE_ETMLOCATION_SHIFT	(24)
+#define GPIO_ROUTE_ETMLOCATION_MASK	(0x3 << GPIO_ROUTE_ETMLOCATION_SHIFT)
+#define GPIO_ROUTE_ETMLOCATION(v)	\
+	(((v) << GPIO_ROUTE_ETMLOCATION_SHIFT) & GPIO_ROUTE_ETMLOCATION_MASK)
+#define GPIO_ROUTE_ETMLOCATION_LOCx(x)	GPIO_ROUTE_ETMLOCATION(x)
+#define GPIO_ROUTE_ETMLOCATION_LOC0	0
+#define GPIO_ROUTE_ETMLOCATION_LOC1	1
+#define GPIO_ROUTE_ETMLOCATION_LOC2	2
+#define GPIO_ROUTE_ETMLOCATION_LOC3	3
+
+#define GPIO_INSENSE_INT		(1 << 0)
+#define GPIO_INSENSE_PRS		(1 << 1)
+
+#define GPIO_LOCK_LOCKKEY_SHIFT		(0)
+#define GPIO_LOCK_LOCKKEY_MASK		(0xFFFF << GPIO_LOCK_LOCKKEY_SHIFT)
+#define GPIO_LOCK_LOCKKEY_UNLOCKED	(0x0000 << GPIO_LOCK_LOCKKEY_SHIFT)
+#define GPIO_LOCK_LOCKKEY_LOCKED	(0x0001 << GPIO_LOCK_LOCKKEY_SHIFT)
+#define GPIO_LOCK_LOCKKEY_LOCK		(0x0000 << GPIO_LOCK_LOCKKEY_SHIFT)
+#define GPIO_LOCK_LOCKKEY_UNLOCK	(0xA534 << GPIO_LOCK_LOCKKEY_SHIFT)
+
+#define GPIO_CTRL_EM4RET		(1 << 0)
+
+#define GPIO_CMD_EM4WUCLR		(1 << 0)
+
+#define GPIO_EM4WUEN_EM4WUEN_A0		(1 << 0)
+#define GPIO_EM4WUEN_EM4WUEN_A6		(1 << 1)
+#define GPIO_EM4WUEN_EM4WUEN_C9		(1 << 2)
+#define GPIO_EM4WUEN_EM4WUEN_F1		(1 << 3)
+#define GPIO_EM4WUEN_EM4WUEN_F2		(1 << 4)
+#define GPIO_EM4WUEN_EM4WUEN_E13	(1 << 5)
+
+#define GPIO_EM4WUPOL_EM4WUPOL_A0	(1 << 0)
+#define GPIO_EM4WUPOL_EM4WUPOL_A6	(1 << 1)
+#define GPIO_EM4WUPOL_EM4WUPOL_C9	(1 << 2)
+#define GPIO_EM4WUPOL_EM4WUPOL_F1	(1 << 3)
+#define GPIO_EM4WUPOL_EM4WUPOL_F2	(1 << 4)
+#define GPIO_EM4WUPOL_EM4WUPOL_E13	(1 << 5)
+
+#define GPIO0				(1 << 0)
+#define GPIO1				(1 << 1)
+#define GPIO2				(1 << 2)
+#define GPIO3				(1 << 3)
+#define GPIO4				(1 << 4)
+#define GPIO5				(1 << 5)
+#define GPIO6				(1 << 6)
+#define GPIO7				(1 << 7)
+#define GPIO8				(1 << 8)
+#define GPIO9				(1 << 9)
+#define GPIO10				(1 << 10)
+#define GPIO11				(1 << 11)
+#define GPIO12				(1 << 12)
+#define GPIO13				(1 << 13)
+#define GPIO14				(1 << 14)
+#define GPIO15				(1 << 15)
+#define GPIO_ALL			(0xFFFF)
+
+/* These are the acceptable mode values.
+ *   (+ readable counterparts)
+ *  do not confuse GPIO_MODE_* for GPIO_P_MODE_MODEx.
+ */
+enum gpio_mode {
+	GPIO_MODE_DISABLE = 0,
+	GPIO_MODE_INPUT,
+	GPIO_MODE_INPUT_PULL,
+	GPIO_MODE_INPUT_PULL_FILTER,
+	GPIO_MODE_PUSH_PULL,
+	GPIO_MODE_PUSH_PULL_DRIVE,
+	GPIO_MODE_WIRED_OR,
+	GPIO_MODE_WIRED_OR_PULL_DOWN,
+	GPIO_MODE_WIRED_AND,
+	GPIO_MODE_WIRED_AND_FILTER,
+	GPIO_MODE_WIRED_AND_PULLUP,
+	GPIO_MODE_WIRED_AND_PULLUP_FILTER,
+	GPIO_MODE_WIRED_AND_DRIVE,
+	GPIO_MODE_WIRED_AND_DRIVE_FILTER,
+	GPIO_MODE_WIRED_AND_DRIVE_PULLUP,
+	GPIO_MODE_WIRED_AND_DRIVE_PULLUP_FILTER
+};
+
+/* for readability. */
+enum gpio_drive_strength {
+	GPIO_STRENGTH_STANDARD = 0,
+	GPIO_STRENGTH_LOWEST,
+	GPIO_STRENGTH_HIGH,
+	GPIO_STRENGTH_LOW
+};
+
+/* for readability */
+#define GPIOA GPIO_PA
+#define GPIOB GPIO_PB
+#define GPIOC GPIO_PC
+#define GPIOD GPIO_PD
+#define GPIOE GPIO_PE
+#define GPIOF GPIO_PF
+
+/* --- Function prototypes ------------------------------------------------- */
+
+BEGIN_DECLS
+
+void gpio_enable_lock(void);
+void gpio_disable_lock(void);
+bool gpio_get_lock_flag(void);
+
+void gpio_set_drive_strength(uint32_t gpio_port,
+		enum gpio_drive_strength driver_stength);
+void gpio_mode_setup(uint32_t gpio_port, enum gpio_mode mode, uint16_t gpios);
+
+void gpio_set(uint32_t gpio_port, uint16_t gpios);
+void gpio_clear(uint32_t gpio_port, uint16_t gpios);
+uint16_t gpio_get(uint32_t gpio_port, uint16_t gpios);
+void gpio_toggle(uint32_t gpio_port, uint16_t gpios);
+uint16_t gpio_port_read(uint32_t gpio_port);
+void gpio_port_write(uint32_t gpio_port, uint16_t data);
+
+void gpio_port_config_lock(uint32_t gpio_port, uint16_t gpios);
+
+END_DECLS
+
+/**@}*/

3rd/libopencm3/include/libopencm3/efm32/common/gpio_common_hglg.h

@@ -0,0 +1,332 @@
+/** @addtogroup gpio_defines
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/efm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/**@{*/
+
+#define GPIO_P(i)		(GPIO_BASE + (0x24 * (i)))
+#define GPIO_PA			GPIO_P(0)
+#define GPIO_PB			GPIO_P(1)
+#define GPIO_PC			GPIO_P(2)
+#define GPIO_PD			GPIO_P(3)
+#define GPIO_PE			GPIO_P(4)
+#define GPIO_PF			GPIO_P(5)
+
+#define GPIO_P_CTRL(port)	MMIO32((port) + 0x00)
+#define GPIO_PA_CTRL		GPIO_P_CTRL(GPIO_PA)
+#define GPIO_PB_CTRL		GPIO_P_CTRL(GPIO_PB)
+#define GPIO_PC_CTRL		GPIO_P_CTRL(GPIO_PC)
+#define GPIO_PD_CTRL		GPIO_P_CTRL(GPIO_PD)
+#define GPIO_PE_CTRL		GPIO_P_CTRL(GPIO_PE)
+#define GPIO_PF_CTRL		GPIO_P_CTRL(GPIO_PF)
+
+#define GPIO_P_CTRL_DRIVEMODE_SHIFT	(0)
+#define GPIO_P_CTRL_DRIVEMODE_MASK	(0x03 << GPIO_P_CTRL_DRIVEMODE_SHIFT)
+#define GPIO_P_CTRL_DRIVEMODE(v)	\
+	(((v) << GPIO_P_CTRL_DRIVEMODE_SHIFT) & GPIO_P_CTRL_DRIVEMODE_MASK)
+#define GPIO_P_CTRL_DRIVEMODE_STANDARD	GPIO_P_CTRL_DRIVEMODE(0)
+#define GPIO_P_CTRL_DRIVEMODE_LOWEST	GPIO_P_CTRL_DRIVEMODE(1)
+#define GPIO_P_CTRL_DRIVEMODE_HIGH	GPIO_P_CTRL_DRIVEMODE(2)
+#define GPIO_P_CTRL_DRIVEMODE_LOW	GPIO_P_CTRL_DRIVEMODE(3)
+
+/* NOTE: GPIO_MODE and GPIO_MODE_MASK is generic.
+ * it is used with both GPIO_Px_MODEL and GPIO_Px_MODEH */
+#define GPIO_P_MODE_MODEx_MASK(x)	(0x0F << (((x) & 0x7) * 4))
+/* for mode: use GPIO_MODE_* */
+#define GPIO_P_MODE_MODEx(x, mode)	\
+	(((mode) << (((x) & 0x7) * 4)) & GPIO_P_MODE_MODEx_MASK(x))
+
+#define GPIO_P_MODEL(port)	MMIO32((port) + 0x04)
+#define GPIO_PA_MODEL		GPIO_P_MODEL(GPIO_PA)
+#define GPIO_PB_MODEL		GPIO_P_MODEL(GPIO_PB)
+#define GPIO_PC_MODEL		GPIO_P_MODEL(GPIO_PC)
+#define GPIO_PD_MODEL		GPIO_P_MODEL(GPIO_PD)
+#define GPIO_PE_MODEL		GPIO_P_MODEL(GPIO_PE)
+
+#define GPIO_P_MODEL_MODEx_MASK(x)	GPIO_P_MODE_MODEx_MASK(x)
+#define GPIO_P_MODEL_MODEx(x, mode)	GPIO_P_MODE_MODEx(x, mode)
+
+#define GPIO_P_MODEL_MODE0_MASK		GPIO_P_MODEL_MODEx_MASK(0)
+#define GPIO_P_MODEL_MODE0(mode)	GPIO_P_MODEL_MODEx(0, mode)
+
+#define GPIO_P_MODEL_MODE1_MASK		GPIO_P_MODEL_MODEx_MASK(1)
+#define GPIO_P_MODEL_MODE1(mode)	GPIO_P_MODEL_MODEx(1, mode)
+
+#define GPIO_P_MODEL_MODE2_MASK		GPIO_P_MODEL_MODEx_MASK(2)
+#define GPIO_P_MODEL_MODE2(mode)	GPIO_P_MODEL_MODEx(2, mode)
+
+#define GPIO_P_MODEL_MODE3_MASK		GPIO_P_MODEL_MODEx_MASK(3)
+#define GPIO_P_MODEL_MODE3(mode)	GPIO_P_MODEL_MODEx(3, mode)
+
+#define GPIO_P_MODEL_MODE4_MASK		GPIO_P_MODEL_MODEx_MASK(4)
+#define GPIO_P_MODEL_MODE4(mode)	GPIO_P_MODEL_MODEx(4, mode)
+
+#define GPIO_P_MODEL_MODE5_MASK		GPIO_P_MODEL_MODEx_MASK(5)
+#define GPIO_P_MODEL_MODE5(mode)	GPIO_P_MODEL_MODEx(5, mode)
+
+#define GPIO_P_MODEL_MODE6_MASK		GPIO_P_MODEL_MODEx_MASK(6)
+#define GPIO_P_MODEL_MODE6(mode)	GPIO_P_MODEL_MODEx(6, mode)
+
+#define GPIO_P_MODEL_MODE7_MASK		GPIO_P_MODEL_MODEx_MASK(7)
+#define GPIO_P_MODEL_MODE7(mode)	GPIO_P_MODEL_MODEx(7, mode)
+
+#define GPIO_P_MODEH(port)		MMIO32((port) + 0x08)
+#define GPIO_PA_MODEH			GPIO_P_MODEH(GPIO_PA)
+#define GPIO_PB_MODEH			GPIO_P_MODEH(GPIO_PB)
+#define GPIO_PC_MODEH			GPIO_P_MODEH(GPIO_PC)
+#define GPIO_PD_MODEH			GPIO_P_MODEH(GPIO_PD)
+#define GPIO_PE_MODEH			GPIO_P_MODEH(GPIO_PE)
+
+/* note: (x - 8) is because for MODEH, MODE8 refers to offset 0 */
+#define GPIO_P_MODEH_MODEx_MASK(x)	GPIO_P_MODE_MODEx_MASK((x) - 8)
+#define GPIO_P_MODEH_MODEx(x, mode)	GPIO_P_MODE_MODEx((x) - 8, mode)
+
+#define GPIO_P_MODEH_MODE8_MASK		GPIO_P_MODEH_MODEx_MASK(8)
+#define GPIO_P_MODEH_MODE8(mode)	GPIO_P_MODEH_MODEx(8, mode)
+
+#define GPIO_P_MODEH_MODE9_MASK		GPIO_P_MODEH_MODEx_MASK(9)
+#define GPIO_P_MODEH_MODE9(mode)	GPIO_P_MODEH_MODEx(9, mode)
+
+#define GPIO_P_MODEH_MODE10_MASK	GPIO_P_MODEH_MODEx_MASK(10)
+#define GPIO_P_MODEH_MODE10(mode)	GPIO_P_MODEH_MODEx(10, mode)
+
+#define GPIO_P_MODEH_MODE11_MASK	GPIO_P_MODEH_MODEx_MASK(11)
+#define GPIO_P_MODEH_MODE11(mode)	GPIO_P_MODEH_MODEx(11, mode)
+
+#define GPIO_P_MODEH_MODE12_MASK	GPIO_P_MODEH_MODEx_MASK(12)
+#define GPIO_P_MODEH_MODE12(mode)	GPIO_P_MODEH_MODEx(12, mode)
+
+#define GPIO_P_MODEH_MODE13_MASK	GPIO_P_MODEH_MODEx_MASK(13)
+#define GPIO_P_MODEH_MODE13(mode)	GPIO_P_MODEH_MODEx(13, mode)
+
+#define GPIO_P_MODEH_MODE14_MASK	GPIO_P_MODEH_MODEx_MASK(14)
+#define GPIO_P_MODEH_MODE14(mode)	GPIO_P_MODEH_MODEx(14, mode)
+
+#define GPIO_P_MODEH_MODE15_MASK	GPIO_P_MODEH_MODEx_MASK(15)
+#define GPIO_P_MODEH_MODE15(mode)	GPIO_P_MODEH_MODEx(15, mode)
+
+#define GPIO_P_DOUT(port)		MMIO32((port) + 0x0C)
+#define GPIO_PA_DOUT			GPIO_P_DOUT(GPIO_PA)
+#define GPIO_PB_DOUT			GPIO_P_DOUT(GPIO_PB)
+#define GPIO_PC_DOUT			GPIO_P_DOUT(GPIO_PC)
+#define GPIO_PD_DOUT			GPIO_P_DOUT(GPIO_PD)
+#define GPIO_PE_DOUT			GPIO_P_DOUT(GPIO_PE)
+
+#define GPIO_P_DOUTSET(port)		MMIO32((port) + 0x10)
+#define GPIO_PA_DOUTSET			GPIO_P_DOUTSET(GPIO_PA)
+#define GPIO_PB_DOUTSET			GPIO_P_DOUTSET(GPIO_PB)
+#define GPIO_PC_DOUTSET			GPIO_P_DOUTSET(GPIO_PC)
+#define GPIO_PD_DOUTSET			GPIO_P_DOUTSET(GPIO_PD)
+#define GPIO_PE_DOUTSET			GPIO_P_DOUTSET(GPIO_PE)
+
+#define GPIO_P_DOUTCLR(port)		MMIO32((port) + 0x14)
+#define GPIO_PA_DOUTCLR			GPIO_P_DOUTCLR(GPIO_PA)
+#define GPIO_PB_DOUTCLR			GPIO_P_DOUTCLR(GPIO_PB)
+#define GPIO_PC_DOUTCLR			GPIO_P_DOUTCLR(GPIO_PC)
+#define GPIO_PD_DOUTCLR			GPIO_P_DOUTCLR(GPIO_PD)
+#define GPIO_PE_DOUTCLR			GPIO_P_DOUTCLR(GPIO_PE)
+
+#define GPIO_P_DOUTTGL(port)		MMIO32((port) + 0x18)
+#define GPIO_PA_DOUTTGL			GPIO_P_DOUTTGL(GPIO_PA)
+#define GPIO_PB_DOUTTGL			GPIO_P_DOUTTGL(GPIO_PB)
+#define GPIO_PC_DOUTTGL			GPIO_P_DOUTTGL(GPIO_PC)
+#define GPIO_PD_DOUTTGL			GPIO_P_DOUTTGL(GPIO_PD)
+#define GPIO_PE_DOUTTGL			GPIO_P_DOUTTGL(GPIO_PE)
+
+#define GPIO_P_DIN(port)		MMIO32((port) + 0x1C)
+#define GPIO_PA_DIN			GPIO_P_DIN(GPIO_PA)
+#define GPIO_PB_DIN			GPIO_P_DIN(GPIO_PB)
+#define GPIO_PC_DIN			GPIO_P_DIN(GPIO_PC)
+#define GPIO_PD_DIN			GPIO_P_DIN(GPIO_PD)
+#define GPIO_PE_DIN			GPIO_P_DIN(GPIO_PE)
+
+#define GPIO_P_PINLOCKN(port)		MMIO32((port) + 0x20)
+#define GPIO_PA_PINLOCKN		GPIO_P_PINLOCKN(GPIO_PA)
+#define GPIO_PB_PINLOCKN		GPIO_P_PINLOCKN(GPIO_PB)
+#define GPIO_PC_PINLOCKN		GPIO_P_PINLOCKN(GPIO_PC)
+#define GPIO_PD_PINLOCKN		GPIO_P_PINLOCKN(GPIO_PD)
+#define GPIO_PE_PINLOCKN		GPIO_P_PINLOCKN(GPIO_PE)
+
+#define GPIO_EXTIPSELL			MMIO32(GPIO_BASE + 0x100)
+#define GPIO_EXTIPSELH			MMIO32(GPIO_BASE + 0x104)
+#define GPIO_EXTIRISE			MMIO32(GPIO_BASE + 0x108)
+#define GPIO_EXTIFALL			MMIO32(GPIO_BASE + 0x10C)
+#define GPIO_IEN			MMIO32(GPIO_BASE + 0x110)
+#define GPIO_IF				MMIO32(GPIO_BASE + 0x114)
+#define GPIO_IFS			MMIO32(GPIO_BASE + 0x118)
+#define GPIO_IFC			MMIO32(GPIO_BASE + 0x11C)
+#define GPIO_ROUTE			MMIO32(GPIO_BASE + 0x120)
+#define GPIO_INSENSE			MMIO32(GPIO_BASE + 0x124)
+#define GPIO_LOCK			MMIO32(GPIO_BASE + 0x128)
+#define GPIO_CTRL			MMIO32(GPIO_BASE + 0x12C)
+#define GPIO_CMD			MMIO32(GPIO_BASE + 0x130)
+#define GPIO_EM4WUEN			MMIO32(GPIO_BASE + 0x134)
+#define GPIO_EM4WUPOL			MMIO32(GPIO_BASE + 0x138)
+#define GPIO_EM4WUCAUSE			MMIO32(GPIO_BASE + 0x13C)
+
+/* mask is performed so that can be used with L and H */
+#define GPIO_EXTIPSEL_MASK(n)		(0x7 << ((n) & 0xF))
+#define GPIO_EXTIPSEL_PORTMASK(n, v)	((v) << ((n) & 0xF))
+#define GPIO_EXTIPSEL_PORTA		0x0
+#define GPIO_EXTIPSEL_PORTB		0x1
+#define GPIO_EXTIPSEL_PORTC		0x2
+#define GPIO_EXTIPSEL_PORTD		0x3
+#define GPIO_EXTIPSEL_PORTE		0x4
+#define GPIO_EXTIPSEL_PORTF		0x5
+
+#define GPIO_ROUTE_SWCLKPEN		(1 << 0)
+#define GPIO_ROUTE_SWDIOPEN		(1 << 1)
+#define GPIO_ROUTE_SWOPEN		(1 << 3)
+
+#define GPIO_ROUTE_SWLOCATION_SHIFT	(8)
+#define GPIO_ROUTE_SWLOCATION_MASK	(0x3 << GPIO_ROUTE_SWLOCATION_SHIFT)
+#define GPIO_ROUTE_SWLOCATION(v)	\
+	(((v) << GPIO_ROUTE_SWLOCATION_SHIFT) & GPIO_ROUTE_SWLOCATION_MASK)
+
+#define GPIO_ROUTE_TCLKPEN		(1 << 12)
+#define GPIO_ROUTE_TD0PEN		(1 << 13)
+#define GPIO_ROUTE_TD1PEN		(1 << 14)
+#define GPIO_ROUTE_TD2PEN		(1 << 15)
+#define GPIO_ROUTE_TD3PEN		(1 << 16)
+
+#define GPIO_ROUTE_ETMLOCATION_SHIFT	(24)
+#define GPIO_ROUTE_ETMLOCATION_MASK	(0x3 << GPIO_ROUTE_ETMLOCATION_SHIFT)
+#define GPIO_ROUTE_ETMLOCATION(v)	\
+	(((v) << GPIO_ROUTE_ETMLOCATION_SHIFT) & GPIO_ROUTE_ETMLOCATION_MASK)
+#define GPIO_ROUTE_ETMLOCATION_LOCx(x)	GPIO_ROUTE_ETMLOCATION(x)
+#define GPIO_ROUTE_ETMLOCATION_LOC0	GPIO_ROUTE_ETMLOCATION_LOCx(0)
+#define GPIO_ROUTE_ETMLOCATION_LOC1	GPIO_ROUTE_ETMLOCATION_LOCx(1)
+#define GPIO_ROUTE_ETMLOCATION_LOC2	GPIO_ROUTE_ETMLOCATION_LOCx(2)
+#define GPIO_ROUTE_ETMLOCATION_LOC3	GPIO_ROUTE_ETMLOCATION_LOCx(3)
+
+#define GPIO_INSENSE_INT		(1 << 0)
+#define GPIO_INSENSE_PRS		(1 << 1)
+
+#define GPIO_LOCK_LOCKKEY_SHIFT		(0)
+#define GPIO_LOCK_LOCKKEY_MASK		(0xFFFF << GPIO_LOCK_LOCKKEY_SHIFT)
+#define GPIO_LOCK_LOCKKEY_UNLOCKED	(0x0000 << GPIO_LOCK_LOCKKEY_SHIFT)
+#define GPIO_LOCK_LOCKKEY_LOCKED	(0x0001 << GPIO_LOCK_LOCKKEY_SHIFT)
+#define GPIO_LOCK_LOCKKEY_LOCK		(0x0000 << GPIO_LOCK_LOCKKEY_SHIFT)
+#define GPIO_LOCK_LOCKKEY_UNLOCK	(0xA534 << GPIO_LOCK_LOCKKEY_SHIFT)
+
+#define GPIO_CTRL_EM4RET		(1 << 0)
+
+#define GPIO_CMD_EM4WUCLR		(1 << 0)
+
+#define GPIO_EM4WUEN_EM4WUEN_A0		(1 << 0)
+#define GPIO_EM4WUEN_EM4WUEN_A6		(1 << 1)
+#define GPIO_EM4WUEN_EM4WUEN_C9		(1 << 2)
+#define GPIO_EM4WUEN_EM4WUEN_F1		(1 << 3)
+#define GPIO_EM4WUEN_EM4WUEN_F2		(1 << 4)
+#define GPIO_EM4WUEN_EM4WUEN_E13	(1 << 5)
+
+#define GPIO_EM4WUPOL_EM4WUPOL_A0	(1 << 0)
+#define GPIO_EM4WUPOL_EM4WUPOL_A6	(1 << 1)
+#define GPIO_EM4WUPOL_EM4WUPOL_C9	(1 << 2)
+#define GPIO_EM4WUPOL_EM4WUPOL_F1	(1 << 3)
+#define GPIO_EM4WUPOL_EM4WUPOL_F2	(1 << 4)
+#define GPIO_EM4WUPOL_EM4WUPOL_E13	(1 << 5)
+
+#define GPIO0				(1 << 0)
+#define GPIO1				(1 << 1)
+#define GPIO2				(1 << 2)
+#define GPIO3				(1 << 3)
+#define GPIO4				(1 << 4)
+#define GPIO5				(1 << 5)
+#define GPIO6				(1 << 6)
+#define GPIO7				(1 << 7)
+#define GPIO8				(1 << 8)
+#define GPIO9				(1 << 9)
+#define GPIO10				(1 << 10)
+#define GPIO11				(1 << 11)
+#define GPIO12				(1 << 12)
+#define GPIO13				(1 << 13)
+#define GPIO14				(1 << 14)
+#define GPIO15				(1 << 15)
+#define GPIO_ALL			(0xFFFF)
+
+/* These are the acceptable mode values.
+ *   (+ readable counterparts)
+ *  do not confuse GPIO_MODE_* for GPIO_P_MODE_MODEx.
+ */
+enum gpio_mode {
+	GPIO_MODE_DISABLE = 0,
+	GPIO_MODE_INPUT,
+	GPIO_MODE_INPUT_PULL,
+	GPIO_MODE_INPUT_PULL_FILTER,
+	GPIO_MODE_PUSH_PULL,
+	GPIO_MODE_PUSH_PULL_DRIVE,
+	GPIO_MODE_WIRED_OR,
+	GPIO_MODE_WIRED_OR_PULL_DOWN,
+	GPIO_MODE_WIRED_AND,
+	GPIO_MODE_WIRED_AND_FILTER,
+	GPIO_MODE_WIRED_AND_PULLUP,
+	GPIO_MODE_WIRED_AND_PULLUP_FILTER,
+	GPIO_MODE_WIRED_AND_DRIVE,
+	GPIO_MODE_WIRED_AND_DRIVE_FILTER,
+	GPIO_MODE_WIRED_AND_DRIVE_PULLUP,
+	GPIO_MODE_WIRED_AND_DRIVE_PULLUP_FILTER
+};
+
+/* for readability. */
+enum gpio_drive_strength {
+	GPIO_STRENGTH_STANDARD = 0,
+	GPIO_STRENGTH_LOWEST,
+	GPIO_STRENGTH_HIGH,
+	GPIO_STRENGTH_LOW
+};
+
+/* for readability */
+#define GPIOA GPIO_PA
+#define GPIOB GPIO_PB
+#define GPIOC GPIO_PC
+#define GPIOD GPIO_PD
+#define GPIOE GPIO_PE
+#define GPIOF GPIO_PF
+
+/* --- Function prototypes ------------------------------------------------- */
+
+BEGIN_DECLS
+
+void gpio_enable_lock(void);
+void gpio_disable_lock(void);
+bool gpio_get_lock_flag(void);
+
+void gpio_set_drive_strength(uint32_t gpio_port,
+		enum gpio_drive_strength driver_stength);
+void gpio_mode_setup(uint32_t gpio_port, enum gpio_mode mode, uint16_t gpios);
+
+void gpio_set(uint32_t gpio_port, uint16_t gpios);
+void gpio_clear(uint32_t gpio_port, uint16_t gpios);
+uint16_t gpio_get(uint32_t gpio_port, uint16_t gpios);
+void gpio_toggle(uint32_t gpio_port, uint16_t gpios);
+uint16_t gpio_port_read(uint32_t gpio_port);
+void gpio_port_write(uint32_t gpio_port, uint16_t data);
+
+void gpio_port_config_lock(uint32_t gpio_port, uint16_t gpios);
+
+END_DECLS
+
+/**@}*/

3rd/libopencm3/include/libopencm3/efm32/common/i2c_common.h

@@ -0,0 +1,271 @@
+/** @addtogroup i2c_defines
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/efm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/**@{*/
+
+#define I2C_CTRL(base)		MMIO32((base) + 0x000)
+#define I2C_CMD(base)		MMIO32((base) + 0x004)
+#define I2C_STATE(base)		MMIO32((base) + 0x008)
+#define I2C_STATUS(base)	MMIO32((base) + 0x00C)
+#define I2C_CLKDIV(base)	MMIO32((base) + 0x010)
+#define I2C_SADDR(base)		MMIO32((base) + 0x014)
+#define I2C_SADDRMASK(base)	MMIO32((base) + 0x018)
+#define I2C_RXDATA(base)	MMIO32((base) + 0x01C)
+#define I2C_RXDATAP(base)	MMIO32((base) + 0x020)
+#define I2C_TXDATA(base)	MMIO32((base) + 0x024)
+#define I2C_IF(base)		MMIO32((base) + 0x028)
+#define I2C_IFS(base)		MMIO32((base) + 0x02C)
+#define I2C_IFC(base)		MMIO32((base) + 0x030)
+#define I2C_IEN(base)		MMIO32((base) + 0x034)
+#define I2C_ROUTE(base)		MMIO32((base) + 0x038)
+
+/* I2C_CTRL */
+#define I2C_CTRL_CLTO_SHIFT	(16)
+#define I2C_CTRL_CLTO_MASK	(0x7 << I2C_CTRL_CLTO_SHIFT)
+#define I2C_CTRL_CLTO(v)	\
+	(((v) << I2C_CTRL_CLTO_SHIFT) & I2C_CTRL_CLTO_MASK)
+#define I2C_CTRL_CLTO_OFF	0
+#define I2C_CTRL_CLTO_40PCC	1
+#define I2C_CTRL_CLTO_80PCC	2
+#define I2C_CTRL_CLTO_160PCC	3
+#define I2C_CTRL_CLTO_320PPC	4
+#define I2C_CTRL_CLTO_1024PPC	5
+
+#define I2C_CTRL_GIBITO		(1 << 15)
+
+#define I2C_CTRL_BTO_SHIFT	(12)
+#define I2C_CTRL_BTO_MASK	(0x3 << I2C_CTRL_BTO_SHIFT)
+#define I2C_CTRL_BTO(v)		\
+	(((v) << I2C_CTRL_BTO_SHIFT) & I2C_CTRL_BTO_MASK)
+#define I2C_CTRL_BTO_OFF	0
+#define I2C_CTRL_BTO_40PCC	1
+#define I2C_CTRL_BTO_80PCC	2
+#define I2C_CTRL_BTO_160PCC	3
+
+#define I2C_CTRL_CLHR_SHIFT		(12)
+#define I2C_CTRL_CLHR_MASK		(0x3 << I2C_CTRL_CLHR_SHIFT)
+#define I2C_CTRL_CLHR(v)		\
+	(((v) << I2C_CTRL_CLHR_SHIFT) & I2C_CTRL_CLHR_MASK)
+#define I2C_CTRL_CLHR_STANDARD		0
+#define I2C_CTRL_CLHR_ASYMMETRIC	1
+#define I2C_CTRL_CLHR_FAST		2
+
+#define I2C_CTRL_GCAMEN		(1 << 6)
+#define I2C_CTRL_ARBDIS		(1 << 5)
+#define I2C_CTRL_AUTOSN		(1 << 4)
+#define I2C_CTRL_AUTOSE		(1 << 3)
+#define I2C_CTRL_AUTOACK	(1 << 2)
+#define I2C_CTRL_SLAVE		(1 << 1)
+#define I2C_CTRL_EN		(1 << 0)
+
+/* I2C_CMD */
+#define I2C_CMD_CLEARPC		(1 << 7)
+#define I2C_CMD_CLEARTX		(1 << 6)
+#define I2C_CMD_ABORT		(1 << 5)
+#define I2C_CMD_CONT		(1 << 4)
+#define I2C_CMD_NACK		(1 << 3)
+#define I2C_CMD_ACK		(1 << 2)
+#define I2C_CMD_STOP		(1 << 1)
+#define I2C_CMD_START		(1 << 0)
+
+/* I2C_STATE */
+#define I2C_STATE_STATE_SHIFT	(5)
+#define I2C_STATE_STATE_MASK	(0x7 << I2C_STATE_STATE_SHIFT)
+#define I2C_STATE_STATE(v)	\
+	(((v) << I2C_STATE_STATE_SHIFT) & I2C_STATE_STATE_MASK)
+#define I2C_STATE_STATE_IDLE	0
+#define I2C_STATE_STATE_WAIT	1
+#define I2C_STATE_STATE_START	2
+#define I2C_STATE_STATE_ADDR	3
+#define I2C_STATE_STATE_ADDRACK	4
+#define I2C_STATE_STATE_DATA	5
+#define I2C_STATE_STATE_DATAACK	6
+
+#define I2C_STATE_BUSHOLD	(1 << 4)
+#define I2C_STATE_NACKED	(1 << 3)
+#define I2C_STATE_TRANSMITTER	(1 << 2)
+#define I2C_STATE_MASTER	(1 << 1)
+#define I2C_STATE_BUSY		(1 << 0)
+
+/* I2C_STATUS */
+#define I2C_STATUS_RXDATAV	(1 << 8)
+#define I2C_STATUS_TXBL		(1 << 7)
+#define I2C_STATUS_TXC		(1 << 6)
+#define I2C_STATUS_PABORT	(1 << 5)
+#define I2C_STATUS_PCONT	(1 << 4)
+#define I2C_STATUS_PNACK	(1 << 3)
+#define I2C_STATUS_PACK		(1 << 2)
+#define I2C_STATUS_PSTOP	(1 << 1)
+#define I2C_STATUS_PSTART	(1 << 0)
+
+/* I2C_CLKDIV */
+#define I2C_CLKDIV_DIV_SHIFT	(0)
+#define I2C_CLKDIV_DIV_MASK	(0xFF << I2C_CLKDIV_DIV_SHIFT)
+#define I2C_CLKDIV_DIV(v)	\
+	(((v) << I2C_CLKDIV_DIV_SHIFT) & I2C_CLKDIV_DIV_MASK)
+
+/* I2C_SADDR */
+#define I2C_SADDR_ADDR_SHIFT	(0)
+#define I2C_SADDR_ADDR_MASK	(0xFF << I2C_SADDR_ADDR_SHIFT)
+#define I2C_SADDR_ADDR(v)	\
+	(((v) << I2C_SADDR_ADDR_SHIFT) & I2C_SADDR_ADDR_MASK)
+
+/* I2C_SADDRMASK */
+#define I2C_SADDRMASK_MASK_SHIFT	(0)
+#define I2C_SADDRMASK_MASK_MASK		(0xFF << I2C_SADDRMASK_MASK_SHIFT)
+#define I2C_SADDRMASK_MASK(v)		\
+	(((v) << I2C_SADDRMASK_MASK_SHIFT) & I2C_SADDRMASK_MASK_MASK)
+
+/* I2C_IF */
+#define I2C_IF_SSTOP		(1 << 16)
+#define I2C_IF_CLTO		(1 << 15)
+#define I2C_IF_BITO		(1 << 14)
+#define I2C_IF_RXUF		(1 << 13)
+#define I2C_IF_TXOF		(1 << 12)
+#define I2C_IF_BUSHOLD		(1 << 11)
+#define I2C_IF_BUSERR		(1 << 10)
+#define I2C_IF_ARBLOST		(1 << 9)
+#define I2C_IF_MSTOP		(1 << 8)
+#define I2C_IF_NACK		(1 << 7)
+#define I2C_IF_ACK		(1 << 6)
+#define I2C_IF_RXDATAV		(1 << 5)
+#define I2C_IF_TXBL		(1 << 4)
+#define I2C_IF_TXC		(1 << 3)
+#define I2C_IF_ADDR		(1 << 2)
+#define I2C_IF_RSTART		(1 << 1)
+#define I2C_IF_START		(1 << 0)
+
+/* I2C_IFS */
+#define I2C_IFS_SSTOP		(1 << 16)
+#define I2C_IFS_CLTO		(1 << 15)
+#define I2C_IFS_BITO		(1 << 14)
+#define I2C_IFS_RXUF		(1 << 13)
+#define I2C_IFS_TXOF		(1 << 12)
+#define I2C_IFS_BUSHOLD		(1 << 11)
+#define I2C_IFS_BUSERR		(1 << 10)
+#define I2C_IFS_ARBLOST		(1 << 9)
+#define I2C_IFS_MSTOP		(1 << 8)
+#define I2C_IFS_NACK		(1 << 7)
+#define I2C_IFS_ACK		(1 << 6)
+#define I2C_IFS_RXDATAV		(1 << 5)
+#define I2C_IFS_TXBL		(1 << 4)
+#define I2C_IFS_TXC		(1 << 3)
+#define I2C_IFS_ADDR		(1 << 2)
+#define I2C_IFS_RSTART		(1 << 1)
+#define I2C_IFS_START		(1 << 0)
+
+/* I2C_IFC */
+#define I2C_IFC_SSTOP		(1 << 16)
+#define I2C_IFC_CLTO		(1 << 15)
+#define I2C_IFC_BITO		(1 << 14)
+#define I2C_IFC_RXUF		(1 << 13)
+#define I2C_IFC_TXOF		(1 << 12)
+#define I2C_IFC_BUSHOLD		(1 << 11)
+#define I2C_IFC_BUSERR		(1 << 10)
+#define I2C_IFC_ARBLOST		(1 << 9)
+#define I2C_IFC_MSTOP		(1 << 8)
+#define I2C_IFC_NACK		(1 << 7)
+#define I2C_IFC_ACK		(1 << 6)
+#define I2C_IFC_RXDATAV		(1 << 5)
+#define I2C_IFC_TXBL		(1 << 4)
+#define I2C_IFC_TXC		(1 << 3)
+#define I2C_IFC_ADDR		(1 << 2)
+#define I2C_IFC_RSTART		(1 << 1)
+#define I2C_IFC_START		(1 << 0)
+
+/* I2C_IEN */
+#define I2C_IEN_SSTOP		(1 << 16)
+#define I2C_IEN_CLTO		(1 << 15)
+#define I2C_IEN_BITO		(1 << 14)
+#define I2C_IEN_RXUF		(1 << 13)
+#define I2C_IEN_TXOF		(1 << 12)
+#define I2C_IEN_BUSHOLD		(1 << 11)
+#define I2C_IEN_BUSERR		(1 << 10)
+#define I2C_IEN_ARBLOST		(1 << 9)
+#define I2C_IEN_MSTOP		(1 << 8)
+#define I2C_IEN_NACK		(1 << 7)
+#define I2C_IEN_ACK		(1 << 6)
+#define I2C_IEN_RXDATAV		(1 << 5)
+#define I2C_IEN_TXBL		(1 << 4)
+#define I2C_IEN_TXC		(1 << 3)
+#define I2C_IEN_ADDR		(1 << 2)
+#define I2C_IEN_RSTART		(1 << 1)
+#define I2C_IEN_START		(1 << 0)
+
+/* I2C_ROUTE */
+#define I2C_ROUTE_LOCATION_SHIFT	(8)
+#define I2C_ROUTE_LOCATION_MASK		(0x7 << I2C_ROUTE_LOCATION_SHIFT)
+#define I2C_ROUTE_LOCATION(v)		\
+	(((v) << I2C_ROUTE_LOCATION_SHIFT) & I2C_ROUTE_LOCATION_MASK)
+#define I2C_ROUTE_LOCATION_LOCx(x)	I2C_ROUTE_LOCATION(x)
+#define I2C_ROUTE_LOCATION_LOC0		0
+#define I2C_ROUTE_LOCATION_LOC1		1
+#define I2C_ROUTE_LOCATION_LOC2		2
+#define I2C_ROUTE_LOCATION_LOC3		3
+#define I2C_ROUTE_LOCATION_LOC4		4
+#define I2C_ROUTE_LOCATION_LOC5		5
+#define I2C_ROUTE_LOCATION_LOC6		6
+
+#define I2C_ROUTE_SCLPEN		(1 << 1)
+#define I2C_ROUTE_SDAPEN		(1 << 0)
+
+/* I2C0 */
+#define I2C0			I2C0_BASE
+#define I2C0_CTRL		I2C_CTRL(I2C0)
+#define I2C0_CMD		I2C_CMD(I2C0)
+#define I2C0_STATE		I2C_STATE(I2C0)
+#define I2C0_STATUS		I2C_STATUS(I2C0)
+#define I2C0_CLKDIV		I2C_CLKDIV(I2C0)
+#define I2C0_SADDR		I2C_SADDR(I2C0)
+#define I2C0_SADDRMASK		I2C_SADDRMASK(I2C0)
+#define I2C0_RXDATA		I2C_RXDATA(I2C0)
+#define I2C0_RXDATAP		I2C_RXDATAP(I2C0)
+#define I2C0_TXDATA		I2C_TXDATA(I2C0)
+#define I2C0_IF			I2C_IF(I2C0)
+#define I2C0_IFS		I2C_IFS(I2C0)
+#define I2C0_IFC		I2C_IFC(I2C0)
+#define I2C0_IEN		I2C_IEN(I2C0)
+#define I2C0_ROUTE		I2C_ROUTE(I2C0)
+
+/* I2C1 */
+#define I2C1			I2C1_BASE
+#define I2C1_CTRL		I2C_CTRL(I2C1)
+#define I2C1_CMD		I2C_CMD(I2C1)
+#define I2C1_STATE		I2C_STATE(I2C1)
+#define I2C1_STATUS		I2C_STATUS(I2C1)
+#define I2C1_CLKDIV		I2C_CLKDIV(I2C1)
+#define I2C1_SADDR		I2C_SADDR(I2C1)
+#define I2C1_SADDRMASK		I2C_SADDRMASK(I2C1)
+#define I2C1_RXDATA		I2C_RXDATA(I2C1)
+#define I2C1_RXDATAP		I2C_RXDATAP(I2C1)
+#define I2C1_TXDATA		I2C_TXDATA(I2C1)
+#define I2C1_IF			I2C_IF(I2C1)
+#define I2C1_IFS		I2C_IFS(I2C1)
+#define I2C1_IFC		I2C_IFC(I2C1)
+#define I2C1_IEN		I2C_IEN(I2C1)
+#define I2C1_ROUTE		I2C_ROUTE(I2C1)
+
+/**@}*/

3rd/libopencm3/include/libopencm3/efm32/common/letimer_common.h

@@ -0,0 +1,167 @@
+/** @addtogroup letimer_defines
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/efm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/**@{*/
+
+#define LETIMER_CTRL(base)		((base) + 0x000)
+#define LETIMER_CMD(base)		((base) + 0x004)
+#define LETIMER_STATUS(base)		((base) + 0x008)
+#define LETIMER_CNT(base)		((base) + 0x00C)
+#define LETIMER_COMP0(base)		((base) + 0x010)
+#define LETIMER_COMP1(base)		((base) + 0x014)
+#define LETIMER_REP0(base)		((base) + 0x018)
+#define LETIMER_REP1(base)		((base) + 0x01C)
+#define LETIMER_IF(base)		((base) + 0x020)
+#define LETIMER_IFS(base)		((base) + 0x024)
+#define LETIMER_IFC(base)		((base) + 0x028)
+#define LETIMER_IEN(base)		((base) + 0x02C)
+#define LETIMER_FREEZE(base)		((base) + 0x030)
+#define LETIMER_SYNCBUSY(base)		((base) + 0x034)
+#define LETIMER_ROUTE(base)		((base) + 0x040)
+
+/* LETIMER_CTRL */
+#define LETIMER_CTRL_DEBUG		(1 << 12)
+#define LETIMER_CTRL_RTCC1TEN		(1 << 11)
+#define LETIMER_CTRL_RTCC0TEN		(1 << 10)
+#define LETIMER_CTRL_COMP0TOP		(1 << 9)
+#define LETIMER_CTRL_BUFTOP		(1 << 8)
+#define LETIMER_CTRL_OPOL1		(1 << 7)
+#define LETIMER_CTRL_OPOL0		(1 << 6)
+
+#define LETIMER_CTRL_UFOA1_SHIFT	(4)
+#define LETIMER_CTRL_UFOA1_MASK		(0x3 << LETIMER_CTRL_UFOA1_SHIFT)
+#define LETIMER_CTRL_UFOA1(v)		\
+	(((v) << LETIMER_CTRL_UFOA1_SHIFT) & LETIMER_CTRL_UFOA1_MASK)
+#define LETIMER_CTRL_UFOA1_NONE		0
+#define LETIMER_CTRL_UFOA1_TOGGLE	1
+#define LETIMER_CTRL_UFOA1_PULSE	2
+#define LETIMER_CTRL_UFOA1_PWM		3
+
+#define LETIMER_CTRL_UFOA0_SHIFT	(2)
+#define LETIMER_CTRL_UFOA0_MASK		(0x3 << LETIMER_CTRL_UFOA0_SHIFT)
+#define LETIMER_CTRL_UFOA0(v)		\
+	(((v) << LETIMER_CTRL_UFOA0_SHIFT) & LETIMER_CTRL_UFOA0_MASK)
+#define LETIMER_CTRL_UFOA0_NONE		0
+#define LETIMER_CTRL_UFOA0_TOGGLE	1
+#define LETIMER_CTRL_UFOA0_PULSE	2
+#define LETIMER_CTRL_UFOA0_PWM		3
+
+#define LETIMER_CTRL_REPMODE_SHIFT	(2)
+#define LETIMER_CTRL_REPMODE_MASK	(0x3 << LETIMER_CTRL_REPMODE_SHIFT)
+#define LETIMER_CTRL_REPMODE(v)		\
+	(((v) << LETIMER_CTRL_REPMODE_SHIFT) & LETIMER_CTRL_REPMODE_MASK)
+#define LETIMER_CTRL_REPMODE_FREE	0
+#define LETIMER_CTRL_REPMODE_ONESHOT	1
+#define LETIMER_CTRL_REPMODE_BUFFERED	2
+#define LETIMER_CTRL_REPMODE_DOUBLE	3
+#define LETIMER_CTRL_REPMODE_ONE_SHOT	LETIMER_CTRL_REPMODE_ONESHOT
+
+/* LETIMER_CMD */
+#define LETIMER_CMD_CTO1		(1 << 4)
+#define LETIMER_CMD_CTO0		(1 << 3)
+#define LETIMER_CMD_CLEAR		(1 << 2)
+#define LETIMER_CMD_STOP		(1 << 1)
+#define LETIMER_CMD_START		(1 << 0)
+
+/* LETIMER_STATUS */
+#define LETIMER_STATUS_RUNNING		(1 << 0)
+
+/* LETIMER_IF */
+#define LETIMER_IF_REP1			(1 << 4)
+#define LETIMER_IF_REP0			(1 << 3)
+#define LETIMER_IF_UF			(1 << 2)
+#define LETIMER_IF_COMP1		(1 << 1)
+#define LETIMER_IF_COMP0		(1 << 0)
+
+/* LETIMER_IFS */
+#define LETIMER_IFS_REP1		(1 << 4)
+#define LETIMER_IFS_REP0		(1 << 3)
+#define LETIMER_IFS_UF			(1 << 2)
+#define LETIMER_IFS_COMP1		(1 << 1)
+#define LETIMER_IFS_COMP0		(1 << 0)
+
+/* LETIMER_IFC */
+#define LETIMER_IFC_REP1		(1 << 4)
+#define LETIMER_IFC_REP0		(1 << 3)
+#define LETIMER_IFC_UF			(1 << 2)
+#define LETIMER_IFC_COMP1		(1 << 1)
+#define LETIMER_IFC_COMP0		(1 << 0)
+
+/* LETIMER_IFE */
+#define LETIMER_IFE_REP1		(1 << 4)
+#define LETIMER_IFE_REP0		(1 << 3)
+#define LETIMER_IFE_UF			(1 << 2)
+#define LETIMER_IFE_COMP1		(1 << 1)
+#define LETIMER_IFE_COMP0		(1 << 0)
+
+/* LETIMER_FREEZE */
+#define LETIMER_FREEZE_REGFREEZE	(1 << 0)
+
+/* LETIMER_SYNCBUSY */
+#define LETIMER_SYNCBUSY_REP1		(1 << 5)
+#define LETIMER_SYNCBUSY_REP0		(1 << 4)
+#define LETIMER_SYNCBUSY_COMP1		(1 << 3)
+#define LETIMER_SYNCBUSY_COMP0		(1 << 2)
+#define LETIMER_SYNCBUSY_CMD		(1 << 1)
+#define LETIMER_SYNCBUSY_CTRL		(1 << 0)
+
+/* LETIMER_ROUTE */
+#define LETIMER_ROUTE_LOCATION_SHIFT	(8)
+#define LETIMER_ROUTE_LOCATION_MASK	(0x7 << LETIMER_ROUTE_LOCATION_SHIFT)
+#define LETIMER_ROUTE_LOCATION(v)	\
+	(((v) << LETIMER_ROUTE_LOCATION_SHIFT) & LETIMER_ROUTE_LOCATION_MASK)
+#define LETIMER_ROUTE_LOCATION_LOCx(x)	LETIMER_ROUTE_LOCATION(x)
+#define LETIMER_ROUTE_LOCATION_LOC0	0
+#define LETIMER_ROUTE_LOCATION_LOC1	1
+#define LETIMER_ROUTE_LOCATION_LOC2	2
+#define LETIMER_ROUTE_LOCATION_LOC3	3
+#define LETIMER_ROUTE_LOCATION_LOC4	4
+#define LETIMER_ROUTE_LOCATION_LOC5	5
+#define LETIMER_ROUTE_LOCATION_LOC6	6
+#define LETIMER_ROUTE_LOCATION_LOC7	7
+
+#define LETIMER_ROUTE_OUT1PEN		(1 << 1)
+#define LETIMER_ROUTE_OUT0PEN		(1 << 0)
+
+/* LETIMER0 */
+#define LETIMER0			LETIMER0_BASE
+#define LETIMER0_CTRL			LETIMER_CTRL(LETIMER0)
+#define LETIMER0_CMD			LETIMER_CMD(LETIMER0)
+#define LETIMER0_STATUS			LETIMER_STATUS(LETIMER0)
+#define LETIMER0_CNT			LETIMER_CNT(LETIMER0)
+#define LETIMER0_COMP0			LETIMER_COMP0(LETIMER0)
+#define LETIMER0_COMP1			LETIMER_COMP1(LETIMER0)
+#define LETIMER0_REP0			LETIMER_REP0(LETIMER0)
+#define LETIMER0_REP1			LETIMER_REP1(LETIMER0)
+#define LETIMER0_IF			LETIMER_IF(LETIMER0)
+#define LETIMER0_IFS			LETIMER_IFS(LETIMER0)
+#define LETIMER0_IFC			LETIMER_IFC(LETIMER0)
+#define LETIMER0_IEN			LETIMER_IEN(LETIMER0)
+#define LETIMER0_FREEZE			LETIMER_FREEZE(LETIMER0)
+#define LETIMER0_SYNCBUSY		LETIMER_SYNCBUSY(LETIMER0)
+#define LETIMER0_ROUTE			LETIMER_ROUTE(LETIMER0)
+
+/**@}*/

3rd/libopencm3/include/libopencm3/efm32/common/msc_common.h

@@ -0,0 +1,156 @@
+/** @addtogroup msc_defines
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/efm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/**@{*/
+
+#define MSC_CTRL		MMIO32(MSC_BASE + 0x000)
+#define MSC_READCTRL		MMIO32(MSC_BASE + 0x004)
+#define MSC_WRITECTRL		MMIO32(MSC_BASE + 0x008)
+#define MSC_WRITECMD		MMIO32(MSC_BASE + 0x00C)
+#define MSC_ADDRB		MMIO32(MSC_BASE + 0x010)
+#define MSC_WDATA		MMIO32(MSC_BASE + 0x018)
+#define MSC_STATUS		MMIO32(MSC_BASE + 0x01C)
+#define MSC_IF			MMIO32(MSC_BASE + 0x02C)
+#define MSC_IFS			MMIO32(MSC_BASE + 0x030)
+#define MSC_IFC			MMIO32(MSC_BASE + 0x034)
+#define MSC_IEN			MMIO32(MSC_BASE + 0x038)
+#define MSC_LOCK		MMIO32(MSC_BASE + 0x03C)
+#define MSC_CMD			MMIO32(MSC_BASE + 0x040)
+#define MSC_CACHEHITS		MMIO32(MSC_BASE + 0x044)
+#define MSC_CACHEMISSES		MMIO32(MSC_BASE + 0x048)
+#define MSC_TIMEBASE		MMIO32(MSC_BASE + 0x050)
+#define MSC_MASSLOCK		MMIO32(MSC_BASE + 0x054)
+
+/* MSC_CTRL */
+#define MSC_CTRL_BUSFAULT	(1 << 0)
+
+/* MSC_READCTRL */
+#define MSC_READCTRL_BUSSTRATEGY_SHIFT	(16)
+#define MSC_READCTRL_BUSSTRATEGY_MASK	\
+	(0x3 << MSC_READCTRL_BUSSTRATEGY_SHIFT)
+#define MSC_READCTRL_BUSSTRATEGY(v)	\
+	(((v) << MSC_READCTRL_BUSSTRATEGY_SHIFT) & \
+	MSC_READCTRL_BUSSTRATEGY_MASK)
+
+#define MSC_READCTRL_BUSSTRATEGY_CPU	MSC_READCTRL_BUSSTRATEGY(0)
+#define MSC_READCTRL_BUSSTRATEGY_DMA	MSC_READCTRL_BUSSTRATEGY(1)
+#define MSC_READCTRL_BUSSTRATEGY_DMAEM1	MSC_READCTRL_BUSSTRATEGY(2)
+#define MSC_READCTRL_BUSSTRATEGY_NONE	MSC_READCTRL_BUSSTRATEGY(3)
+
+#define MSC_READCTRL_RAMCEN	(1 << 7)
+#define MSC_READCTRL_EBICDIS	(1 << 6)
+#define MSC_READCTRL_ICCDIS	(1 << 5)
+#define MSC_READCTRL_AIDIS	(1 << 4)
+#define MSC_READCTRL_IFCDIS	(1 << 3)
+
+#define MSC_READCTRL_MODE_SHIFT		(0)
+#define MSC_READCTRL_MODE_MASK		(0x7 << MSC_READCTRL_MODE_SHIFT)
+#define MSC_READCTRL_MODE(v)		\
+	(((v) << MSC_READCTRL_MODE_SHIFT) & MSC_READCTRL_MODE_MASK)
+#define MSC_READCTRL_MODE_WS0		0
+#define MSC_READCTRL_MODE_WS1		1
+#define MSC_READCTRL_MODE_WS0SCBTP	2
+#define MSC_READCTRL_MODE_WS1SCBTP	3
+#define MSC_READCTRL_MODE_WS2		4
+#define MSC_READCTRL_MODE_WS2SCBTP	5
+
+/* MSC_WRITECTRL */
+#define MSC_WRITECTRL_IRQERASEABORT	(1 << 1)
+#define MSC_WRITECTRL_WREN		(1 << 0)
+
+/* MSC_WRITECMD */
+#define MSC_WRITECMD_CLEARWDATA		(1 << 12)
+#define MSC_WRITECMD_ERASEMAIN0		(1 << 8)
+#define MSC_WRITECMD_ERASEABORT		(1 << 5)
+#define MSC_WRITECMD_WRITETRIG		(1 << 4)
+#define MSC_WRITECMD_WRITEONCE		(1 << 3)
+#define MSC_WRITECMD_WRITEEND		(1 << 2)
+#define MSC_WRITECMD_ERASEPAGE		(1 << 1)
+#define MSC_WRITECMD_LADDRIM		(1 << 0)
+
+/* MSC_STATUS */
+#define MSC_STATUS_PCRUNNING		(1 << 6)
+#define MSC_STATUS_ERASEABORTED		(1 << 5)
+#define MSC_STATUS_WORDTIMEOUT		(1 << 4)
+#define MSC_STATUS_WDATAREADY		(1 << 3)
+#define MSC_STATUS_INVADDR		(1 << 2)
+#define MSC_STATUS_LOCKED		(1 << 1)
+#define MSC_STATUS_BUSY			(1 << 0)
+
+/* MSC_IF */
+#define MSC_IF_CMOF		(1 << 3)
+#define MSC_IF_CHOF		(1 << 2)
+#define MSC_IF_WRITE		(1 << 1)
+#define MSC_IF_ERASE		(1 << 0)
+
+/* MSC_IFS */
+#define MSC_IFS_CMOF		(1 << 3)
+#define MSC_IFS_CHOF		(1 << 2)
+#define MSC_IFS_WRITE		(1 << 1)
+#define MSC_IFS_ERASE		(1 << 0)
+
+/* MSC_IFC */
+#define MSC_IFC_CMOF		(1 << 3)
+#define MSC_IFC_CHOF		(1 << 2)
+#define MSC_IFC_WRITE		(1 << 1)
+#define MSC_IFC_ERASE		(1 << 0)
+
+/* MSC_*IEN */
+#define MSC_IEN_CMOF		(1 << 3)
+#define MSC_IEN_CHOF		(1 << 2)
+#define MSC_IEN_WRITE		(1 << 1)
+#define MSC_IEN_ERASE		(1 << 0)
+
+/* MSC_LOCK */
+#define MSC_LOCK_LOCKKEY_SHIFT		(0)
+#define MSC_LOCK_LOCKKEY(v)		((v) << MSC_LOCK_LOCKKEY_SHIFT)
+#define MSC_LOCK_LOCKKEY_UNLOCKED	MSC_LOCK_LOCKKEY(0)
+#define MSC_LOCK_LOCKKEY_LOCKED		MSC_LOCK_LOCKKEY(1)
+#define MSC_LOCK_LOCKKEY_LOCK		MSC_LOCK_LOCKKEY(0)
+#define MSC_LOCK_LOCKKEY_UNLOCK		MSC_LOCK_LOCKKEY(0x1B71)
+
+/* MSC_CMD */
+#define MSC_CMD_STOPPC			(1 << 2)
+#define MSC_CMD_STARTPC			(1 << 1)
+#define MSC_CMD_INVCACHE		(1 << 0)
+
+/* MSC_TIMEBASE */
+#define MSC_TIMEBASE_PERIOD		(1 << 16)
+
+#define MSC_TIMEBASE_BASE_SHIFT		(0)
+#define MSC_TIMEBASE_BASE_MASK		(0x3F << MSC_TIMEBASE_BASE_SHIFT)
+#define MSC_TIMEBASE_BASE(v)		\
+	(((v) << MSC_TIMEBASE_BASE_SHIFT) & MSC_TIMEBASE_BASE_MASK)
+
+/* MSC_MASSLOCK */
+#define MSC_MASSLOCK_LOCKKEY_SHIFT	(0)
+#define MSC_MASSLOCK_LOCKKEY(v)		((v) << MSC_MASSLOCK_LOCKKEY_SHIFT)
+#define MSC_MASSLOCK_LOCKKEY_UNLOCKED	MSC_MASSLOCK_LOCKKEY(0)
+#define MSC_MASSLOCK_LOCKKEY_LOCKED	MSC_MASSLOCK_LOCKKEY(1)
+#define MSC_MASSLOCK_LOCKKEY_LOCK	MSC_MASSLOCK_LOCKKEY(0)
+#define MSC_MASSLOCK_LOCKKEY_UNLOCK	MSC_MASSLOCK_LOCKKEY(0x631A)
+
+/**@}*/

3rd/libopencm3/include/libopencm3/efm32/common/opamp_common.h

@@ -0,0 +1,21 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* OpAmp register are in dac.h */
+#include <libopencm3/efm32/dac.h>

3rd/libopencm3/include/libopencm3/efm32/common/prs_common.h

@@ -0,0 +1,365 @@
+/** @addtogroup prs_defines
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/efm32/memorymap.h>
+
+/**@{*/
+
+#define PRS_SWPULSE		MMIO32(PRS_BASE + 0x000)
+#define PRS_SWLEVEL		MMIO32(PRS_BASE + 0x004)
+#define PRS_ROUTE		MMIO32(PRS_BASE + 0x008)
+#define PRS_CHx_CTRL(x)		MMIO32(PRS_BASE + 0x010 + (0x004 * (x)))
+#define PRS_CH0_CTRL		PRS_CHx_CTRL(0)
+#define PRS_CH1_CTRL		PRS_CHx_CTRL(1)
+#define PRS_CH2_CTRL		PRS_CHx_CTRL(2)
+#define PRS_CH3_CTRL		PRS_CHx_CTRL(3)
+#define PRS_CH4_CTRL		PRS_CHx_CTRL(4)
+#define PRS_CH5_CTRL		PRS_CHx_CTRL(5)
+#define PRS_CH6_CTRL		PRS_CHx_CTRL(6)
+#define PRS_CH7_CTRL		PRS_CHx_CTRL(71)
+#define PRS_CH8_CTRL		PRS_CHx_CTRL(8)
+#define PRS_CH9_CTRL		PRS_CHx_CTRL(9)
+#define PRS_CH10_CTRL		PRS_CHx_CTRL(10)
+#define PRS_CH11_CTRL		PRS_CHx_CTRL(11)
+
+/* PRS_SWPULSE */
+#define PRS_SWPULSE_CHxPULSE(x)	(1 << (x))
+#define PRS_SWPULSE_CH0PULSE	PRS_SWPULSE_CHxPULSE(0)
+#define PRS_SWPULSE_CH1PULSE	PRS_SWPULSE_CHxPULSE(1)
+#define PRS_SWPULSE_CH2PULSE	PRS_SWPULSE_CHxPULSE(2)
+#define PRS_SWPULSE_CH3PULSE	PRS_SWPULSE_CHxPULSE(3)
+#define PRS_SWPULSE_CH4PULSE	PRS_SWPULSE_CHxPULSE(4)
+#define PRS_SWPULSE_CH5PULSE	PRS_SWPULSE_CHxPULSE(5)
+#define PRS_SWPULSE_CH6PULSE	PRS_SWPULSE_CHxPULSE(6)
+#define PRS_SWPULSE_CH7PULSE	PRS_SWPULSE_CHxPULSE(7)
+#define PRS_SWPULSE_CH8PULSE	PRS_SWPULSE_CHxPULSE(8)
+#define PRS_SWPULSE_CH9PULSE	PRS_SWPULSE_CHxPULSE(9)
+#define PRS_SWPULSE_CH10PULSE	PRS_SWPULSE_CHxPULSE(10)
+#define PRS_SWPULSE_CH11PULSE	PRS_SWPULSE_CHxPULSE(11)
+
+/* PRS_SWLEVEL */
+#define PRS_SWLEVEL_CHxLEVEL(x)	(1 << (x))
+#define PRS_SWLEVEL_CH0LEVEL	PRS_SWLEVEL_CHxLEVEL(0)
+#define PRS_SWLEVEL_CH1LEVEL	PRS_SWLEVEL_CHxLEVEL(1)
+#define PRS_SWLEVEL_CH2LEVEL	PRS_SWLEVEL_CHxLEVEL(2)
+#define PRS_SWLEVEL_CH3LEVEL	PRS_SWLEVEL_CHxLEVEL(3)
+#define PRS_SWLEVEL_CH4LEVEL	PRS_SWLEVEL_CHxLEVEL(4)
+#define PRS_SWLEVEL_CH5LEVEL	PRS_SWLEVEL_CHxLEVEL(5)
+#define PRS_SWLEVEL_CH6LEVEL	PRS_SWLEVEL_CHxLEVEL(6)
+#define PRS_SWLEVEL_CH7LEVEL	PRS_SWLEVEL_CHxLEVEL(7)
+#define PRS_SWLEVEL_CH8LEVEL	PRS_SWLEVEL_CHxLEVEL(8)
+#define PRS_SWLEVEL_CH9LEVEL	PRS_SWLEVEL_CHxLEVEL(9)
+#define PRS_SWLEVEL_CH10LEVEL	PRS_SWLEVEL_CHxLEVEL(10)
+#define PRS_SWLEVEL_CH11LEVEL	PRS_SWLEVEL_CHxLEVEL(11)
+
+/* PRS_ROUTE */
+#define PRS_ROUTE_LOCATION_SHIFT	(8)
+#define PRS_ROUTE_LOCATION_MASK		(0x7 << PRS_ROUTE_LOCATION_SHIFT)
+#define PRS_ROUTE_LOCATION(v)		\
+	(((v) << PRS_ROUTE_LOCATION_SHIFT) & PRS_ROUTE_LOCATION_MASK)
+#define PRS_ROUTE_LOCATION_LOCx(x)	PRS_ROUTE_LOCATION(x)
+#define PRS_ROUTE_LOCATION_LOC0		0
+#define PRS_ROUTE_LOCATION_LOC1		1
+
+#define PRS_ROUTE_CHxPEN(x)		(1 << (x))
+#define PRS_ROUTE_CH3PEN		PRS_ROUTE_CHxPEN(3)
+#define PRS_ROUTE_CH2PEN		PRS_ROUTE_CHxPEN(2)
+#define PRS_ROUTE_CH1PEN		PRS_ROUTE_CHxPEN(1)
+#define PRS_ROUTE_CH0PEN		PRS_ROUTE_CHxPEN(0)
+
+/* PRS_CHx_CTRL */
+#define PRS_CH_CTRL_ASYNC		(1 << 28)
+
+#define PRS_CH_CTRL_EDSEL_SHIFT		(24)
+#define PRS_CH_CTRL_EDSEL_MASK		(0x3 << PRS_CH_CTRL_EDSEL_SHIFT)
+#define PRS_CH_CTRL_EDSEL_OFF		(0 << PRS_CH_CTRL_EDSEL_SHIFT)
+#define PRS_CH_CTRL_EDSEL_POSEDGE	(1 << PRS_CH_CTRL_EDSEL_SHIFT)
+#define PRS_CH_CTRL_EDSEL_NEGEDGE	(2 << PRS_CH_CTRL_EDSEL_SHIFT)
+#define PRS_CH_CTRL_EDSEL_BOTHEDGES	(3 << PRS_CH_CTRL_EDSEL_SHIFT)
+
+#define PRS_CH_CTRL_SOURCESEL_SHIFT	(16)
+#define PRS_CH_CTRL_SOURCESEL_MASK	(0x3F << PRS_CH_CTRL_SOURCESEL_SHIFT)
+#define PRS_CH_CTRL_SOURCESEL(v)	\
+	(((v) << PRS_CH_CTRL_SOURCESEL_SHIFT) & PRS_CH_CTRL_SOURCESEL_MASK)
+#define PRS_CH_CTRL_SOURCESEL_NONE	0b000000
+#define PRS_CH_CTRL_SOURCESEL_VCMP	0b000001
+#define PRS_CH_CTRL_SOURCESEL_ACMP0	0b000010
+#define PRS_CH_CTRL_SOURCESEL_ACMP1	0b000011
+#define PRS_CH_CTRL_SOURCESEL_DAC0	0b000110
+#define PRS_CH_CTRL_SOURCESEL_ADC0	0b001000
+#define PRS_CH_CTRL_SOURCESEL_USART0	0b010000
+#define PRS_CH_CTRL_SOURCESEL_USART1	0b010001
+#define PRS_CH_CTRL_SOURCESEL_USART2	0b010010
+#define PRS_CH_CTRL_SOURCESEL_TIMER0	0b011100
+#define PRS_CH_CTRL_SOURCESEL_TIMER1	0b011101
+#define PRS_CH_CTRL_SOURCESEL_TIMER2	0b011110
+#define PRS_CH_CTRL_SOURCESEL_TIMER3	0b011111
+#define PRS_CH_CTRL_SOURCESEL_USB	0b100100
+#define PRS_CH_CTRL_SOURCESEL_RTC	0b101000
+#define PRS_CH_CTRL_SOURCESEL_UART0	0b101001
+#define PRS_CH_CTRL_SOURCESEL_UART1	0b101010
+#define PRS_CH_CTRL_SOURCESEL_GPIOL	0b110000
+#define PRS_CH_CTRL_SOURCESEL_GPIOH	0b110001
+#define PRS_CH_CTRL_SOURCESEL_LETIMER0	0b110100
+#define PRS_CH_CTRL_SOURCESEL_BURTC	0b110111
+#define PRS_CH_CTRL_SOURCESEL_LESENSEL	0b111001
+#define PRS_CH_CTRL_SOURCESEL_LESENSEH	0b111010
+#define PRS_CH_CTRL_SOURCESEL_LESENSED	0b111011
+
+#define PRS_CH_CTRL_SIGSEL_SHIFT	(0)
+#define PRS_CH_CTRL_SIGSEL_MASK		(0x7 << PRS_CH_CTRL_SIGSEL_SHIFT)
+#define PRS_CH_CTRL_SIGSEL(v)		\
+	(((v) << PRS_CH_CTRL_SIGSEL_SHIFT) & PRS_CH_CTRL_SIGSEL_MASK)
+#define PRS_CH_CTRL_SIGSEL_OFF			0
+#define PRS_CH_CTRL_SIGSEL_VCMPOUT		0
+#define PRS_CH_CTRL_SIGSEL_ACMP0OUT		0
+#define PRS_CH_CTRL_SIGSEL_ACMP1OUT		0
+#define PRS_CH_CTRL_SIGSEL_DAC0CH0		0
+#define PRS_CH_CTRL_SIGSEL_DAC0CH1		1
+#define PRS_CH_CTRL_SIGSEL_ADCSINGLE		0
+#define PRS_CH_CTRL_SIGSEL_ADCSCAN		1
+#define PRS_CH_CTRL_SIGSEL_USART0IRTX		0
+#define PRS_CH_CTRL_SIGSEL_USART0TXC		1
+#define PRS_CH_CTRL_SIGSEL_USART0RXDATA		2
+#define PRS_CH_CTRL_SIGSEL_USART1TXC		1
+#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV	2
+#define PRS_CH_CTRL_SIGSEL_USART2TXC		1
+#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV	2
+#define PRS_CH_CTRL_SIGSEL_TIMER0UF		0
+#define PRS_CH_CTRL_SIGSEL_TIMER0OF		1
+#define PRS_CH_CTRL_SIGSEL_TIMER0CC0		2
+#define PRS_CH_CTRL_SIGSEL_TIMER0CC1		3
+#define PRS_CH_CTRL_SIGSEL_TIMER0CC2		4
+#define PRS_CH_CTRL_SIGSEL_TIMER1UF		0
+#define PRS_CH_CTRL_SIGSEL_TIMER1OF		1
+#define PRS_CH_CTRL_SIGSEL_TIMER1CC0		2
+#define PRS_CH_CTRL_SIGSEL_TIMER1CC1		3
+#define PRS_CH_CTRL_SIGSEL_TIMER1CC2		4
+#define PRS_CH_CTRL_SIGSEL_TIMER2UF		0
+#define PRS_CH_CTRL_SIGSEL_TIMER2OF		1
+#define PRS_CH_CTRL_SIGSEL_TIMER2CC0		2
+#define PRS_CH_CTRL_SIGSEL_TIMER2CC1		3
+#define PRS_CH_CTRL_SIGSEL_TIMER2CC2		4
+#define PRS_CH_CTRL_SIGSEL_TIMER3UF		0
+#define PRS_CH_CTRL_SIGSEL_TIMER3OF		1
+#define PRS_CH_CTRL_SIGSEL_TIMER3CC0		2
+#define PRS_CH_CTRL_SIGSEL_TIMER3CC1		3
+#define PRS_CH_CTRL_SIGSEL_TIMER3CC2		4
+#define PRS_CH_CTRL_SIGSEL_USBSOF		0
+#define PRS_CH_CTRL_SIGSEL_USBSOFSR		1
+#define PRS_CH_CTRL_SIGSEL_RTCOF		0
+#define PRS_CH_CTRL_SIGSEL_RTCCOMP0		1
+#define PRS_CH_CTRL_SIGSEL_RTCCOMP1		2
+#define PRS_CH_CTRL_SIGSEL_UART0TXC		1
+#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV		2
+#define PRS_CH_CTRL_SIGSEL_UART1TXC		1
+#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV		2
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN0		0
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN1		1
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN2		2
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN3		3
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN4		4
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN5		5
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN6		6
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN7		7
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN8		0
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN9		1
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN10		2
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN11		3
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN12		4
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN13		5
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN14		6
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN15		7
+#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0		0
+#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1		1
+#define PRS_CH_CTRL_SIGSEL_BURTCOF		0
+#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0		1
+#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0	0
+#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1	1
+#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2	2
+#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3	3
+#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4	4
+#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5	5
+#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6	6
+#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7	7
+#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8	0
+#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9	1
+#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10	2
+#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11	3
+#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12	4
+#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13	5
+#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14	6
+#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15	7
+#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0		0
+#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1		1
+#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2		2
+
+/* generic of above */
+#define PRS_CH_CTRL_SIGSEL_VCMP_OUT		0
+#define PRS_CH_CTRL_SIGSEL_ACMP_OUT		0
+#define PRS_CH_CTRL_SIGSEL_DAC_CHx(x)		PRS_CH_CTRL_SIGSEL(x)
+#define PRS_CH_CTRL_SIGSEL_DAC_CH0		0
+#define PRS_CH_CTRL_SIGSEL_DAC_CH1		1
+#define PRS_CH_CTRL_SIGSEL_ADC_SINGLE		0
+#define PRS_CH_CTRL_SIGSEL_ADC_SCAN		1
+#define PRS_CH_CTRL_SIGSEL_USART_IRTX		0
+#define PRS_CH_CTRL_SIGSEL_USART_TXC		1
+#define PRS_CH_CTRL_SIGSEL_USART_RXDATAV	2
+#define PRS_CH_CTRL_SIGSEL_TIMER_UF		0
+#define PRS_CH_CTRL_SIGSEL_TIMER_OF		1
+#define PRS_CH_CTRL_SIGSEL_TIMER_CCx(x)		PRS_CH_CTRL_SIGSEL((x) + 2)
+#define PRS_CH_CTRL_SIGSEL_TIMER_CC0		PRS_CH_CTRL_SIGSEL_TIMER_CCx(0)
+#define PRS_CH_CTRL_SIGSEL_TIMER_CC1		PRS_CH_CTRL_SIGSEL_TIMER_CCx(1)
+#define PRS_CH_CTRL_SIGSEL_TIMER_CC2		PRS_CH_CTRL_SIGSEL_TIMER_CCx(2)
+#define PRS_CH_CTRL_SIGSEL_USB_SOF		0
+#define PRS_CH_CTRL_SIGSEL_USB_SOFSR		1
+#define PRS_CH_CTRL_SIGSEL_RTC_OF		0
+#define PRS_CH_CTRL_SIGSEL_RTC_COMPx(x)		PRS_CH_CTRL_SIGSEL((x) + 1)
+#define PRS_CH_CTRL_SIGSEL_RTC_COMP0		PRS_CH_CTRL_SIGSEL_RTC_COMPx(0)
+#define PRS_CH_CTRL_SIGSEL_RTC_COMP1		PRS_CH_CTRL_SIGSEL_RTC_COMPx(1)
+#define PRS_CH_CTRL_SIGSEL_UART_TXC		1
+#define PRS_CH_CTRL_SIGSEL_UART_RXDATAV		2
+#define PRS_CH_CTRL_SIGSEL_GPIOL_PINx(x)	PRS_CH_CTRL_SIGSEL(x)
+#define PRS_CH_CTRL_SIGSEL_GPIO_PIN0	\
+	0
+#define PRS_CH_CTRL_SIGSEL_GPIO_PIN1	\
+	1
+#define PRS_CH_CTRL_SIGSEL_GPIO_PIN2	\
+	2
+#define PRS_CH_CTRL_SIGSEL_GPIO_PIN3	\
+	3
+#define PRS_CH_CTRL_SIGSEL_GPIO_PIN4	\
+	4
+#define PRS_CH_CTRL_SIGSEL_GPIO_PIN5	\
+	5
+#define PRS_CH_CTRL_SIGSEL_GPIO_PIN6	\
+	6
+#define PRS_CH_CTRL_SIGSEL_GPIO_PIN7	\
+	7
+#define PRS_CH_CTRL_SIGSEL_GPIOH_PINx(x)	PRS_CH_CTRL_SIGSEL((x) - 8)
+#define PRS_CH_CTRL_SIGSEL_GPIO_PIN8	\
+	PRS_CH_CTRL_SIGSEL_GPIOH_PINx(8)
+#define PRS_CH_CTRL_SIGSEL_GPIO_PIN9	\
+	PRS_CH_CTRL_SIGSEL_GPIOH_PINx(9)
+#define PRS_CH_CTRL_SIGSEL_GPIO_PIN10	\
+	PRS_CH_CTRL_SIGSEL_GPIOH_PINx(10)
+#define PRS_CH_CTRL_SIGSEL_GPIO_PIN11	\
+	PRS_CH_CTRL_SIGSEL_GPIOH_PINx(11)
+#define PRS_CH_CTRL_SIGSEL_GPIO_PIN12	\
+	PRS_CH_CTRL_SIGSEL_GPIOH_PINx(12)
+#define PRS_CH_CTRL_SIGSEL_GPIO_PIN13	\
+	PRS_CH_CTRL_SIGSEL_GPIOH_PINx(13)
+#define PRS_CH_CTRL_SIGSEL_GPIO_PIN14	\
+	PRS_CH_CTRL_SIGSEL_GPIOH_PINx(14)
+#define PRS_CH_CTRL_SIGSEL_GPIO_PIN15	\
+	PRS_CH_CTRL_SIGSEL_GPIOH_PINx(15)
+#define PRS_CH_CTRL_SIGSEL_LETIMER_CHx(x)	PRS_CH_CTRL_SIGSEL(x)
+#define PRS_CH_CTRL_SIGSEL_LETIMER_CH0	\
+	0
+#define PRS_CH_CTRL_SIGSEL_LETIMER_CH1	\
+	1
+#define PRS_CH_CTRL_SIGSEL_BURTC_OF		0
+#define PRS_CH_CTRL_SIGSEL_BURTC_COMP0		1
+#define PRS_CH_CTRL_SIGSEL_LESENSEL_SCANRESx(x)		PRS_CH_CTRL_SIGSEL(x)
+#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES0	\
+	0
+#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES1	\
+	1
+#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES2	\
+	2
+#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES3	\
+	3
+#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES4	\
+	4
+#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES5	\
+	5
+#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES6	\
+	6
+#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES7	\
+	7
+#define PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(x)	\
+	PRS_CH_CTRL_SIGSEL((x) - 8)
+#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES8	\
+	PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(8)
+#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES9	\
+	PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(9)
+#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES10	\
+	PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(10)
+#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES11	\
+	PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(11)
+#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES12	\
+	PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(12)
+#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES13	\
+	PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(13)
+#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES14	\
+	PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(14)
+#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES15	\
+	PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(15)
+#define PRS_CH_CTRL_SIGSEL_LESENSED_DECx(x)	PRS_CH_CTRL_SIGSEL(x)
+#define PRS_CH_CTRL_SIGSEL_LESENSE_DEC0	\
+	0
+#define PRS_CH_CTRL_SIGSEL_LESENSE_DEC1	\
+	1
+#define PRS_CH_CTRL_SIGSEL_LESENSE_DEC2	\
+	2
+
+/** @defgroup prs_ch PRS Channel Number
+@ingroup prs_defines
+
+@{*/
+enum prs_ch {
+	PRS_CH0 = 0,
+	PRS_CH1,
+	PRS_CH2,
+	PRS_CH3,
+	PRS_CH4,
+	PRS_CH5,
+	PRS_CH6,
+	PRS_CH7,
+	PRS_CH8,
+	PRS_CH9,
+	PRS_CH10,
+	PRS_CH11
+};
+/**@}*/
+
+BEGIN_DECLS
+
+void prs_enable_gpio_output(enum prs_ch ch);
+void prs_disable_gpio_output(enum prs_ch ch);
+void prs_set_output_loc(uint32_t loc);
+
+void prs_software_pulse(enum prs_ch ch);
+void prs_software_level_high(enum prs_ch ch);
+void prs_software_level_low(enum prs_ch ch);
+
+void prs_enable_async(enum prs_ch ch);
+void prs_disable_async(enum prs_ch ch);
+void prs_set_edge(enum prs_ch ch, uint32_t edge);
+void prs_set_source(enum prs_ch ch, uint32_t source);
+void prs_set_signal(enum prs_ch ch, uint32_t sig);
+
+END_DECLS
+
+/**@}*/

3rd/libopencm3/include/libopencm3/efm32/common/rmu_common.h

@@ -0,0 +1,58 @@
+/** @addtogroup rmu_defines
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/efm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/**@{*/
+
+#define RMU_CTRL		MMIO32(RMU_BASE + 0x00)
+#define RMU_RSTCAUSE	MMIO32(RMU_BASE + 0x04)
+#define RMU_CMD			MMIO32(RMU_BASE + 0x08)
+
+/* RMU_CTRL */
+#define RMU_CTRL_BURSTEN	(1 << 1)
+#define RMU_CTRL_LOCKUPRDIS	(1 << 0)
+
+/* RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_BUMODERST		(1 << 15)
+#define RMU_RSTCAUSE_BUBODREG		(1 << 14)
+#define RMU_RSTCAUSE_BUBODUNREG		(1 << 13)
+#define RMU_RSTCAUSE_BUBODBUVIN		(1 << 12)
+#define RMU_RSTCAUSE_BUBODVDDDREG	(1 << 11)
+#define RMU_RSTCAUSE_BODAVDD1		(1 << 10)
+#define RMU_RSTCAUSE_BODAVDD0		(1 << 9)
+#define RMU_RSTCAUSE_EM4WURST		(1 << 8)
+#define RMU_RSTCAUSE_EM4RST			(1 << 7)
+#define RMU_RSTCAUSE_SYSREQRST		(1 << 6)
+#define RMU_RSTCAUSE_LOCKUPRST		(1 << 5)
+#define RMU_RSTCAUSE_WDOGRST		(1 << 4)
+#define RMU_RSTCAUSE_EXTRST			(1 << 3)
+#define RMU_RSTCAUSE_BODREGRST		(1 << 2)
+#define RMU_RSTCAUSE_BODUNREGRST	(1 << 1)
+#define RMU_RSTCAUSE_PORST			(1 << 0)
+
+/* RMU_CMD */
+#define RMU_CMD_RCCLR	(1 << 0)
+
+/**@}*/

3rd/libopencm3/include/libopencm3/efm32/common/rtc_common.h

@@ -0,0 +1,73 @@
+/** @addtogroup rtc_defines
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/efm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/**@{*/
+
+#define RTC_CTRL		(RTC_BASE + 0x000)
+#define RTC_CNT			(RTC_BASE + 0x004)
+#define RTC_COMP0		(RTC_BASE + 0x008)
+#define RTC_COMP1		(RTC_BASE + 0x00C)
+#define RTC_IF			(RTC_BASE + 0x010)
+#define RTC_IFS			(RTC_BASE + 0x014)
+#define RTC_IFC			(RTC_BASE + 0x018)
+#define RTC_IEN			(RTC_BASE + 0x01C)
+#define RTC_FREEZE		(RTC_BASE + 0x020)
+#define RTC_SYNCBUSY	(RTC_BASE + 0x024)
+
+/* RTC_CTRL */
+#define RTC_CTRL_COMP0TOP		(1 << 2)
+#define RTC_CTRL_DEBUGRUN		(1 << 1)
+#define RTC_CTRL_EN				(1 << 0)
+
+/* RTC_IF */
+#define RTC_IF_COMP1			(1 << 2)
+#define RTC_IF_COMP0			(1 << 1)
+#define RTC_IF_OF				(1 << 0)
+
+/* RTC_IFS */
+#define RTC_IFS_COMP1			(1 << 2)
+#define RTC_IFS_COMP0			(1 << 1)
+#define RTC_IFS_OF				(1 << 0)
+
+/* RTC_IFC */
+#define RTC_IFC_COMP1			(1 << 2)
+#define RTC_IFC_COMP0			(1 << 1)
+#define RTC_IFC_OF				(1 << 0)
+
+/* RTC_IFE */
+#define RTC_IFE_COMP1			(1 << 2)
+#define RTC_IFE_COMP0			(1 << 1)
+#define RTC_IFE_OF				(1 << 0)
+
+/* RTC_FREEZE */
+#define RTC_FREEZE_REGFREEZE	(1 << 0)
+
+/* RTC_SYNCBUSY */
+#define RTC_SYNCBUSY_COMP1		(1 << 2)
+#define RTC_SYNCBUSY_COMP0		(1 << 1)
+#define RTC_SYNCBUSY_CTRL		(1 << 0)
+
+/**@}*/

3rd/libopencm3/include/libopencm3/efm32/common/timer_common.h

@@ -0,0 +1,612 @@
+/** @addtogroup timer_defines
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/efm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/**@{*/
+
+#define TIMER_CTRL(base)		MMIO32((base) + 0x000)
+#define TIMER_CMD(base)			MMIO32((base) + 0x004)
+#define TIMER_STATUS(base)		MMIO32((base) + 0x008)
+#define TIMER_IEN(base)			MMIO32((base) + 0x00C)
+#define TIMER_IF(base)			MMIO32((base) + 0x010)
+#define TIMER_IFS(base)			MMIO32((base) + 0x014)
+#define TIMER_IFC(base)			MMIO32((base) + 0x018)
+#define TIMER_TOP(base)			MMIO32((base) + 0x01C)
+#define TIMER_TOPB(base)		MMIO32((base) + 0x020)
+#define TIMER_CNT(base)			MMIO32((base) + 0x024)
+#define TIMER_ROUTE(base)		MMIO32((base) + 0x028)
+
+#define TIMER_CCx_CTRL(base, x)		MMIO32((base) + 0x030 + (0x10 * (x)))
+#define TIMER_CCx_CCV(base, x)		MMIO32((base) + 0x034 + (0x10 * (x)))
+#define TIMER_CCx_CCVP(base, x)		MMIO32((base) + 0x038 + (0x10 * (x)))
+#define TIMER_CCx_CCVB(base, x)		MMIO32((base) + 0x03C + (0x10 * (x)))
+
+#define TIMER_CC0_CTRL(base)		TIMER_CCx_CTRL(base, 0)
+#define TIMER_CC0_CCV(base)		TIMER_CCx_CCV(base, 0)
+#define TIMER_CC0_CCVP(base)		TIMER_CCx_CCVP(base, 0)
+#define TIMER_CC0_CCVB(base)		TIMER_CCx_CCVB(base, 0)
+
+#define TIMER_CC1_CTRL(base)		TIMER_CCx_CTRL(base, 1)
+#define TIMER_CC1_CCV(base)		TIMER_CCx_CCV(base, 1)
+#define TIMER_CC1_CCVP(base)		TIMER_CCx_CCVP(base, 1)
+#define TIMER_CC1_CCVB(base)		TIMER_CCx_CCVB(base, 1)
+
+#define TIMER_CC2_CTRL(base)		TIMER_CCx_CTRL(base, 2)
+#define TIMER_CC2_CCV(base)		TIMER_CCx_CCV(base, 2)
+#define TIMER_CC2_CCVP(base)		TIMER_CCx_CCVP(base, 2)
+#define TIMER_CC2_CCVB(base)		TIMER_CCx_CCVB(base, 2)
+
+#define TIMER_DTCTRL(base)		MMIO32((base) + 0x070)
+#define TIMER_DTTIME(base)		MMIO32((base) + 0x074)
+#define TIMER_DTFC(base)		MMIO32((base) + 0x078)
+#define TIMER_DTOGEN(base)		MMIO32((base) + 0x07C)
+#define TIMER_DTFAULT(base)		MMIO32((base) + 0x080)
+#define TIMER_DTFAULTC(base)		MMIO32((base) + 0x084)
+#define TIMER_DTLOCK(base)		MMIO32((base) + 0x088)
+
+/* TIMER_CTRL */
+#define TIMER_CTRL_RSSCOIST		(1 << 29)
+#define TIMER_CTRL_ATI			(1 << 28)
+
+#define TIMER_CTRL_PRESC_SHIFT		(24)
+#define TIMER_CTRL_PRESC_MASK		(0xF << TIMER_CTRL_PRESC_SHIFT)
+#define TIMER_CTRL_PRESC(v)			\
+	(((v) << TIMER_CTRL_PRESC_SHIFT) & TIMER_CTRL_PRESC_MASK)
+#define TIMER_CTRL_PRESC_DIV1		0
+#define TIMER_CTRL_PRESC_DIV2		1
+#define TIMER_CTRL_PRESC_DIV4		2
+#define TIMER_CTRL_PRESC_DIV8		3
+#define TIMER_CTRL_PRESC_DIV16		4
+#define TIMER_CTRL_PRESC_DIV32		5
+#define TIMER_CTRL_PRESC_DIV64		6
+#define TIMER_CTRL_PRESC_DIV128		7
+#define TIMER_CTRL_PRESC_DIV256		8
+#define TIMER_CTRL_PRESC_DIV512		9
+#define TIMER_CTRL_PRESC_DIV1024	10
+#define TIMER_CTRL_PRESC_NODIV		TIMER_CTRL_PRESC_DIV1
+
+#define TIMER_CTRL_CLKSEL_SHIFT		(16)
+#define TIMER_CTRL_CLKSEL_MASK		(0x3 << TIMER_CTRL_CLKSEL_SHIFT)
+#define TIMER_CTRL_CLKSEL(v)		\
+	(((v) << TIMER_CTRL_CLKSEL_SHIFT) & TIMER_CTRL_CLKSEL_MASK)
+#define TIMER_CTRL_CLKSEL_PRESCHFPERCLK	0
+#define TIMER_CTRL_CLKSEL_CC1		1
+#define TIMER_CTRL_CLKSEL_TIMEROUF	2
+
+#define TIMER_CTRL_X2CNT		(1 << 13)
+
+#define TIMER_CTRL_FALLA_SHIFT		(10)
+#define TIMER_CTRL_FALLA_MASK		(0x3 << TIMER_CTRL_FALLA_SHIFT)
+#define TIMER_CTRL_FALLA(v)		\
+	(((v) << TIMER_CTRL_FALLA_SHIFT) & TIMER_CTRL_FALLA_MASK)
+#define TIMER_CTRL_FALLA_NONE		0
+#define TIMER_CTRL_FALLA_START		1
+#define TIMER_CTRL_FALLA_STOP		2
+#define TIMER_CTRL_FALLA_RELOADSTART	3
+
+#define TIMER_CTRL_RISEA_SHIFT		(8)
+#define TIMER_CTRL_RISEA_MASK		(0x3 << TIMER_CTRL_RISEA_SHIFT)
+#define TIMER_CTRL_RISEA(v)		\
+	(((v) << TIMER_CTRL_RISEA_SHIFT) & TIMER_CTRL_RISEA_MASK)
+#define TIMER_CTRL_RISEA_NONE		0
+#define TIMER_CTRL_RISEA_START		1
+#define TIMER_CTRL_RISEA_STOP		2
+#define TIMER_CTRL_RISEA_RELOADSTART	3
+
+/* TIMER_CTRL_DMACLRACT bit is strangely documented.
+ * set this bit,
+ * in case you are doing one DMA transfer on every timer trigger event.
+ * if this bit is not set, strange behaviour is seen.
+*/
+
+#define TIMER_CTRL_DMACLRACT		(1 << 7)
+#define TIMER_CTRL_DEBUGRUN		(1 << 6)
+#define TIMER_CTRL_QDM			(1 << 5)
+#define TIMER_CTRL_OSMEN		(1 << 4)
+#define TIMER_CTRL_SYNC			(1 << 3)
+
+#define TIMER_CTRL_MODE_SHIFT		(0)
+#define TIMER_CTRL_MODE_MASK		(0x3 << TIMER_CTRL_MODE_SHIFT)
+#define TIMER_CTRL_MODE(v)		\
+	(((v) << TIMER_CTRL_MODE_SHIFT) & TIMER_CTRL_MODE_MASK)
+#define TIMER_CTRL_MODE_UP		0
+#define TIMER_CTRL_MODE_DOWN		1
+#define TIMER_CTRL_MODE_UPDOWN		2
+#define TIMER_CTRL_MODE_QDEC		3
+
+/* TIMER_CMD */
+#define TIMER_CMD_STOP			(1 << 1)
+#define TIMER_CMD_START			(1 << 0)
+
+/* TIMER_STATUS */
+#define TIMER_STATUS_CCPOLx(x)		(1 << ((x) + 24))
+#define TIMER_STATUS_CCPOL2		TIMER_STATUS_CCPOLx(2)
+#define TIMER_STATUS_CCPOL1		TIMER_STATUS_CCPOLx(1)
+#define TIMER_STATUS_CCPOL0		TIMER_STATUS_CCPOLx(0)
+
+#define TIMER_STATUS_ICVx(x)		(1 << ((x) + 16))
+#define TIMER_STATUS_ICV2		TIMER_STATUS_ICVx(2)
+#define TIMER_STATUS_ICV1		TIMER_STATUS_ICVx(1)
+#define TIMER_STATUS_ICV0		TIMER_STATUS_ICVx(0)
+
+#define TIMER_STATUS_CCVBVx(x)		(1 << ((x) + 8))
+#define TIMER_STATUS_CCVBV2		TIMER_STATUS_CCVBVx(2)
+#define TIMER_STATUS_CCVBV1		TIMER_STATUS_CCVBVx(1)
+#define TIMER_STATUS_CCVBV0		TIMER_STATUS_CCVBVx(0)
+
+#define TIMER_STATUS_TOPBV		(1 << 2)
+#define TIMER_STATUS_DIR		(1 << 1)
+#define TIMER_STATUS_RUNNING		(1 << 0)
+
+/* TIMER_IEN */
+#define TIMER_IEN_ICBOFx(x)		(1 << ((x) + 8))
+#define TIMER_IEN_ICBOF0		TIMER_IEN_ICBOFx(0)
+#define TIMER_IEN_ICBOF1		TIMER_IEN_ICBOFx(1)
+#define TIMER_IEN_ICBOF2		TIMER_IEN_ICBOFx(2)
+
+#define TIMER_IEN_CCx(x)		(1 << ((x) + 4))
+#define TIMER_IEN_CC0			TIMER_IEN_CCx(0)
+#define TIMER_IEN_CC1			TIMER_IEN_CCx(1)
+#define TIMER_IEN_CC2			TIMER_IEN_CCx(2)
+
+#define TIMER_IEN_UF			(1 << 1)
+#define TIMER_IEN_OF			(1 << 0)
+
+
+/* TIMER_IF */
+#define TIMER_IF_ICBOFx(x)		(1 << ((x) + 8))
+#define TIMER_IF_ICBOF0			TIMER_IF_ICBOFx(0)
+#define TIMER_IF_ICBOF1			TIMER_IF_ICBOFx(1)
+#define TIMER_IF_ICBOF2			TIMER_IF_ICBOFx(2)
+
+#define TIMER_IF_CCx(x)			(1 << ((x) + 4))
+#define TIMER_IF_CC0			TIMER_IF_CCx(0)
+#define TIMER_IF_CC1			TIMER_IF_CCx(1)
+#define TIMER_IF_CC2			TIMER_IF_CCx(2)
+
+#define TIMER_IF_UF			(1 << 1)
+#define TIMER_IF_OF			(1 << 0)
+
+/* TIMER_IFS */
+#define TIMER_IFS_ICBOFx(x)		(1 << ((x) + 8))
+#define TIMER_IFS_ICBOF0		TIMER_IFS_ICBOFx(0)
+#define TIMER_IFS_ICBOF1		TIMER_IFS_ICBOFx(1)
+#define TIMER_IFS_ICBOF2		TIMER_IFS_ICBOFx(2)
+
+#define TIMER_IFS_CCx(x)		(1 << ((x) + 4))
+#define TIMER_IFS_CC0			TIMER_IFS_CCx(0)
+#define TIMER_IFS_CC1			TIMER_IFS_CCx(1)
+#define TIMER_IFS_CC2			TIMER_IFS_CCx(2)
+
+#define TIMER_IFS_UF			(1 << 1)
+#define TIMER_IFS_OF			(1 << 0)
+
+
+/* TIMER_IFC */
+#define TIMER_IFC_ICBOFx(x)		(1 << ((x) + 8))
+#define TIMER_IFC_ICBOF0		TIMER_IFC_ICBOFx(0)
+#define TIMER_IFC_ICBOF1		TIMER_IFC_ICBOFx(1)
+#define TIMER_IFC_ICBOF2		TIMER_IFC_ICBOFx(2)
+
+#define TIMER_IFC_CCx(x)		(1 << ((x) + 4))
+#define TIMER_IFC_CC0			TIMER_IFC_CCx(0)
+#define TIMER_IFC_CC1			TIMER_IFC_CCx(1)
+#define TIMER_IFC_CC2			TIMER_IFC_CCx(2)
+
+#define TIMER_IFC_UF			(1 << 1)
+#define TIMER_IFC_OF			(1 << 0)
+
+/* TIMER_ROUTE */
+#define TIMER_ROUTE_LOCATION_SHIFT	(16)
+#define TIMER_ROUTE_LOCATION_MASK	(0x7 << TIMER_ROUTE_LOCATION_SHIFT)
+#define TIMER_ROUTE_LOCATION(v)		\
+	(((v) << TIMER_ROUTE_LOCATION_SHIFT) & TIMER_ROUTE_LOCATION_MASK)
+#define TIMER_ROUTE_LOCATION_LOCx(x)	TIMER_ROUTE_LOCATION(x)
+#define TIMER_ROUTE_LOCATION_LOC0	0
+#define TIMER_ROUTE_LOCATION_LOC1	1
+#define TIMER_ROUTE_LOCATION_LOC2	2
+#define TIMER_ROUTE_LOCATION_LOC3	3
+#define TIMER_ROUTE_LOCATION_LOC4	4
+#define TIMER_ROUTE_LOCATION_LOC5	5
+
+#define TIMER_ROUTE_CDTIxPEN(x)		(1 << (8 + (x)))
+#define TIMER_ROUTE_CDTI0PEN		TIMER_ROUTE_CDTIxPEN(0)
+#define TIMER_ROUTE_CDTI1PEN		TIMER_ROUTE_CDTIxPEN(1)
+#define TIMER_ROUTE_CDTI2PEN		TIMER_ROUTE_CDTIxPEN(2)
+
+#define TIMER_ROUTE_CCxPEN(x)		(1 << (0 + (x)))
+#define TIMER_ROUTE_CC0PEN		TIMER_ROUTE_CCxPEN(0)
+#define TIMER_ROUTE_CC1PEN		TIMER_ROUTE_CCxPEN(1)
+#define TIMER_ROUTE_CC2PEN		TIMER_ROUTE_CCxPEN(2)
+
+/* TIMER_CCx_CTRL */
+#define TIMER_CC_CTRL_ICEVCTRL_SHIFT	(26)
+#define TIMER_CC_CTRL_ICEVCTRL_MASK	(0x3 << TIMER_CC_CTRL_ICEVCTRL_SHIFT)
+#define TIMER_CC_CTRL_ICEVCTRL(v)	\
+	(((v) << TIMER_CC_CTRL_ICEVCTRL_SHIFT) & TIMER_CC_CTRL_ICEVCTRL_MASK)
+#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE	0
+#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE	1
+#define TIMER_CC_CTRL_ICEVCTRL_RISING		2
+#define TIMER_CC_CTRL_ICEVCTRL_FALLING		3
+
+#define TIMER_CC_CTRL_ICEVCTRL_EVERY_EDGE	\
+	TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE
+#define TIMER_CC_CTRL_ICEVCTRL_EVERY_SECOND_EDGE	\
+	TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE
+
+#define TIMER_CC_CTRL_ICEDGE_SHIFT	(24)
+#define TIMER_CC_CTRL_ICEDGE_MASK	(0x3 << TIMER_CC_CTRL_ICEDGE_SHIFT)
+#define TIMER_CC_CTRL_ICEDGE(v)		\
+	(((v) << TIMER_CC_CTRL_ICEDGE_SHIFT) & TIMER_CC_CTRL_ICEDGE_MASK)
+#define TIMER_CC_CTRL_ICEDGE_RISING	0
+#define TIMER_CC_CTRL_ICEDGE_FALLING	1
+#define TIMER_CC_CTRL_ICEDGE_BOTH	2
+#define TIMER_CC_CTRL_ICEDGE_NONE	3
+
+#define TIMER_CC_CTRL_FILT		(1 << 21)
+#define TIMER_CC_CTRL_INSEL		(1 << 21)
+
+
+#define TIMER_CC_CTRL_PRSSEL_SHIFT	(16)
+#define TIMER_CC_CTRL_PRSSEL_MASK	(0xF << TIMER_CC_CTRL_PRSSEL_SHIFT)
+#define TIMER_CC_CTRL_PRSSEL(v)		\
+	(((v) << TIMER_CC_CTRL_PRSSEL_SHIFT) & TIMER_CC_CTRL_PRSSEL_MASK)
+#define TIMER_CC_CTRL_PRSSEL_PRSCHx(x)	TIMER_CC_CTRL_PRSSEL(x)
+#define TIMER_CC_CTRL_PRSSEL_PRSCH0	0
+#define TIMER_CC_CTRL_PRSSEL_PRSCH1	1
+#define TIMER_CC_CTRL_PRSSEL_PRSCH2	2
+#define TIMER_CC_CTRL_PRSSEL_PRSCH3	3
+#define TIMER_CC_CTRL_PRSSEL_PRSCH4	4
+#define TIMER_CC_CTRL_PRSSEL_PRSCH5	5
+#define TIMER_CC_CTRL_PRSSEL_PRSCH6	6
+#define TIMER_CC_CTRL_PRSSEL_PRSCH7	7
+#define TIMER_CC_CTRL_PRSSEL_PRSCH8	8
+#define TIMER_CC_CTRL_PRSSEL_PRSCH9	9
+#define TIMER_CC_CTRL_PRSSEL_PRSCH10	10
+#define TIMER_CC_CTRL_PRSSEL_PRSCH11	11
+
+#define TIMER_CC_CTRL_CUFOA_SHIFT	(12)
+#define TIMER_CC_CTRL_CUFOA_MASK	(0x3 << TIMER_CC_CTRL_CUFOA_SHIFT)
+#define TIMER_CC_CTRL_CUFOA(v)		\
+	(((v) << TIMER_CC_CTRL_CUFOA_SHIFT) & TIMER_CC_CTRL_CUFOA_MASK)
+#define TIMER_CC_CTRL_CUFOA_NONE	0
+#define TIMER_CC_CTRL_CUFOA_TOGGLE	1
+#define TIMER_CC_CTRL_CUFOA_CLEAR	2
+#define TIMER_CC_CTRL_CUFOA_SET		3
+
+#define TIMER_CC_CTRL_COFOA_SHIFT	(10)
+#define TIMER_CC_CTRL_COFOA_MASK	(0x3 << TIMER_CC_CTRL_COFOA_SHIFT)
+#define TIMER_CC_CTRL_COFOA(v)		\
+	(((v) << TIMER_CC_CTRL_COFOA_SHIFT) & TIMER_CC_CTRL_COFOA_MASK)
+#define TIMER_CC_CTRL_COFOA_NONE	0
+#define TIMER_CC_CTRL_COFOA_TOGGLE	1
+#define TIMER_CC_CTRL_COFOA_CLEAR	2
+#define TIMER_CC_CTRL_COFOA_SET		3
+
+#define TIMER_CC_CTRL_CMOA_SHIFT	(8)
+#define TIMER_CC_CTRL_CMOA_MASK		(0x3 << TIMER_CC_CTRL_CMOA_SHIFT)
+#define TIMER_CC_CTRL_CMOA(v)		\
+	(((v) << TIMER_CC_CTRL_CMOA_SHIFT) & TIMER_CC_CTRL_CMOA_MASK)
+#define TIMER_CC_CTRL_CMOA_NONE		0
+#define TIMER_CC_CTRL_CMOA_TOGGLE	1
+#define TIMER_CC_CTRL_CMOA_CLEAR	2
+#define TIMER_CC_CTRL_CMOA_SET		3
+
+#define TIMER_CC_CTRL_COIST		(1 << 4)
+#define TIMER_CC_CTRL_OUTINV		(1 << 2)
+
+#define TIMER_CC_CTRL_MODE_SHIFT	(0)
+#define TIMER_CC_CTRL_MODE_MASK		(0x3 << TIMER_CC_CTRL_MODE_SHIFT)
+#define TIMER_CC_CTRL_MODE(v)		\
+	(((v) << TIMER_CC_CTRL_MODE_SHIFT) & TIMER_CC_CTRL_MODE_MASK)
+#define TIMER_CC_CTRL_MODE_OFF		0
+#define TIMER_CC_CTRL_MODE_INPUTCAPTURE		1
+#define TIMER_CC_CTRL_MODE_OUTPUTCOMPARE	2
+#define TIMER_CC_CTRL_MODE_PWM		3
+
+#define TIMER_CC_CTRL_MODE_INPUT_CAPTURE	\
+	TIMER_CC_CTRL_MODE_INPUTCAPTURE
+#define TIMER_CC_CTRL_MODE_OUTPUT_CAPTURE	\
+	TIMER_CC_CTRL_MODE_OUTPUTCAPTURE
+
+/* TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSEN		(1 << 24)
+
+#define TIMER_DTCTRL_DTPRSSEL_SHIFT	(4)
+#define TIMER_DTCTRL_DTPRSSEL_MASK	(0xF << TIMER_DTCTRL_DTPRSSEL_SHIFT)
+#define TIMER_DTCTRL_DTPRSSEL(v)	\
+	(((v) << TIMER_DTCTRL_DTPRSSEL_SHIFT) & TIMER_DTCTRL_DTPRSSEL_MASK)
+#define TIMER_DTCTRL_DTPRSSEL_PRSCHx(x)	TIMER_DTCTRL_DTPRSSEL(x)
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH0	0
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH1	1
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH2	2
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH3	3
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH4	4
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH5	5
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH6	6
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH7	7
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH8	8
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH9	9
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH10	10
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH11	11
+
+#define TIMER_DTCTRL_DTCINV		(1 << 3)
+#define TIMER_DTCTRL_DTIPOL		(1 << 2)
+#define TIMER_DTCTRL_DTDAS		(1 << 1)
+#define TIMER_DTCTRL_DTEN		(1 << 0)
+
+/* TIMER_DTTIME */
+#define TIMER_DTTIME_DTFALLT_SHIFT	(16)
+#define TIMER_DTTIME_DTFALLT_MASK	(0x3F << TIMER_DTTIME_DTFALLT_SHIFT)
+#define TIMER_DTTIME_DTFALLT(v)		\
+	(((v) << TIMER_DTTIME_DTFALLT_SHIFT) & TIMER_DTTIME_DTFALLT_MASK)
+
+#define TIMER_DTTIME_DTRISET_SHIFT	(8)
+#define TIMER_DTTIME_DTRISET_MASK	(0x3F << TIMER_DTTIME_DTRISET_SHIFT)
+#define TIMER_DTTIME_DTRISET(v)		\
+	(((v) << TIMER_DTTIME_DTRISET_SHIFT) & TIMER_DTTIME_DTRISET_MASK)
+
+
+#define TIMER_DTTIME_DTPRESC_SHIFT	(0)
+#define TIMER_DTTIME_DTPRESC_MASK	(0xF << TIMER_DTTIME_DTPRESC_SHIFT)
+#define TIMER_DTTIME_DTPRESC(v)		\
+	(((v) << TIMER_DTTIME_DTPRESC_SHIFT) & TIMER_DTTIME_DTPRESC_MASK)
+#define TIMER_DTTIME_DTPRESC_DIV1	0
+#define TIMER_DTTIME_DTPRESC_DIV2	1
+#define TIMER_DTTIME_DTPRESC_DIV4	2
+#define TIMER_DTTIME_DTPRESC_DIV8	3
+#define TIMER_DTTIME_DTPRESC_DIV16	4
+#define TIMER_DTTIME_DTPRESC_DIV32	5
+#define TIMER_DTTIME_DTPRESC_DIV64	6
+#define TIMER_DTTIME_DTPRESC_DIV128	7
+#define TIMER_DTTIME_DTPRESC_DIV256	8
+#define TIMER_DTTIME_DTPRESC_DIV512	8
+#define TIMER_DTTIME_DTPRESC_DIV1024	10
+#define TIMER_DTTIME_DTPRESC_NODIV	TIMER_DTTIME_DTPRESC_DIV1
+
+/* TIMER_DTFC */
+#define TIMER_DTFC_DTLOCKUPFEN		(1 << 27)
+#define TIMER_DTFC_DTDBGFEN		(1 << 26)
+#define TIMER_DTFC_DTPRS1FEN		(1 << 25)
+#define TIMER_DTFC_DTPRS0FEN		(1 << 24)
+
+#define TIMER_DTFC_DTFA_SHIFT		(16)
+#define TIMER_DTFC_DTFA_MASK		(0x3 << TIMER_DTFC_DTFA_SHIFT)
+#define TIMER_DTFC_DTFA(v)		\
+	(((v) << TIMER_DTFC_DTFA_SHIFT) & TIMER_DTFC_DTFA_MASK)
+#define TIMER_DTFC_DTFA_NONE		0
+#define TIMER_DTFC_DTFA_INACTIVE	1
+#define TIMER_DTFC_DTFA_CLEAR		2
+#define TIMER_DTFC_DTFA_TRISTATE	3
+
+#define TIMER_DTFC_DTPRS1FSEL_SHIFT	(8)
+#define TIMER_DTFC_DTPRS1FSEL_MASK	(0x3 << TIMER_DTFC_DTPRS1FSEL_SHIFT)
+#define TIMER_DTFC_DTPRS1FSEL(v)	\
+	(((v) << TIMER_DTFC_DTPRS1FSEL_SHIFT) & TIMER_DTFC_DTPRS1FSEL_MASK)
+#define TIMER_DTFC_DTPRS1FSEL_PRSCHx(x)	TIMER_DTFC_DTPRS1FSEL(x)
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH0	0
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH1	1
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH2	2
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH3	3
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH4	4
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH5	5
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH6	6
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH7	7
+
+#define TIMER_DTFC_DTPRS0FSEL_SHIFT	(8)
+#define TIMER_DTFC_DTPRS0FSEL_MASK	(0x3 << TIMER_DTFC_DTPRS0FSEL_SHIFT)
+#define TIMER_DTFC_DTPRS0FSEL(v)	\
+	(((v) << TIMER_DTFC_DTPRS0FSEL_SHIFT) & TIMER_DTFC_DTPRS0FSEL_MASK)
+#define TIMER_DTFC_DTPRS0FSEL_PRSCHx(x)	TIMER_DTFC_DTPRS0FSEL(x)
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH0	0
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH1	1
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH2	2
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH3	3
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH4	4
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH5	5
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH6	6
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH7	7
+
+/* TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCDTI2EN	(1 << 5)
+#define TIMER_DTOGEN_DTOGCDTI1EN	(1 << 4)
+#define TIMER_DTOGEN_DTOGCDTI0EN	(1 << 3)
+#define TIMER_DTOGEN_DTOGCC2EN		(1 << 2)
+#define TIMER_DTOGEN_DTOGCC1EN		(1 << 1)
+#define TIMER_DTOGEN_DTOGCC0EN		(1 << 0)
+
+/* TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTLOCKUPF		(1 << 3)
+#define TIMER_DTFAULT_DTDBGF		(1 << 2)
+#define TIMER_DTFAULT_DTPRS1F		(1 << 1)
+#define TIMER_DTFAULT_DTPRS0F		(1 << 0)
+
+/* TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_TLOCKUPFC	(1 << 3)
+#define TIMER_DTFAULTC_DTDBGFC		(1 << 2)
+#define TIMER_DTFAULTC_DTPRS1FC		(1 << 1)
+#define TIMER_DTFAULTC_DTPRS0FC		(1 << 0)
+
+/* TIMER_DTLOCK */
+#define TIMER_DTLOCK_LOCKKEY_SHIFT	(0)
+#define TIMER_DTLOCK_LOCKKEY_MASK	(0xFFFF << TIMER_DTLOCK_LOCKKEY_SHIFT)
+#define TIMER_DTLOCK_LOCKKEY_UNLOCKED	(0x0000 << TIMER_DTLOCK_LOCKKEY_SHIFT)
+#define TIMER_DTLOCK_LOCKKEY_LOCKED	(0x0001 << TIMER_DTLOCK_LOCKKEY_SHIFT)
+#define TIMER_DTLOCK_LOCKKEY_LOCK	(0x0000 << TIMER_DTLOCK_LOCKKEY_SHIFT)
+#define TIMER_DTLOCK_LOCKKEY_UNLOCK	(0xCE80 << TIMER_DTLOCK_LOCKKEY_SHIFT)
+
+/* TIMER0 */
+#define TIMER0				TIMER0_BASE
+#define TIMER0_CTRL			TIMER_CTRL(TIMER0)
+#define TIMER0_CMD			TIMER_CMD(TIMER0)
+#define TIMER0_STATUS			TIMER_STATUS(TIMER0)
+#define TIMER0_IEN			TIMER_IEN(TIMER0)
+#define TIMER0_IF			TIMER_IF(TIMER0)
+#define TIMER0_IFS			TIMER_IFS(TIMER0)
+#define TIMER0_IFC			TIMER_IFC(TIMER0)
+#define TIMER0_TOP			TIMER_TOP(TIMER0)
+#define TIMER0_TOPB			TIMER_TOPB(TIMER0)
+#define TIMER0_CNT			TIMER_CNT(TIMER0)
+#define TIMER0_ROUTE			TIMER_ROUTE(TIMER0)
+
+#define TIMER0_CC0_CTRL			TIMER_CC0_CTRL(TIMER0)
+#define TIMER0_CC0_CCV			TIMER_CC0_CCV(TIMER0)
+#define TIMER0_CC0_CCVP			TIMER_CC0_CCVP(TIMER0)
+#define TIMER0_CC0_CCVB			TIMER_CC0_CCVB(TIMER0)
+
+#define TIMER0_CC1_CTRL			TIMER_CC1_CTRL(TIMER0)
+#define TIMER0_CC1_CCV			TIMER_CC1_CCV(TIMER0)
+#define TIMER0_CC1_CCVP			TIMER_CC1_CCVP(TIMER0)
+#define TIMER0_CC1_CCVB			TIMER_CC1_CCVB(TIMER0)
+
+#define TIMER0_CC2_CTRL			TIMER_CC2_CTRL(TIMER0)
+#define TIMER0_CC2_CCV			TIMER_CC2_CCV(TIMER0)
+#define TIMER0_CC2_CCVP			TIMER_CC2_CCVP(TIMER0)
+#define TIMER0_CC2_CCVB			TIMER_CC2_CCVB(TIMER0)
+
+#define TIMER0_DTCTRL			TIMER_DTCTRL(TIMER0)
+#define TIMER0_DTTIME			TIMER_DTTIME(TIMER0)
+#define TIMER0_DTFC			TIMER_DTFC(TIMER0)
+#define TIMER0_DTOGEN			TIMER_DTOGEN(TIMER0)
+#define TIMER0_DTFAULT			TIMER_DTFAULT(TIMER0)
+#define TIMER0_DTFAULTC			TIMER_DTFAULTC(TIMER0)
+#define TIMER0_DTLOCK			TIMER_DTLOCK(TIMER0)
+
+/* TIMER1 */
+#define TIMER1				TIMER1_BASE
+#define TIMER1_CTRL			TIMER_CTRL(TIMER1)
+#define TIMER1_CMD			TIMER_CMD(TIMER1)
+#define TIMER1_STATUS			TIMER_STATUS(TIMER1)
+#define TIMER1_IEN			TIMER_IEN(TIMER1)
+#define TIMER1_IF			TIMER_IF(TIMER1)
+#define TIMER1_IFS			TIMER_IFS(TIMER1)
+#define TIMER1_IFC			TIMER_IFC(TIMER1)
+#define TIMER1_TOP			TIMER_TOP(TIMER1)
+#define TIMER1_TOPB			TIMER_TOPB(TIMER1)
+#define TIMER1_CNT			TIMER_CNT(TIMER1)
+#define TIMER1_ROUTE			TIMER_ROUTE(TIMER1)
+
+#define TIMER1_CC0_CTRL			TIMER_CC0_CTRL(TIMER1)
+#define TIMER1_CC0_CCV			TIMER_CC0_CCV(TIMER1)
+#define TIMER1_CC0_CCVP			TIMER_CC0_CCVP(TIMER1)
+#define TIMER1_CC0_CCVB			TIMER_CC0_CCVB(TIMER1)
+
+#define TIMER1_CC1_CTRL			TIMER_CC1_CTRL(TIMER1)
+#define TIMER1_CC1_CCV			TIMER_CC1_CCV(TIMER1)
+#define TIMER1_CC1_CCVP			TIMER_CC1_CCVP(TIMER1)
+#define TIMER1_CC1_CCVB			TIMER_CC1_CCVB(TIMER1)
+
+#define TIMER1_CC2_CTRL			TIMER_CC2_CTRL(TIMER1)
+#define TIMER1_CC2_CCV			TIMER_CC2_CCV(TIMER1)
+#define TIMER1_CC2_CCVP			TIMER_CC2_CCVP(TIMER1)
+#define TIMER1_CC2_CCVB			TIMER_CC2_CCVB(TIMER1)
+
+/* TIMER2 */
+#define TIMER2				TIMER2_BASE
+#define TIMER2_CTRL			TIMER_CTRL(TIMER2)
+#define TIMER2_CMD			TIMER_CMD(TIMER2)
+#define TIMER2_STATUS			TIMER_STATUS(TIMER2)
+#define TIMER2_IEN			TIMER_IEN(TIMER2)
+#define TIMER2_IF			TIMER_IF(TIMER2)
+#define TIMER2_IFS			TIMER_IFS(TIMER2)
+#define TIMER2_IFC			TIMER_IFC(TIMER2)
+#define TIMER2_TOP			TIMER_TOP(TIMER2)
+#define TIMER2_TOPB			TIMER_TOPB(TIMER2)
+#define TIMER2_CNT			TIMER_CNT(TIMER2)
+#define TIMER2_ROUTE			TIMER_ROUTE(TIMER2)
+
+#define TIMER2_CC0_CTRL			TIMER_CC0_CTRL(TIMER2)
+#define TIMER2_CC0_CCV			TIMER_CC0_CCV(TIMER2)
+#define TIMER2_CC0_CCVP			TIMER_CC0_CCVP(TIMER2)
+#define TIMER2_CC0_CCVB			TIMER_CC0_CCVB(TIMER2)
+
+#define TIMER2_CC1_CTRL			TIMER_CC1_CTRL(TIMER2)
+#define TIMER2_CC1_CCV			TIMER_CC1_CCV(TIMER2)
+#define TIMER2_CC1_CCVP			TIMER_CC1_CCVP(TIMER2)
+#define TIMER2_CC1_CCVB			TIMER_CC1_CCVB(TIMER2)
+
+#define TIMER2_CC2_CTRL			TIMER_CC2_CTRL(TIMER2)
+#define TIMER2_CC2_CCV			TIMER_CC2_CCV(TIMER2)
+#define TIMER2_CC2_CCVP			TIMER_CC2_CCVP(TIMER2)
+#define TIMER2_CC2_CCVB			TIMER_CC2_CCVB(TIMER2)
+
+/* TIMER3 */
+#define TIMER3				TIMER3_BASE
+#define TIMER3_CTRL			TIMER_CTRL(TIMER3)
+#define TIMER3_CMD			TIMER_CMD(TIMER3)
+#define TIMER3_STATUS			TIMER_STATUS(TIMER3)
+#define TIMER3_IEN			TIMER_IEN(TIMER3)
+#define TIMER3_IF			TIMER_IF(TIMER3)
+#define TIMER3_IFS			TIMER_IFS(TIMER3)
+#define TIMER3_IFC			TIMER_IFC(TIMER3)
+#define TIMER3_TOP			TIMER_TOP(TIMER3)
+#define TIMER3_TOPB			TIMER_TOPB(TIMER3)
+#define TIMER3_CNT			TIMER_CNT(TIMER3)
+#define TIMER3_ROUTE			TIMER_ROUTE(TIMER3)
+
+#define TIMER3_CC0_CTRL			TIMER_CC0_CTRL(TIMER3)
+#define TIMER3_CC0_CCV			TIMER_CC0_CCV(TIMER3)
+#define TIMER3_CC0_CCVP			TIMER_CC0_CCVP(TIMER3)
+#define TIMER3_CC0_CCVB			TIMER_CC0_CCVB(TIMER3)
+
+#define TIMER3_CC1_CTRL			TIMER_CC1_CTRL(TIMER3)
+#define TIMER3_CC1_CCV			TIMER_CC1_CCV(TIMER3)
+#define TIMER3_CC1_CCVP			TIMER_CC1_CCVP(TIMER3)
+#define TIMER3_CC1_CCVB			TIMER_CC1_CCVB(TIMER3)
+
+#define TIMER3_CC2_CTRL			TIMER_CC2_CTRL(TIMER3)
+#define TIMER3_CC2_CCV			TIMER_CC2_CCV(TIMER3)
+#define TIMER3_CC2_CCVP			TIMER_CC2_CCVP(TIMER3)
+#define TIMER3_CC2_CCVB			TIMER_CC2_CCVB(TIMER3)
+
+/** @defgroup timer_ch Timer Channel Number
+@ingroup timer_defines
+
+@{*/
+enum tim_ch {
+	TIM_CH0 = 0,
+	TIM_CH1,
+	TIM_CH2
+};
+/**@}*/
+
+BEGIN_DECLS
+
+void timer_start(uint32_t timer);
+void timer_stop(uint32_t timer);
+
+void timer_set_clock_prescaler(uint32_t timer, uint32_t prescaler);
+
+void timer_set_top(uint32_t timer, uint32_t top);
+
+/* TODO: interrupt {enable, disable, read-flags} */
+
+/* TODO: for channel (output value, input value)
+ *  enable channel
+ * set location, set output mode */
+
+END_DECLS
+
+/**@}*/

3rd/libopencm3/include/libopencm3/efm32/common/uart_common.h

@@ -0,0 +1,104 @@
+/** @addtogroup uart_defines
+ *
+ * @brief UART registers are mostly equivalent to USART registers.
+ *
+ * USART and UART registers are equivalent except [in UART registers]:
+ *
+ *  * USART_CTRL: SYNC, CSMA, SMSDELAY, SSSEARLY, CSINV, CPOL and CPHA
+ *	(Synchronous operation not available)
+ *  * USART_STATUS: MASTEREN (Synchronous operation not available)
+ *  * USART_CTRL: MSBF (transmission LSB first only)
+ *  * USART_CTRL: AUTOCS (chip-select not available)
+ *  * USART_CTRL: SCMODE (SmartCard mode not available)
+ *  * USART_FRAME: DATABITS (limited framesize. 8-9 databits only)
+ *  * USART_IRCTRL: IREN (IrDA not available)
+ *   (except DATABITS, all the above are 0)
+ *
+ * full text: (p495, "d0183_Rev1.10" EFM32LG-RM)
+ *  - "18.3 Functional Description",
+ *  - "18.4 Register Description"
+ *  - "18.5 Register Map"
+ *
+ * use USART macro's to manipulate UART registers.
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/efm32/memorymap.h>
+#include <libopencm3/efm32/usart.h>
+
+/**@{*/
+
+/* UART0 */
+#define UART0				UART0_BASE
+#define UART0_CTRL			USART_CTRL(UART0)
+#define UART0_FRAME			USART_FRAME(UART0)
+#define UART0_TRIGCTRL		USART_TRIGCTRL(UART0)
+#define UART0_CMD			USART_CMD(UART0)
+#define UART0_STATUS		USART_STATUS(UART0)
+#define UART0_CLKDIV		USART_CLKDIV(UART0)
+#define UART0_RXDATAX		USART_RXDATAX(UART0)
+#define UART0_RXDATA		USART_RXDATA(UART0)
+#define UART0_RXDOUBLEX		USART_RXDOUBLEX(UART0)
+#define UART0_RXDOUBLE		USART_RXDOUBLE(UART0)
+#define UART0_RXDATAXP		USART_RXDATAXP(UART0)
+#define UART0_RXDOUBLEXP	USART_RXDOUBLEXP(UART0)
+#define UART0_TXDATAX		USART_TXDATAX(UART0)
+#define UART0_TXDATA		USART_TXDATA(UART0)
+#define UART0_TXDOUBLEX		USART_TXDOUBLEX(UART0)
+#define UART0_TXDOUBLE		USART_TXDOUBLE(UART0)
+#define UART0_IF			USART_IF(UART0)
+#define UART0_IFS			USART_IFS(UART0)
+#define UART0_IFC			USART_IFC(UART0)
+#define UART0_IEN			USART_IEN(UART0)
+#define UART0_IRCTRL		USART_IRCTRL(UART0)
+#define UART0_ROUTE			USART_ROUTE(UART0)
+#define UART0_INPUT			USART_INPUT(UART0)
+#define UART0_I2SCTRL		USART_I2SCTRL(UART0)
+
+/* UART1 */
+#define UART1				UART1_BASE
+#define UART1_CTRL			USART_CTRL(UART1)
+#define UART1_FRAME			USART_FRAME(UART1)
+#define UART1_TRIGCTRL		USART_TRIGCTRL(UART1)
+#define UART1_CMD			USART_CMD(UART1)
+#define UART1_STATUS		USART_STATUS(UART1)
+#define UART1_CLKDIV		USART_CLKDIV(UART1)
+#define UART1_RXDATAX		USART_RXDATAX(UART1)
+#define UART1_RXDATA		USART_RXDATA(UART1)
+#define UART1_RXDOUBLEX		USART_RXDOUBLEX(UART1)
+#define UART1_RXDOUBLE		USART_RXDOUBLE(UART1)
+#define UART1_RXDATAXP		USART_RXDATAXP(UART1)
+#define UART1_RXDOUBLEXP	USART_RXDOUBLEXP(UART1)
+#define UART1_TXDATAX		USART_TXDATAX(UART1)
+#define UART1_TXDATA		USART_TXDATA(UART1)
+#define UART1_TXDOUBLEX		USART_TXDOUBLEX(UART1)
+#define UART1_TXDOUBLE		USART_TXDOUBLE(UART1)
+#define UART1_IF			USART_IF(UART1)
+#define UART1_IFS			USART_IFS(UART1)
+#define UART1_IFC			USART_IFC(UART1)
+#define UART1_IEN			USART_IEN(UART1)
+#define UART1_IRCTRL		USART_IRCTRL(UART1)
+#define UART1_ROUTE			USART_ROUTE(UART1)
+#define UART1_INPUT			USART_INPUT(UART1)
+#define UART1_I2SCTRL		USART_I2SCTRL(UART1)
+
+/**@}*/

3rd/libopencm3/include/libopencm3/efm32/common/usart_common.h

@@ -0,0 +1,514 @@
+/** @addtogroup usart_defines
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/efm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/**@{*/
+
+#define USART_CTRL(base)		MMIO32((base) + 0x000)
+#define USART_FRAME(base)		MMIO32((base) + 0x004)
+#define USART_TRIGCTRL(base)		MMIO32((base) + 0x008)
+#define USART_CMD(base)			MMIO32((base) + 0x00C)
+#define USART_STATUS(base)		MMIO32((base) + 0x010)
+#define USART_CLKDIV(base)		MMIO32((base) + 0x014)
+#define USART_RXDATAX(base)		MMIO32((base) + 0x018)
+#define USART_RXDATA(base)		MMIO32((base) + 0x01C)
+#define USART_RXDOUBLEX(base)		MMIO32((base) + 0x020)
+#define USART_RXDOUBLE(base)		MMIO32((base) + 0x024)
+#define USART_RXDATAXP(base)		MMIO32((base) + 0x028)
+#define USART_RXDOUBLEXP(base)		MMIO32((base) + 0x02C)
+#define USART_TXDATAX(base)		MMIO32((base) + 0x030)
+#define USART_TXDATA(base)		MMIO32((base) + 0x034)
+#define USART_TXDOUBLEX(base)		MMIO32((base) + 0x038)
+#define USART_TXDOUBLE(base)		MMIO32((base) + 0x03C)
+#define USART_IF(base)			MMIO32((base) + 0x040)
+#define USART_IFS(base)			MMIO32((base) + 0x044)
+#define USART_IFC(base)			MMIO32((base) + 0x048)
+#define USART_IEN(base)			MMIO32((base) + 0x04C)
+#define USART_IRCTRL(base)		MMIO32((base) + 0x050)
+#define USART_ROUTE(base)		MMIO32((base) + 0x054)
+#define USART_INPUT(base)		MMIO32((base) + 0x058)
+#define USART_I2SCTRL(base)		MMIO32((base) + 0x05C)
+
+/* USART_CTRL */
+#define USART_CTRL_SMSDELAY		(1 << 31)
+#define USART_CTRL_MVDIS		(1 << 30)
+#define USART_CTRL_AUTOTX		(1 << 29)
+#define USART_CTRL_BYTESWAP		(1 << 28)
+
+#define USART_CTRL_TXDELAY_SHIFT	(26)
+#define USART_CTRL_TXDELAY_MASK		(0x3 << USART_CTRL_TXDELAY_SHIFT)
+#define USART_CTRL_TXDELAY(v)		\
+	(((v)  << USART_CTRL_TXDELAY_SHIFT) & USART_CTRL_TXDELAY_MASK)
+#define USART_CTRL_TXDELAY_NONE		0
+#define USART_CTRL_TXDELAY_SINGLE	1
+#define USART_CTRL_TXDELAY_DOUBLE	2
+#define USART_CTRL_TXDELAY_TRIPLE	3
+
+#define USART_CTRL_SSSEARLY		(1 << 25)
+#define USART_CTRL_ERRSTX		(1 << 24)
+#define USART_CTRL_ERRSRX		(1 << 23)
+#define USART_CTRL_ERRSDMA		(1 << 22)
+#define USART_CTRL_BIT8DV		(1 << 21)
+#define USART_CTRL_SKIPPERRF		(1 << 20)
+#define USART_CTRL_SCRETRANS		(1 << 19)
+#define USART_CTRL_SCMODE		(1 << 18)
+#define USART_CTRL_AUTOTRI		(1 << 17)
+#define USART_CTRL_AUTOCS		(1 << 16)
+#define USART_CTRL_CSINV		(1 << 15)
+#define USART_CTRL_TXINV		(1 << 14)
+#define USART_CTRL_RXINV		(1 << 13)
+#define USART_CTRL_TXBIL		(1 << 12)
+#define USART_CTRL_CSMA			(1 << 11)
+#define USART_CTRL_MSBF			(1 << 10)
+#define USART_CTRL_CLKPHA		(1 << 9)
+#define USART_CTRL_CLKPOL		(1 << 8)
+
+#define USART_CTRL_OVS_SHIFT		(5)
+#define USART_CTRL_OVS_MASK		(0x3 << USART_CTRL_OVS_SHIFT)
+#define USART_CTRL_OVS(v)		\
+	(((v)  << USART_CTRL_OVS_SHIFT) & USART_CTRL_OVS_MASK)
+#define USART_CTRL_OVS_X16		0
+#define USART_CTRL_OVS_X8		1
+#define USART_CTRL_OVS_X6		2
+#define USART_CTRL_OVS_X4		3
+
+#define USART_CTRL_MPAB			(1 << 4)
+#define USART_CTRL_MPM			(1 << 3)
+#define USART_CTRL_CCEN			(1 << 2)
+#define USART_CTRL_LOOPBK		(1 << 1)
+#define USART_CTRL_SYNC			(1 << 0)
+
+/* USART_FRAME */
+
+#define USART_FRAME_STOPBITS_SHIFT	(12)
+#define USART_FRAME_STOPBITS_MASK	(0x3 << USART_FRAME_STOPBITS_SHIFT)
+#define USART_FRAME_STOPBITS(v)		\
+	(((v)  << USART_FRAME_STOPBITS_SHIFT) & USART_FRAME_STOPBITS_MASK)
+#define USART_FRAME_STOPBITS_HALF	0
+#define USART_FRAME_STOPBITS_ONE	1
+#define USART_FRAME_STOPBITS_ONEANDAHALF	2
+#define USART_FRAME_STOPBITS_ONE_AND_A_HALF	\
+	USART_FRAME_STOPBITS_ONEANDAHALF
+#define USART_FRAME_STOPBITS_TWO	3
+
+#define USART_FRAME_PARITY_SHIFT	(8)
+#define USART_FRAME_PARITY_MASK		(0x3 << USART_FRAME_PARITY_SHIFT)
+#define USART_FRAME_PARITY(v)		\
+	(((v)  << USART_FRAME_PARITY_SHIFT) & USART_FRAME_PARITY_MASK)
+#define USART_FRAME_PARITY_NONE		0
+#define USART_FRAME_PARITY_EVEN		2
+#define USART_FRAME_PARITY_ODD		3
+
+#define USART_FRAME_DATABITS_SHIFT	(0)
+#define USART_FRAME_DATABITS_MASK	(0xF << USART_FRAME_DATABITS_SHIFT)
+#define USART_FRAME_DATABITS(v)		\
+	(((v)  << USART_FRAME_DATABITS_SHIFT) & USART_FRAME_DATABITS_MASK)
+#define USART_FRAME_DATABITS_FOUR	1
+#define USART_FRAME_DATABITS_FIVE	2
+#define USART_FRAME_DATABITS_SIX	3
+#define USART_FRAME_DATABITS_SEVEN	4
+#define USART_FRAME_DATABITS_EIGHT	5
+#define USART_FRAME_DATABITS_NINE	6
+#define USART_FRAME_DATABITS_TEN	7
+#define USART_FRAME_DATABITS_ELEVEN	8
+#define USART_FRAME_DATABITS_TWELVE	9
+#define USART_FRAME_DATABITS_THIRTEEN	10
+#define USART_FRAME_DATABITS_FOURTEEN	11
+#define USART_FRAME_DATABITS_FIFTEEN	12
+#define USART_FRAME_DATABITS_SIXTEEN	13
+
+/* USART_TRIGCTRL */
+#define USART_TRIGCTRL_AUTOTXTEN	(1 << 6)
+#define USART_TRIGCTRL_TXTEN		(1 << 5)
+#define USART_TRIGCTRL_RXTEN		(1 << 4)
+
+#define USART_TRIGCTRL_TSEL_SHIFT	(8)
+#define USART_TRIGCTRL_TSEL_MASK	(0x3 << USART_TRIGCTRL_TSEL_SHIFT)
+#define USART_TRIGCTRL_TSEL_PRSCHx(v)	\
+	(((v) << USART_TRIGCTRL_TSEL_SHIFT) & USART_TRIGCTRL_TSEL_MASK)
+#define USART_TRIGCTRL_TSEL_PRSCH0	0
+#define USART_TRIGCTRL_TSEL_PRSCH1	1
+#define USART_TRIGCTRL_TSEL_PRSCH2	2
+#define USART_TRIGCTRL_TSEL_PRSCH3	3
+#define USART_TRIGCTRL_TSEL_PRSCH4	4
+#define USART_TRIGCTRL_TSEL_PRSCH5	5
+#define USART_TRIGCTRL_TSEL_PRSCH6	6
+#define USART_TRIGCTRL_TSEL_PRSCH7	7
+
+/* USART_CMD */
+#define USART_CMD_CLEARRX		(1 << 11)
+#define USART_CMD_CLEARTX		(1 << 10)
+#define USART_CMD_TXTRIDIS		(1 << 9)
+#define USART_CMD_TXTRIEN		(1 << 8)
+#define USART_CMD_RXBLOCKDIS		(1 << 7)
+#define USART_CMD_RXBLOCKEN		(1 << 6)
+#define USART_CMD_MASTERDIS		(1 << 5)
+#define USART_CMD_MASTEREN		(1 << 4)
+#define USART_CMD_TXDIS			(1 << 3)
+#define USART_CMD_TXEN			(1 << 2)
+#define USART_CMD_RXDIS			(1 << 1)
+#define USART_CMD_RXEN			(1 << 0)
+
+/* USART_STATUS */
+#define USART_STATUS_RXFULLRIGHT	(1 << 12)
+#define USART_STATUS_RXDATAVRIGHT	(1 << 11)
+#define USART_STATUS_TXBSRIGHT		(1 << 10)
+#define USART_STATUS_TXBDRIGHT		(1 << 9)
+#define USART_STATUS_RXFULL		(1 << 8)
+#define USART_STATUS_RXDATAV		(1 << 7)
+#define USART_STATUS_TXBL		(1 << 6)
+#define USART_STATUS_TXC		(1 << 5)
+#define USART_STATUS_TXTRI		(1 << 4)
+#define USART_STATUS_RXBLOCK		(1 << 3)
+#define USART_STATUS_MASTER		(1 << 2)
+#define USART_STATUS_TXENS		(1 << 1)
+#define USART_STATUS_RXENS		(1 << 0)
+
+/* USART_CLKDIV */
+#define USART_CLKDIV_DIV_SHIFT		(6)
+#define USART_CLKDIV_DIV_MASK		(0x7FFF << USART_CLKDIV_DIV_SHIFT)
+#define USART_CLKDIV_DIV(v)		\
+	(((v) << USART_CLKDIV_DIV_SHIFT) & USART_CLKDIV_DIV_MASK)
+
+/* USART_RXDATAX */
+#define USART_RXDATAX_FERR		(1 << 15)
+#define USART_RXDATAX_PERR		(1 << 14)
+
+#define USART_RXDATAX_RXDATA_SHIFT	(0)
+#define USART_RXDATAX_RXDATA_MASK	(0x1FF << USART_RXDATAX_RXDATA_SHIFT)
+
+/* USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_FERR1		(1 << 31)
+#define USART_RXDOUBLEX_PERR1		(1 << 30)
+
+#define USART_RXDOUBLEX_RXDATA1_SHIFT	(16)
+#define USART_RXDOUBLEX_RXDATA1_MASK	\
+	(0x1FF << USART_RXDOUBLEX_RXDATA1_SHIFT)
+
+#define USART_RXDOUBLEX_FERR0		(1 << 15)
+#define USART_RXDOUBLEX_PERR0		(1 << 14)
+
+#define USART_RXDOUBLEX_RXDATA0_SHIFT	(0)
+#define USART_RXDOUBLEX_RXDATA0_MASK	\
+	(0x1FF << USART_RXDOUBLEX_RXDATA1_SHIFT)
+
+/* USART_RXDOUBLE */
+#define USART_RXDOUBLE_RXDATA1_SHIFT	(8)
+#define USART_RXDOUBLE_RXDATA1_MASK	(0xFF << USART_RXDOUBLE_RXDATA1_SHIFT)
+
+#define USART_RXDOUBLE_RXDATA0_SHIFT	(0)
+#define USART_RXDOUBLE_RXDATA0_MASK	(0xFF << USART_RXDOUBLE_RXDATA0_SHIFT)
+
+/* USART_RXDATAXP */
+#define USART_RXDATAXP_FERRP		(1 << 15)
+#define USART_RXDATAXP_PERRP		(1 << 14)
+
+#define USART_RXDATAXP_RXDATAP_SHIFT	(0)
+#define USART_RXDATAXP_RXDATAP_MASK	(0x1FF << USART_RXDATAXP_RXDATAP_SHIFT)
+
+/* USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_FERR1		(1 << 31)
+#define USART_RXDOUBLEXP_PERR1		(1 << 30)
+
+#define USART_RXDOUBLEXP_RXDATA1_SHIFT	(16)
+#define USART_RXDOUBLEXP_RXDATA1_MASK	\
+	(0x1FF << USART_RXDOUBLEXP_RXDATA1_SHIFT)
+
+#define USART_RXDOUBLEXP_FERR0		(1 << 15)
+#define USART_RXDOUBLEXP_PERR0		(1 << 14)
+
+#define USART_RXDOUBLEXP_RXDATA0_SHIFT	(0)
+#define USART_RXDOUBLEXP_RXDATA0_MASK	\
+	(0x1FF << USART_RXDOUBLEXP_RXDATA1_SHIFT)
+
+/* USART_TXDATAX */
+#define USART_TXDATAX_RXENAT		(1 << 15)
+#define USART_TXDATAX_TXDISAT		(1 << 14)
+#define USART_TXDATAX_TXBREAK		(1 << 13)
+#define USART_TXDATAX_TXTRIAT		(1 << 12)
+#define USART_TXDATAX_UBRXAT		(1 << 11)
+
+#define USART_TXDATAX_TXDATAX_SHIFT	(0)
+#define USART_TXDATAX_TXDATAX_MASK	(0x1FF << USART_TXDATAX_TXDATAX_SHIFT)
+
+/* USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_RXENAT1		(1 << 31)
+#define USART_TXDOUBLEX_TXDISAT1	(1 << 30)
+#define USART_TXDOUBLEX_TXBREAK1	(1 << 29)
+#define USART_TXDOUBLEX_TXTRIAT1	(1 << 28)
+#define USART_TXDOUBLEX_UBRXAT1		(1 << 27)
+
+#define USART_TXDOUBLEX_TXDATA1_SHIFT	(16)
+#define USART_TXDOUBLEX_TXDATA1_MASK	\
+	(0x1FF << USART_TXDOUBLEX_TXDATA1_SHIFT)
+
+#define USART_TXDOUBLEX_RXENAT0		(1 << 15)
+#define USART_TXDOUBLEX_TXDISAT0	(1 << 14)
+#define USART_TXDOUBLEX_TXBREAK0	(1 << 13)
+#define USART_TXDOUBLEX_TXTRIAT0	(1 << 12)
+#define USART_TXDOUBLEX_UBRXAT0		(1 << 11)
+
+#define USART_TXDOUBLEX_TXDATA0_SHIFT	(0)
+#define USART_TXDOUBLEX_TXDATA0_MASK	\
+	(0x1FF << USART_TXDOUBLEX_TXDATA0_SHIFT)
+
+/* USART_TXDOUBLE */
+#define USART_TXDOUBLE_TXDATA1_SHIFT	(8)
+#define USART_TXDOUBLE_TXDATA1_MASK	(0xFF << USART_TXDOUBLE_TXDATA1_SHIFT)
+
+#define USART_TXDOUBLE_TXDATA0_SHIFT	(0)
+#define USART_TXDOUBLE_TXDATA0_MASK	(0xFF << USART_TXDOUBLE_TXDATA0_SHIFT)
+
+/* USART_IF */
+#define USART_IF_CCF			(1 << 12)
+#define USART_IF_SSM			(1 << 11)
+#define USART_IF_MPAF			(1 << 10)
+#define USART_IF_FERR			(1 << 9)
+#define USART_IF_PERR			(1 << 8)
+#define USART_IF_TXUF			(1 << 7)
+#define USART_IF_TXOF			(1 << 6)
+#define USART_IF_RXUF			(1 << 5)
+#define USART_IF_RXOF			(1 << 4)
+#define USART_IF_RXFULL			(1 << 3)
+#define USART_IF_RXDATAV		(1 << 2)
+#define USART_IF_TXBL			(1 << 1)
+#define USART_IF_TXC			(1 << 0)
+
+/* USART_IFS */
+#define USART_IFS_CCF			(1 << 12)
+#define USART_IFS_SSM			(1 << 11)
+#define USART_IFS_MPAF			(1 << 10)
+#define USART_IFS_FERR			(1 << 9)
+#define USART_IFS_PERR			(1 << 8)
+#define USART_IFS_TXUF			(1 << 7)
+#define USART_IFS_TXOF			(1 << 6)
+#define USART_IFS_RXUF			(1 << 5)
+#define USART_IFS_RXOF			(1 << 4)
+#define USART_IFS_RXFULL		(1 << 3)
+#define USART_IFS_RXDATAV		(1 << 2)
+#define USART_IFS_TXBL			(1 << 1)
+#define USART_IFS_TXC			(1 << 0)
+
+/* USART_IFC */
+#define USART_IFC_CCF			(1 << 12)
+#define USART_IFC_SSM			(1 << 11)
+#define USART_IFC_MPAF			(1 << 10)
+#define USART_IFC_FERR			(1 << 9)
+#define USART_IFC_PERR			(1 << 8)
+#define USART_IFC_TXUF			(1 << 7)
+#define USART_IFC_TXOF			(1 << 6)
+#define USART_IFC_RXUF			(1 << 5)
+#define USART_IFC_RXOF			(1 << 4)
+#define USART_IFC_RXFULL		(1 << 3)
+#define USART_IFC_RXDATAV		(1 << 2)
+#define USART_IFC_TXBL			(1 << 1)
+#define USART_IFC_TXC			(1 << 0)
+
+/* USART_IEN */
+#define USART_IEN_CCF			(1 << 12)
+#define USART_IEN_SSM			(1 << 11)
+#define USART_IEN_MPAF			(1 << 10)
+#define USART_IEN_FERR			(1 << 9)
+#define USART_IEN_PERR			(1 << 8)
+#define USART_IEN_TXUF			(1 << 7)
+#define USART_IEN_TXOF			(1 << 6)
+#define USART_IEN_RXUF			(1 << 5)
+#define USART_IEN_RXOF			(1 << 4)
+#define USART_IEN_RXFULL		(1 << 3)
+#define USART_IEN_RXDATAV		(1 << 2)
+#define USART_IEN_TXBL			(1 << 1)
+#define USART_IEN_TXC			(1 << 0)
+
+/* USART_IRCTRL */
+#define USART_IRCTRL_IRPRSEN		(1 << 7)
+
+#define USART_IRCTRL_IRPRSSEL_SHIFT	(4)
+#define USART_IRCTRL_IRPRSSEL_MASK	(0x7 << USART_IRCTRL_IRPRSSEL_SHIFT)
+#define USART_IRCTRL_IRPRSSEL(v)	\
+	(((v) << USART_IRCTRL_IRPRSSEL_SHIFT) & USART_IRCTRL_IRPRSSEL_MASK)
+#define USART_IRCTRL_IRPRSSEL_PRSCHx(x)	USART_IRCTRL_IRPRSSEL(x)
+#define USART_IRCTRL_IRPRSSEL_PRSCH0	0
+#define USART_IRCTRL_IRPRSSEL_PRSCH1	1
+#define USART_IRCTRL_IRPRSSEL_PRSCH2	2
+#define USART_IRCTRL_IRPRSSEL_PRSCH3	3
+#define USART_IRCTRL_IRPRSSEL_PRSCH4	4
+#define USART_IRCTRL_IRPRSSEL_PRSCH5	5
+#define USART_IRCTRL_IRPRSSEL_PRSCH6	6
+#define USART_IRCTRL_IRPRSSEL_PRSCH7	7
+
+#define USART_IRCTRL_IRFILT		(1 << 3)
+
+#define USART_IRCTRL_IRPW_SHIFT		(1)
+#define USART_IRCTRL_IRPW_MASK		(0x3 << USART_IRCTRL_IRPW_SHIFT)
+#define USART_IRCTRL_IRPW(v)		\
+	(((v) << USART_IRCTRL_IRPW_SHIFT) & USART_IRCTRL_IRPW_MASK)
+#define USART_IRCTRL_IRPW_ONE		0
+#define USART_IRCTRL_IRPW_TWO		1
+#define USART_IRCTRL_IRPW_THREE		2
+#define USART_IRCTRL_IRPW_FOUR		3
+
+#define USART_IRCTRL_IREN		(1 << 0)
+
+/* USART_ROUTE */
+#define USART_ROUTE_LOCATION_SHIFT	(8)
+#define USART_ROUTE_LOCATION_MASK	(0x7 << USART_ROUTE_LOCATION_SHIFT)
+#define USART_ROUTE_LOCATION(v)		\
+	(((v) << USART_ROUTE_LOCATION_SHIFT) & USART_ROUTE_LOCATION_MASK)
+#define USART_ROUTE_LOCATION_LOCx(x)	USART_ROUTE_LOCATION(x)
+#define USART_ROUTE_LOCATION_LOC0	0
+#define USART_ROUTE_LOCATION_LOC1	1
+#define USART_ROUTE_LOCATION_LOC2	2
+#define USART_ROUTE_LOCATION_LOC3	3
+#define USART_ROUTE_LOCATION_LOC4	4
+#define USART_ROUTE_LOCATION_LOC5	5
+
+#define USART_ROUTE_CLKPEN		(1 << 3)
+#define USART_ROUTE_CSPEN		(1 << 2)
+#define USART_ROUTE_TXPEN		(1 << 1)
+#define USART_ROUTE_RXPEN		(1 << 0)
+
+/* USART_INPUT */
+#define USART_INPUT_RXPRS		(1 << 4)
+
+#define USART_INPUT_RXPRSSEL_SHIFT	(0)
+#define USART_INPUT_RXPRSSEL_MASK	(0xF << USART_INPUT_RXPRSSEL_SHIFT)
+#define USART_INPUT_RXPRSSEL(v)	\
+	(((v) << USART_INPUT_RXPRSSEL_SHIFT) & USART_INPUT_RXPRSSEL_MASK)
+#define USART_INPUT_RXPRSSEL_PRSCHx(x)	USART_INPUT_RXPRSSEL(x)
+#define USART_INPUT_RXPRSSEL_PRSCH0	0
+#define USART_INPUT_RXPRSSEL_PRSCH1	1
+#define USART_INPUT_RXPRSSEL_PRSCH2	2
+#define USART_INPUT_RXPRSSEL_PRSCH3	3
+#define USART_INPUT_RXPRSSEL_PRSCH4	4
+#define USART_INPUT_RXPRSSEL_PRSCH5	5
+#define USART_INPUT_RXPRSSEL_PRSCH6	6
+#define USART_INPUT_RXPRSSEL_PRSCH7	7
+#define USART_INPUT_RXPRSSEL_PRSCH8	8
+#define USART_INPUT_RXPRSSEL_PRSCH9	9
+#define USART_INPUT_RXPRSSEL_PRSCH10	10
+#define USART_INPUT_RXPRSSEL_PRSCH11	11
+
+/* USART_I2SCTRL */
+#define USART_I2SCTRL_FORMAT_SHIFT	(8)
+#define USART_I2SCTRL_FORMAT_MASK	(0x7 << USART_I2SCTRL_FORMAT_SHIFT)
+#define USART_I2SCTRL_FORMAT(v)	\
+	(((v) << USART_I2SCTRL_FORMAT_SHIFT) & USART_I2SCTRL_FORMAT_MASK)
+#define USART_I2SCTRL_FORMAT_W32D32	0
+#define USART_I2SCTRL_FORMAT_W32D24M	1
+#define USART_I2SCTRL_FORMAT_W32D24	2
+#define USART_I2SCTRL_FORMAT_W32D16	3
+#define USART_I2SCTRL_FORMAT_W32D8	4
+#define USART_I2SCTRL_FORMAT_W16D16	5
+#define USART_I2SCTRL_FORMAT_W16D8	6
+#define USART_I2SCTRL_FORMAT_W8D8	7
+
+#define USART_I2SCTRL_DELAY		(1 << 4)
+#define USART_I2SCTRL_DMASPLIT		(1 << 3)
+#define USART_I2SCTRL_JUSTIFY		(1 << 2)
+#define USART_I2SCTRL_MONO		(1 << 1)
+#define USART_I2SCTRL_EN		(1 << 0)
+
+/* USART0 */
+#define USART0				USART0_BASE
+#define USART0_CTRL			USART_CTRL(USART0)
+#define USART0_FRAME			USART_FRAME(USART0)
+#define USART0_TRIGCTRL			USART_TRIGCTRL(USART0)
+#define USART0_CMD			USART_CMD(USART0)
+#define USART0_STATUS			USART_STATUS(USART0)
+#define USART0_CLKDIV			USART_CLKDIV(USART0)
+#define USART0_RXDATAX			USART_RXDATAX(USART0)
+#define USART0_RXDATA			USART_RXDATA(USART0)
+#define USART0_RXDOUBLEX		USART_RXDOUBLEX(USART0)
+#define USART0_RXDOUBLE			USART_RXDOUBLE(USART0)
+#define USART0_RXDATAXP			USART_RXDATAXP(USART0)
+#define USART0_RXDOUBLEXP		USART_RXDOUBLEXP(USART0)
+#define USART0_TXDATAX			USART_TXDATAX(USART0)
+#define USART0_TXDATA			USART_TXDATA(USART0)
+#define USART0_TXDOUBLEX		USART_TXDOUBLEX(USART0)
+#define USART0_TXDOUBLE			USART_TXDOUBLE(USART0)
+#define USART0_IF			USART_IF(USART0)
+#define USART0_IFS			USART_IFS(USART0)
+#define USART0_IFC			USART_IFC(USART0)
+#define USART0_IEN			USART_IEN(USART0)
+#define USART0_IRCTRL			USART_IRCTRL(USART0)
+#define USART0_ROUTE			USART_ROUTE(USART0)
+#define USART0_INPUT			USART_INPUT(USART0)
+#define USART0_I2SCTRL			USART_I2SCTRL(USART0)
+
+/* USART1 */
+#define USART1				USART1_BASE
+#define USART1_CTRL			USART_CTRL(USART1)
+#define USART1_FRAME			USART_FRAME(USART1)
+#define USART1_TRIGCTRL			USART_TRIGCTRL(USART1)
+#define USART1_CMD			USART_CMD(USART1)
+#define USART1_STATUS			USART_STATUS(USART1)
+#define USART1_CLKDIV			USART_CLKDIV(USART1)
+#define USART1_RXDATAX			USART_RXDATAX(USART1)
+#define USART1_RXDATA			USART_RXDATA(USART1)
+#define USART1_RXDOUBLEX		USART_RXDOUBLEX(USART1)
+#define USART1_RXDOUBLE			USART_RXDOUBLE(USART1)
+#define USART1_RXDATAXP			USART_RXDATAXP(USART1)
+#define USART1_RXDOUBLEXP		USART_RXDOUBLEXP(USART1)
+#define USART1_TXDATAX			USART_TXDATAX(USART1)
+#define USART1_TXDATA			USART_TXDATA(USART1)
+#define USART1_TXDOUBLEX		USART_TXDOUBLEX(USART1)
+#define USART1_TXDOUBLE			USART_TXDOUBLE(USART1)
+#define USART1_IF			USART_IF(USART1)
+#define USART1_IFS			USART_IFS(USART1)
+#define USART1_IFC			USART_IFC(USART1)
+#define USART1_IEN			USART_IEN(USART1)
+#define USART1_IRCTRL			USART_IRCTRL(USART1)
+#define USART1_ROUTE			USART_ROUTE(USART1)
+#define USART1_INPUT			USART_INPUT(USART1)
+#define USART1_I2SCTRL			USART_I2SCTRL(USART1)
+
+/* USART2 */
+#define USART2				USART2_BASE
+#define USART2_CTRL			USART_CTRL(USART2)
+#define USART2_FRAME			USART_FRAME(USART2)
+#define USART2_TRIGCTRL			USART_TRIGCTRL(USART2)
+#define USART2_CMD			USART_CMD(USART2)
+#define USART2_STATUS			USART_STATUS(USART2)
+#define USART2_CLKDIV			USART_CLKDIV(USART2)
+#define USART2_RXDATAX			USART_RXDATAX(USART2)
+#define USART2_RXDATA			USART_RXDATA(USART2)
+#define USART2_RXDOUBLEX		USART_RXDOUBLEX(USART2)
+#define USART2_RXDOUBLE			USART_RXDOUBLE(USART2)
+#define USART2_RXDATAXP			USART_RXDATAXP(USART2)
+#define USART2_RXDOUBLEXP		USART_RXDOUBLEXP(USART2)
+#define USART2_TXDATAX			USART_TXDATAX(USART2)
+#define USART2_TXDATA			USART_TXDATA(USART2)
+#define USART2_TXDOUBLEX		USART_TXDOUBLEX(USART2)
+#define USART2_TXDOUBLE			USART_TXDOUBLE(USART2)
+#define USART2_IF			USART_IF(USART2)
+#define USART2_IFS			USART_IFS(USART2)
+#define USART2_IFC			USART_IFC(USART2)
+#define USART2_IEN			USART_IEN(USART2)
+#define USART2_IRCTRL			USART_IRCTRL(USART2)
+#define USART2_ROUTE			USART_ROUTE(USART2)
+#define USART2_INPUT			USART_INPUT(USART2)
+#define USART2_I2SCTRL			USART_I2SCTRL(USART2)
+
+/**@}*/

3rd/libopencm3/include/libopencm3/efm32/common/usb_common.h

@@ -0,0 +1,371 @@
+/** @addtogroup usb_defines
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/usb/usbd.h>
+
+/**@{*/
+
+#define USB_CTRL			MMIO32(USB_BASE + 0x000)
+#define USB_STATUS			MMIO32(USB_BASE + 0x004)
+#define USB_IF				MMIO32(USB_BASE + 0x008)
+#define USB_IFS				MMIO32(USB_BASE + 0x00C)
+#define USB_IFC				MMIO32(USB_BASE + 0x010)
+#define USB_IEN				MMIO32(USB_BASE + 0x014)
+#define USB_ROUTE			MMIO32(USB_BASE + 0x018)
+
+/* USB_CTRL */
+#define USB_CTRL_DMPUAP			(1 << 1)
+
+/* USB_ROUTE */
+#define USB_ROUTE_DMPUPEN		(1 << 2)
+#define USB_ROUTE_VBUSENPEN		(1 << 1)
+#define USB_ROUTE_PHYPEN		(1 << 0)
+
+/* Core Global Control and Status Registers */
+#define USB_OTG_BASE			(USB_BASE + 0x3C000)
+#define USB_GOTGCTL			MMIO32(USB_OTG_BASE + 0x000)
+#define USB_GOTGINT			MMIO32(USB_OTG_BASE + 0x004)
+#define USB_GAHBCFG			MMIO32(USB_OTG_BASE + 0x008)
+#define USB_GUSBCFG			MMIO32(USB_OTG_BASE + 0x00C)
+#define USB_GRSTCTL			MMIO32(USB_OTG_BASE + 0x010)
+#define USB_GINTSTS			MMIO32(USB_OTG_BASE + 0x014)
+#define USB_GINTMSK			MMIO32(USB_OTG_BASE + 0x018)
+#define USB_GRXSTSR			MMIO32(USB_OTG_BASE + 0x01C)
+#define USB_GRXSTSP			MMIO32(USB_OTG_BASE + 0x020)
+#define USB_GRXFSIZ			MMIO32(USB_OTG_BASE + 0x024)
+#define USB_GNPTXFSIZ			MMIO32(USB_OTG_BASE + 0x028)
+#define USB_GNPTXSTS			MMIO32(USB_OTG_BASE + 0x02C)
+#define USB_GDFIFOCFG			MMIO32(USB_OTG_BASE + 0x05C)
+#define USB_HPTXFSIZ			MMIO32(USB_OTG_BASE + 0x100)
+#define USB_DIEPTXF(x)			\
+	MMIO32(USB_OTG_BASE + 0x104 + (4 * ((x) - 1)))
+
+/* Host-mode Control and Status Registers */
+#define USB_HCFG			MMIO32(USB_OTG_BASE + 0x400)
+#define USB_HFIR			MMIO32(USB_OTG_BASE + 0x404)
+#define USB_HFNUM			MMIO32(USB_OTG_BASE + 0x408)
+#define USB_HPTXSTS			MMIO32(USB_OTG_BASE + 0x410)
+#define USB_HAINT			MMIO32(USB_OTG_BASE + 0x414)
+#define USB_HAINTMSK			MMIO32(USB_OTG_BASE + 0x418)
+#define USB_HPRT			MMIO32(USB_OTG_BASE + 0x440)
+#define USB_HCx_CHAR(x)			\
+	MMIO32(USB_OTG_BASE + 0x500 + ((x) * 0x20))
+#define USB_HCx_INT(x)			\
+	MMIO32(USB_OTG_BASE + 0x508 + ((x) * 0x20))
+#define USB_HCx_INTMSK(x)		\
+	MMIO32(USB_OTG_BASE + 0x50C + ((x) * 0x20))
+#define USB_HCx_TSIZ(x)			\
+	MMIO32(USB_OTG_BASE + 0x510 + ((x) * 0x20))
+#define USB_HCx_DMAADDR(x)		\
+	MMIO32(USB_OTG_BASE + 0x514 + ((x) * 0x20))
+
+/* Device-mode Control and Status Registers */
+#define USB_DCFG			MMIO32(USB_OTG_BASE + 0x800)
+#define USB_DCTL			MMIO32(USB_OTG_BASE + 0x804)
+#define USB_DSTS			MMIO32(USB_OTG_BASE + 0x808)
+#define USB_DIEPMSK			MMIO32(USB_OTG_BASE + 0x810)
+#define USB_DOEPMSK			MMIO32(USB_OTG_BASE + 0x814)
+#define USB_DAINT			MMIO32(USB_OTG_BASE + 0x818)
+#define USB_DAINTMSK			MMIO32(USB_OTG_BASE + 0x81C)
+#define USB_DVBUSDIS			MMIO32(USB_OTG_BASE + 0x828)
+#define USB_DVBUSPULSE			MMIO32(USB_OTG_BASE + 0x82C)
+#define USB_DIEPEMPMSK			MMIO32(USB_OTG_BASE + 0x834)
+
+#define USB_DIEPx_CTL(x)		\
+	MMIO32(USB_OTG_BASE + 0x900 + ((x) * 0x20))
+#define USB_DIEPx_INT(x)		\
+	MMIO32(USB_OTG_BASE + 0x908 + ((x) * 0x20))
+#define USB_DIEPx_TSIZ(x)		\
+	MMIO32(USB_OTG_BASE + 0x910 + ((x) * 0x20))
+#define USB_DIEP0CTL			USB_DIEPx_CTL(0)
+#define USB_DIEP0TSIZ			USB_DIEPx_TSIZ(0)
+#define USB_DIEP0INT			USB_DIEPx_INT(0)
+
+#define USB_DOEPx_CTL(x)		\
+	MMIO32(USB_OTG_BASE + 0xB00 + ((x) * 0x20))
+#define USB_DOEPx_INT(x)		\
+	MMIO32(USB_OTG_BASE + 0xB08 + ((x) * 0x20))
+#define USB_DOEPx_TSIZ(x)		\
+	MMIO32(USB_OTG_BASE + 0xB10 + ((x) * 0x20))
+#define USB_DOEP0CTL			USB_DOEPx_CTL(0)
+#define USB_DOEP0TSIZ			USB_DOEPx_TSIZ(0)
+#define USB_DOEP0INT			USB_DOEPx_INT(0)
+
+/* Power and clock gating control and status register */
+#define USB_PCGCCTL			MMIO32(USB_OTG_BASE + 0xE00)
+
+/* Data FIFO */
+#define USB_FIFOxD(x)			\
+	(&MMIO32(USB_OTG_BASE + (((x) + 1) << 12)))
+
+/* Global CSRs */
+/* USB control registers (OTG_HS_GOTGCTL) */
+#define USB_GOTGCTL_BSVLD		(1 << 19)
+#define USB_GOTGCTL_ASVLD		(1 << 18)
+#define USB_GOTGCTL_DBCT		(1 << 17)
+#define USB_GOTGCTL_CIDSTS		(1 << 16)
+#define USB_GOTGCTL_DHNPEN		(1 << 11)
+#define USB_GOTGCTL_HSHNPEN		(1 << 10)
+#define USB_GOTGCTL_HNPRQ		(1 << 9)
+#define USB_GOTGCTL_HNGSCS		(1 << 8)
+#define USB_GOTGCTL_SRQ			(1 << 1)
+#define USB_GOTGCTL_SRQSCS		(1 << 0)
+
+/* AHB configuration register (USB_GAHBCFG) */
+#define USB_GAHBCFG_GLBLINTRMSK		0x0001
+#define USB_GAHBCFG_TXFELVL		0x0080
+#define USB_GAHBCFG_PTXFELVL		0x0100
+
+/* USB configuration register (USB_GUSBCFG) */
+#define USB_GUSBCFG_TOCAL		0x00000003
+#define USB_GUSBCFG_SRPCAP		0x00000100
+#define USB_GUSBCFG_HNPCAP		0x00000200
+#define USB_GUSBCFG_TRDT_MASK		(0xf << 10)
+#define USB_GUSBCFG_TRDT_16BIT		(0x5 << 10)
+#define USB_GUSBCFG_TRDT_8BIT		(0x9 << 10)
+#define USB_GUSBCFG_NPTXRWEN		0x00004000
+#define USB_GUSBCFG_FHMOD		0x20000000
+#define USB_GUSBCFG_FDMOD		0x40000000
+#define USB_GUSBCFG_CTXPKT		0x80000000
+#define USB_GUSBCFG_PHYSEL		(1 << 7)
+
+/* reset register (USB_GRSTCTL) */
+#define USB_GRSTCTL_AHBIDL		(1 << 31)
+/* Bits 30:11 - Reserved */
+#define USB_GRSTCTL_TXFNUM_MASK		(0x1f << 6)
+#define USB_GRSTCTL_TXFFLSH		(1 << 5)
+#define USB_GRSTCTL_RXFFLSH		(1 << 4)
+/* Bit 3 - Reserved */
+#define USB_GRSTCTL_FCRST		(1 << 2)
+#define USB_GRSTCTL_HSRST		(1 << 1)
+#define USB_GRSTCTL_CSRST		(1 << 0)
+
+/* interrupt status register (USB_GINTSTS) */
+#define USB_GINTSTS_WKUPINT		(1 << 31)
+#define USB_GINTSTS_SRQINT		(1 << 30)
+#define USB_GINTSTS_DISCINT		(1 << 29)
+#define USB_GINTSTS_CIDSCHG		(1 << 28)
+/* Bit 27 - Reserved */
+#define USB_GINTSTS_PTXFE		(1 << 26)
+#define USB_GINTSTS_HCINT		(1 << 25)
+#define USB_GINTSTS_HPRTINT		(1 << 24)
+/* Bits 23:22 - Reserved */
+#define USB_GINTSTS_IPXFR		(1 << 21)
+#define USB_GINTSTS_INCOMPISOOUT	(1 << 21)
+#define USB_GINTSTS_IISOIXFR		(1 << 20)
+#define USB_GINTSTS_OEPINT		(1 << 19)
+#define USB_GINTSTS_IEPINT		(1 << 18)
+/* Bits 17:16 - Reserved */
+#define USB_GINTSTS_EOPF		(1 << 15)
+#define USB_GINTSTS_ISOODRP		(1 << 14)
+#define USB_GINTSTS_ENUMDNE		(1 << 13)
+#define USB_GINTSTS_USBRST		(1 << 12)
+#define USB_GINTSTS_USBSUSP		(1 << 11)
+#define USB_GINTSTS_ESUSP		(1 << 10)
+/* Bits 9:8 - Reserved */
+#define USB_GINTSTS_GONAKEFF		(1 << 7)
+#define USB_GINTSTS_GINAKEFF		(1 << 6)
+#define USB_GINTSTS_NPTXFE		(1 << 5)
+#define USB_GINTSTS_RXFLVL		(1 << 4)
+#define USB_GINTSTS_SOF			(1 << 3)
+#define USB_GINTSTS_OTGINT		(1 << 2)
+#define USB_GINTSTS_MMIS		(1 << 1)
+#define USB_GINTSTS_CMOD		(1 << 0)
+
+/* interrupt mask register (USB_GINTMSK) */
+#define USB_GINTMSK_MMISM		0x00000002
+#define USB_GINTMSK_OTGINT		0x00000004
+#define USB_GINTMSK_SOFM		0x00000008
+#define USB_GINTMSK_RXFLVLM		0x00000010
+#define USB_GINTMSK_NPTXFEM		0x00000020
+#define USB_GINTMSK_GINAKEFFM		0x00000040
+#define USB_GINTMSK_GONAKEFFM		0x00000080
+#define USB_GINTMSK_ESUSPM		0x00000400
+#define USB_GINTMSK_USBSUSPM		0x00000800
+#define USB_GINTMSK_USBRST		0x00001000
+#define USB_GINTMSK_ENUMDNEM		0x00002000
+#define USB_GINTMSK_ISOODRPM		0x00004000
+#define USB_GINTMSK_EOPFM		0x00008000
+#define USB_GINTMSK_EPMISM		0x00020000
+#define USB_GINTMSK_IEPINT		0x00040000
+#define USB_GINTMSK_OEPINT		0x00080000
+#define USB_GINTMSK_IISOIXFRM		0x00100000
+#define USB_GINTMSK_IISOOXFRM		0x00200000
+#define USB_GINTMSK_IPXFRM		0x00200000
+#define USB_GINTMSK_PRTIM		0x01000000
+#define USB_GINTMSK_HCIM		0x02000000
+#define USB_GINTMSK_PTXFEM		0x04000000
+#define USB_GINTMSK_CIDSCHGM		0x10000000
+#define USB_GINTMSK_DISCINT		0x20000000
+#define USB_GINTMSK_SRQIM		0x40000000
+#define USB_GINTMSK_WUIM		0x80000000
+
+/* Receive Status Pop Register (USB_GRXSTSP) */
+/* Bits 31:25 - Reserved */
+#define USB_GRXSTSP_FRMNUM_MASK		(0xf << 21)
+#define USB_GRXSTSP_PKTSTS_MASK		(0xf << 17)
+#define USB_GRXSTSP_PKTSTS_GOUTNAK	(0x1 << 17)
+#define USB_GRXSTSP_PKTSTS_OUT		(0x2 << 17)
+#define USB_GRXSTSP_PKTSTS_OUT_COMP	(0x3 << 17)
+#define USB_GRXSTSP_PKTSTS_SETUP_COMP	(0x4 << 17)
+#define USB_GRXSTSP_PKTSTS_SETUP	(0x6 << 17)
+#define USB_GRXSTSP_DPID_MASK		(0x3 << 15)
+#define USB_GRXSTSP_DPID_DATA0		(0x0 << 15)
+#define USB_GRXSTSP_DPID_DATA1		(0x2 << 15)
+#define USB_GRXSTSP_DPID_DATA2		(0x1 << 15)
+#define USB_GRXSTSP_DPID_MDATA		(0x3 << 15)
+#define USB_GRXSTSP_BCNT_MASK		(0x7ff << 4)
+#define USB_GRXSTSP_EPNUM_MASK		(0xf << 0)
+
+/* general core configuration register (USB_GCCFG) */
+/* Bits 31:22 - Reserved */
+#define USB_GCCFG_NOVBUSSENS		(1 << 21)
+#define USB_GCCFG_SOFOUTEN		(1 << 20)
+#define USB_GCCFG_VBUSBSEN		(1 << 19)
+#define USB_GCCFG_VBUSASEN		(1 << 18)
+/* Bit 17 - Reserved */
+#define USB_GCCFG_PWRDWN		(1 << 16)
+/* Bits 15:0 - Reserved */
+
+
+/* Device-mode CSRs */
+/* device control register (USB_DCTL) */
+/* Bits 31:12 - Reserved */
+#define USB_DCTL_POPRGDNE		(1 << 11)
+#define USB_DCTL_CGONAK			(1 << 10)
+#define USB_DCTL_SGONAK			(1 << 9)
+#define USB_DCTL_SGINAK			(1 << 8)
+#define USB_DCTL_TCTL_MASK		(7 << 4)
+#define USB_DCTL_GONSTS			(1 << 3)
+#define USB_DCTL_GINSTS			(1 << 2)
+#define USB_DCTL_SDIS			(1 << 1)
+#define USB_DCTL_RWUSIG			(1 << 0)
+
+/* device configuration register (USB_DCFG) */
+#define USB_DCFG_DSPD			0x0003
+#define USB_DCFG_NZLSOHSK		0x0004
+#define USB_DCFG_DAD			0x07F0
+#define USB_DCFG_PFIVL			0x1800
+
+/* Device IN Endpoint Common Interrupt Mask Register (USB_DIEPMSK) */
+/* Bits 31:10 - Reserved */
+#define USB_DIEPMSK_BIM			(1 << 9)
+#define USB_DIEPMSK_TXFURM		(1 << 8)
+/* Bit 7 - Reserved */
+#define USB_DIEPMSK_INEPNEM		(1 << 6)
+#define USB_DIEPMSK_INEPNMM		(1 << 5)
+#define USB_DIEPMSK_ITTXFEMSK		(1 << 4)
+#define USB_DIEPMSK_TOM			(1 << 3)
+/* Bit 2 - Reserved */
+#define USB_DIEPMSK_EPDM		(1 << 1)
+#define USB_DIEPMSK_XFRCM		(1 << 0)
+
+/* Device OUT Endpoint Common Interrupt Mask Register (USB_DOEPMSK) */
+/* Bits 31:10 - Reserved */
+#define USB_DOEPMSK_BOIM		(1 << 9)
+#define USB_DOEPMSK_OPEM		(1 << 8)
+/* Bit 7 - Reserved */
+#define USB_DOEPMSK_B2BSTUP		(1 << 6)
+/* Bit 5 - Reserved */
+#define USB_DOEPMSK_OTEPDM		(1 << 4)
+#define USB_DOEPMSK_STUPM		(1 << 3)
+/* Bit 2 - Reserved */
+#define USB_DOEPMSK_EPDM		(1 << 1)
+#define USB_DOEPMSK_XFRCM		(1 << 0)
+
+/* Device Control IN Endpoint 0 Control Register (USB_DIEP0CTL) */
+#define USB_DIEP0CTL_EPENA		(1 << 31)
+#define USB_DIEP0CTL_EPDIS		(1 << 30)
+/* Bits 29:28 - Reserved */
+#define USB_DIEP0CTL_SD0PID		(1 << 28)
+#define USB_DIEP0CTL_SNAK		(1 << 27)
+#define USB_DIEP0CTL_CNAK		(1 << 26)
+#define USB_DIEP0CTL_TXFNUM_MASK	(0xf << 22)
+#define USB_DIEP0CTL_STALL		(1 << 21)
+/* Bit 20 - Reserved */
+#define USB_DIEP0CTL_EPTYP_MASK		(0x3 << 18)
+#define USB_DIEP0CTL_NAKSTS		(1 << 17)
+/* Bit 16 - Reserved */
+#define USB_DIEP0CTL_USBAEP		(1 << 15)
+/* Bits 14:2 - Reserved */
+#define USB_DIEP0CTL_MPSIZ_MASK		(0x3 << 0)
+#define USB_DIEP0CTL_MPSIZ_64		(0x0 << 0)
+#define USB_DIEP0CTL_MPSIZ_32		(0x1 << 0)
+#define USB_DIEP0CTL_MPSIZ_16		(0x2 << 0)
+#define USB_DIEP0CTL_MPSIZ_8		(0x3 << 0)
+
+/* Device Control OUT Endpoint 0 Control Register (USB_DOEP0CTL) */
+#define USB_DOEP0CTL_EPENA		(1 << 31)
+#define USB_DOEP0CTL_EPDIS		(1 << 30)
+/* Bits 29:28 - Reserved */
+#define USB_DOEP0CTL_SD0PID		(1 << 28)
+#define USB_DOEP0CTL_SNAK		(1 << 27)
+#define USB_DOEP0CTL_CNAK		(1 << 26)
+/* Bits 25:22 - Reserved */
+#define USB_DOEP0CTL_STALL		(1 << 21)
+#define USB_DOEP0CTL_SNPM		(1 << 20)
+#define USB_DOEP0CTL_EPTYP_MASK		(0x3 << 18)
+#define USB_DOEP0CTL_NAKSTS		(1 << 17)
+/* Bit 16 - Reserved */
+#define USB_DOEP0CTL_USBAEP		(1 << 15)
+/* Bits 14:2 - Reserved */
+#define USB_DOEP0CTL_MPSIZ_MASK		(0x3 << 0)
+#define USB_DOEP0CTL_MPSIZ_64		(0x0 << 0)
+#define USB_DOEP0CTL_MPSIZ_32		(0x1 << 0)
+#define USB_DOEP0CTL_MPSIZ_16		(0x2 << 0)
+#define USB_DOEP0CTL_MPSIZ_8		(0x3 << 0)
+
+/* Device IN Endpoint Interrupt Register (USB_DIEPINTx) */
+/* Bits 31:8 - Reserved */
+#define USB_DIEP_INT_TXFE		(1 << 7)
+#define USB_DIEP_INT_INEPNE		(1 << 6)
+/* Bit 5 - Reserved */
+#define USB_DIEP_INT_ITTXFE		(1 << 4)
+#define USB_DIEP_INT_TOC		(1 << 3)
+/* Bit 2 - Reserved */
+#define USB_DIEP_INT_EPDISD		(1 << 1)
+#define USB_DIEP_INT_XFRC		(1 << 0)
+
+/* Device IN Endpoint Interrupt Register (USB_DOEPINTx) */
+/* Bits 31:7 - Reserved */
+#define USB_DOEP_INT_B2BSTUP		(1 << 6)
+/* Bit 5 - Reserved */
+#define USB_DOEP_INT_OTEPDIS		(1 << 4)
+#define USB_DOEP_INT_SETUP		(1 << 3)
+/* Bit 2 - Reserved */
+#define USB_DOEP_INT_EPDISD		(1 << 1)
+#define USB_DOEP_INT_XFRC		(1 << 0)
+
+/* Device OUT Endpoint 0 Transfer Size Register (USB_DOEP0TSIZ) */
+/* Bit 31 - Reserved */
+#define USB_DIEP0TSIZ_STUPCNT_1		(0x1 << 29)
+#define USB_DIEP0TSIZ_STUPCNT_2		(0x2 << 29)
+#define USB_DIEP0TSIZ_STUPCNT_3		(0x3 << 29)
+#define USB_DIEP0TSIZ_STUPCNT_MASK	(0x3 << 29)
+/* Bits 28:20 - Reserved */
+#define USB_DIEP0TSIZ_PKTCNT		(1 << 19)
+/* Bits 18:7 - Reserved */
+#define USB_DIEP0TSIZ_XFRSIZ_MASK	(0x7f << 0)
+
+/**@}*/

3rd/libopencm3/include/libopencm3/efm32/common/wdog_common.h

@@ -0,0 +1,78 @@
+/** @addtogroup wdog_defines
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/efm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/**@{*/
+
+#define WDOG_CTRL			MMIO32(WDOG_BASE + 0x000)
+#define WDOG_CMD			MMIO32(WDOG_BASE + 0x004)
+#define WDOG_SYNCBUSY			MMIO32(WDOG_BASE + 0x008)
+
+/* WDOG_CTRL */
+#define WDOG_CTRL_CLKSEL_SHIFT		(12)
+#define WDOG_CTRL_CLKSEL_MASK		(0x3 << WDOG_CTRL_CLKSEL_SHIFT)
+#define WDOG_CTRL_CLKSEL(v)		\
+	(((v) << WDOG_CTRL_CLKSEL_SHIFT) & WDOG_CTRL_CLKSEL_MASK)
+#define WDOG_CTRL_CLKSEL_ULFRCO		0
+#define WDOG_CTRL_CLKSEL_LFRCO		1
+#define WDOG_CTRL_CLKSEL_LFXO		2
+
+#define WDOG_CTRL_PERSEL_SHIFT		(8)
+#define WDOG_CTRL_PERSEL_MASK		(0xF << WDOG_CTRL_PERSEL_SHIFT)
+#define WDOG_CTRL_PERSEL(v)				\
+	(((v) << WDOG_CTRL_PERSEL_SHIFT) & WDOG_CTRL_PERSEL_MASK)
+#define WDOG_CTRL_PERSEL_9CYCLES	0
+#define WDOG_CTRL_PERSEL_17CYCLES	1
+#define WDOG_CTRL_PERSEL_33CYCLES	2
+#define WDOG_CTRL_PERSEL_65CYCLES	3
+#define WDOG_CTRL_PERSEL_129CYCLES	4
+#define WDOG_CTRL_PERSEL_257CYCLES	5
+#define WDOG_CTRL_PERSEL_513CYCLES	6
+#define WDOG_CTRL_PERSEL_1KCYCLES	7
+#define WDOG_CTRL_PERSEL_2KCYCLES	8
+#define WDOG_CTRL_PERSEL_4KCYCLES	9
+#define WDOG_CTRL_PERSEL_8KCYCLES	10
+#define WDOG_CTRL_PERSEL_16KCYCLES	11
+#define WDOG_CTRL_PERSEL_32KCYCLES	12
+#define WDOG_CTRL_PERSEL_64KCYCLES	13
+#define WDOG_CTRL_PERSEL_128KCYCLES	14
+#define WDOG_CTRL_PERSEL_256KCYCLES	15
+
+#define WDOG_CTRL_SWOSCBLOCK		(1 << 6)
+#define WDOG_CTRL_EM4BLOCK		(1 << 5)
+#define WDOG_CTRL_LOCK			(1 << 4)
+#define WDOG_CTRL_EM3RUN		(1 << 3)
+#define WDOG_CTRL_EM2RUN		(1 << 2)
+#define WDOG_CTRL_DEBUGRUN		(1 << 1)
+#define WDOG_CTRL_EN			(1 << 0)
+
+/* WDOG_CMD */
+#define WDOG_CMD_CLEAR			(1 << 0)
+
+/* WDOG_SYNCBUSY */
+#define WDOG_SYNCBUSY_CMD		(1 << 1)
+#define WDOG_SYNCBUSY_CTRL		(1 << 0)
+
+/**@}*/

3rd/libopencm3/include/libopencm3/efm32/common/wdog_common_hglg.h

@@ -0,0 +1,78 @@
+/** @addtogroup wdog_defines
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/efm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/**@{*/
+
+#define WDOG_CTRL			MMIO32(WDOG_BASE + 0x000)
+#define WDOG_CMD			MMIO32(WDOG_BASE + 0x004)
+#define WDOG_SYNCBUSY			MMIO32(WDOG_BASE + 0x008)
+
+/* WDOG_CTRL */
+#define WDOG_CTRL_CLKSEL_SHIFT		(12)
+#define WDOG_CTRL_CLKSEL_MASK		(0x3 << WDOG_CTRL_CLKSEL_SHIFT)
+#define WDOG_CTRL_CLKSEL(v)		\
+	(((v) << WDOG_CTRL_CLKSEL_SHIFT) & WDOG_CTRL_CLKSEL_MASK)
+#define WDOG_CTRL_CLKSEL_ULFRCO		WDOG_CTRL_CLKSEL(0)
+#define WDOG_CTRL_CLKSEL_LFRCO		WDOG_CTRL_CLKSEL(1)
+#define WDOG_CTRL_CLKSEL_LFXO		WDOG_CTRL_CLKSEL(2)
+
+#define WDOG_CTRL_PERSEL_SHIFT		(8)
+#define WDOG_CTRL_PERSEL_MASK		(0xF << WDOG_CTRL_PERSEL_SHIFT)
+#define WDOG_CTRL_PERSEL(v)				\
+	(((v) << WDOG_CTRL_PERSEL_SHIFT) & WDOG_CTRL_PERSEL_MASK)
+#define WDOG_CTRL_PERSEL_9CYCLES	WDOG_CTRL_PERSEL(0)
+#define WDOG_CTRL_PERSEL_17CYCLES	WDOG_CTRL_PERSEL(1)
+#define WDOG_CTRL_PERSEL_33CYCLES	WDOG_CTRL_PERSEL(2)
+#define WDOG_CTRL_PERSEL_65CYCLES	WDOG_CTRL_PERSEL(3)
+#define WDOG_CTRL_PERSEL_129CYCLES	WDOG_CTRL_PERSEL(4)
+#define WDOG_CTRL_PERSEL_257CYCLES	WDOG_CTRL_PERSEL(5)
+#define WDOG_CTRL_PERSEL_513CYCLES	WDOG_CTRL_PERSEL(6)
+#define WDOG_CTRL_PERSEL_1KCYCLES	WDOG_CTRL_PERSEL(7)
+#define WDOG_CTRL_PERSEL_2KCYCLES	WDOG_CTRL_PERSEL(8)
+#define WDOG_CTRL_PERSEL_4KCYCLES	WDOG_CTRL_PERSEL(9)
+#define WDOG_CTRL_PERSEL_8KCYCLES	WDOG_CTRL_PERSEL(10)
+#define WDOG_CTRL_PERSEL_16KCYCLES	WDOG_CTRL_PERSEL(11)
+#define WDOG_CTRL_PERSEL_32KCYCLES	WDOG_CTRL_PERSEL(12)
+#define WDOG_CTRL_PERSEL_64KCYCLES	WDOG_CTRL_PERSEL(13)
+#define WDOG_CTRL_PERSEL_128KCYCLES	WDOG_CTRL_PERSEL(14)
+#define WDOG_CTRL_PERSEL_256KCYCLES	WDOG_CTRL_PERSEL(15)
+
+#define WDOG_CTRL_SWOSCBLOCK		(1 << 6)
+#define WDOG_CTRL_EM4BLOCK		(1 << 5)
+#define WDOG_CTRL_LOCK			(1 << 4)
+#define WDOG_CTRL_EM3RUN		(1 << 3)
+#define WDOG_CTRL_EM2RUN		(1 << 2)
+#define WDOG_CTRL_DEBUGRUN		(1 << 1)
+#define WDOG_CTRL_EN			(1 << 0)
+
+/* WDOG_CMD */
+#define WDOG_CMD_CLEAR			(1 << 0)
+
+/* WDOG_SYNCBUSY */
+#define WDOG_SYNCBUSY_CMD		(1 << 1)
+#define WDOG_SYNCBUSY_CTRL		(1 << 0)
+
+/**@}*/

3rd/libopencm3/include/libopencm3/efm32/dac.h

@@ -0,0 +1,28 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#if defined(EFM32LG)
+#	include <libopencm3/efm32/lg/dac.h>
+#elif defined(EFM32WG)
+#	include <libopencm3/efm32/wg/dac.h>
+#elif defined(EZR32WG)
+#	include <libopencm3/efm32/ezr32wg/dac.h>
+#else
+#	error "efm32 family not defined."
+#endif