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  1. /** @defgroup rcc_file RCC Controller
  2. @brief <b>LM3S RCC Controller</b>
  3. @ingroup LM3Sxx
  4. @version 1.0.0
  5. @author @htmlonly &copy; @endhtmlonly 2015
  6. Daniele Lacamera \<root at danielinux dot net\>
  7. @date 21 November 2015
  8. LGPL License Terms @ref lgpl_license
  9. */
  10. /*
  11. * This file is part of the libopencm3 project.
  12. *
  13. * Copyright (C) 2015 Daniele Lacamera <root@danielinux.net>
  14. *
  15. * This library is free software: you can redistribute it and/or modify
  16. * it under the terms of the GNU Lesser General Public License as published by
  17. * the Free Software Foundation, either version 3 of the License, or
  18. * (at your option) any later version.
  19. *
  20. * This library is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU Lesser General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU Lesser General Public License
  26. * along with this library. If not, see <http://www.gnu.org/licenses/>.
  27. */
  28. #include <stdint.h>
  29. #include <libopencm3/lm3s/rcc.h>
  30. #include <libopencm3/cm3/sync.h>
  31. int rcc_clock_setup_in_xtal_8mhz_out_50mhz(void)
  32. {
  33. uint32_t rcc = RCC_RESET_VALUE;
  34. uint32_t rcc2 = RCC2_RESET_VALUE;
  35. /* Stage 0: Reset values applied */
  36. RCC_CR = rcc;
  37. RCC2_CR = rcc2;
  38. __dmb();
  39. /* Stage 1: Reset Oscillators and select configured values */
  40. RCC_CR = RCC_SYSDIV_50MHZ | RCC_PWMDIV_64 | RCC_XTAL_8MHZ_400MHZ | RCC_USEPWMDIV;
  41. RCC2_CR = (4 - 1) << RCC2_SYSDIV2_SHIFT;
  42. __dmb();
  43. /* Stage 2: Power on oscillators */
  44. rcc &= ~RCC_OFF;
  45. rcc2 &= ~RCC2_OFF;
  46. RCC_CR = rcc;
  47. RCC2_CR = rcc2;
  48. __dmb();
  49. /* Stage 3: Set USESYSDIV */
  50. rcc |= RCC_BYPASS | RCC_USESYSDIV;
  51. RCC_CR = rcc;
  52. __dmb();
  53. /* Stage 4: Wait for PLL raw interrupt */
  54. while ((RCC_RIS & RIS_PLLLRIS) == 0)
  55. ;
  56. /* Stage 5: Disable bypass */
  57. rcc &= ~RCC_BYPASS;
  58. rcc2 &= ~RCC2_BYPASS;
  59. RCC_CR = rcc;
  60. RCC2_CR = rcc2;
  61. __dmb();
  62. return 0;
  63. }