551 lines
13 KiB
C
551 lines
13 KiB
C
/** @defgroup rcc_file RCC peripheral API
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*
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* @ingroup peripheral_apis
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*
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* @brief <b>libopencm3 STM32G0xx Reset and Clock Control</b>
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*
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* @author @htmlonly © @endhtmlonly 2019 Guillaume Revaillot <g.revaillot@gmail.com>
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*
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* @date 10 January 2019
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*
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* This library supports the Reset and Clock Control System in the STM32 series
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* of ARM Cortex Microcontrollers by ST Microelectronics.
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/stm32/rcc.h>
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#include <libopencm3/stm32/pwr.h>
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#include <libopencm3/stm32/flash.h>
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#include <libopencm3/cm3/assert.h>
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/* Set the default clock frequencies after reset. */
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uint32_t rcc_ahb_frequency = 16000000;
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uint32_t rcc_apb1_frequency = 16000000;
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const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = {
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[RCC_CLOCK_CONFIG_LSI_32KHZ] = {
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/* 32khz from lsi, scale2, 0ws */
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.sysclock_source = RCC_LSI,
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.hpre = RCC_CFGR_HPRE_NODIV,
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.ppre = RCC_CFGR_PPRE_NODIV,
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.flash_waitstates = FLASH_ACR_LATENCY_0WS,
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.voltage_scale = PWR_SCALE2,
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.ahb_frequency = 32000,
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.apb_frequency = 32000,
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},
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[RCC_CLOCK_CONFIG_HSI_4MHZ] = {
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/* 4mhz from hsi/4, scale2, 0ws */
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.sysclock_source = RCC_HSI,
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.hsisys_div = RCC_CR_HSIDIV_DIV4,
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.hpre = RCC_CFGR_HPRE_NODIV,
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.ppre = RCC_CFGR_PPRE_NODIV,
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.flash_waitstates = FLASH_ACR_LATENCY_0WS,
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.voltage_scale = PWR_SCALE2,
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.ahb_frequency = 4000000,
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.apb_frequency = 4000000,
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},
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[RCC_CLOCK_CONFIG_HSI_16MHZ] = {
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/* 16mhz from hsi, scale2, 0ws */
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.sysclock_source = RCC_HSI,
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.hsisys_div = RCC_CR_HSIDIV_DIV1,
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.hpre = RCC_CFGR_HPRE_NODIV,
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.ppre = RCC_CFGR_PPRE_NODIV,
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.flash_waitstates = FLASH_ACR_LATENCY_0WS,
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.voltage_scale = PWR_SCALE2,
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.ahb_frequency = 16000000,
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.apb_frequency = 16000000,
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},
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[RCC_CLOCK_CONFIG_HSI_PLL_32MHZ] = {
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/* 32mhz from hsi via pll @ 128mhz / 4, scale1, 1ws */
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.sysclock_source = RCC_PLL,
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.pll_source = RCC_PLLCFGR_PLLSRC_HSI16,
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.pll_div = RCC_PLLCFGR_PLLM_DIV(1),
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.pll_mul = RCC_PLLCFGR_PLLN_MUL(8),
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.pllp_div = RCC_PLLCFGR_PLLP_DIV(4),
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.pllq_div = RCC_PLLCFGR_PLLQ_DIV(4),
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.pllr_div = RCC_PLLCFGR_PLLR_DIV(4),
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.hpre = RCC_CFGR_HPRE_NODIV,
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.ppre = RCC_CFGR_PPRE_NODIV,
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.flash_waitstates = FLASH_ACR_LATENCY_1WS,
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.voltage_scale = PWR_SCALE1,
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.ahb_frequency = 32000000,
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.apb_frequency = 32000000,
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},
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[RCC_CLOCK_CONFIG_HSI_PLL_64MHZ] = {
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/* 64mhz from hsi via pll @ 128mhz / 2, scale1, 2ws */
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.sysclock_source = RCC_PLL,
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.pll_source = RCC_PLLCFGR_PLLSRC_HSI16,
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.pll_div = RCC_PLLCFGR_PLLM_DIV(1),
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.pll_mul = RCC_PLLCFGR_PLLN_MUL(8),
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.pllp_div = RCC_PLLCFGR_PLLP_DIV(2),
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.pllq_div = RCC_PLLCFGR_PLLQ_DIV(2),
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.pllr_div = RCC_PLLCFGR_PLLR_DIV(2),
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.hpre = RCC_CFGR_HPRE_NODIV,
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.ppre = RCC_CFGR_PPRE_NODIV,
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.flash_waitstates = FLASH_ACR_LATENCY_2WS,
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.voltage_scale = PWR_SCALE1,
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.ahb_frequency = 64000000,
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.apb_frequency = 64000000,
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},
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[RCC_CLOCK_CONFIG_HSE_12MHZ_PLL_64MHZ] = {
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/* 64mhz from hse@12mhz via pll @ 128mhz / 2, scale1, 2ws */
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.sysclock_source = RCC_PLL,
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.pll_source = RCC_PLLCFGR_PLLSRC_HSE,
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.pll_div = RCC_PLLCFGR_PLLM_DIV(3),
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.pll_mul = RCC_PLLCFGR_PLLN_MUL(32),
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.pllp_div = RCC_PLLCFGR_PLLP_DIV(2),
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.pllq_div = RCC_PLLCFGR_PLLQ_DIV(2),
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.pllr_div = RCC_PLLCFGR_PLLR_DIV(2),
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.hpre = RCC_CFGR_HPRE_NODIV,
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.ppre = RCC_CFGR_PPRE_NODIV,
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.flash_waitstates = FLASH_ACR_LATENCY_2WS,
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.voltage_scale = PWR_SCALE1,
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.ahb_frequency = 64000000,
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.apb_frequency = 64000000,
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},
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};
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void rcc_osc_on(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CR |= RCC_CR_PLLON;
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break;
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case RCC_HSE:
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RCC_CR |= RCC_CR_HSEON;
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break;
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case RCC_HSI:
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RCC_CR |= RCC_CR_HSION;
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break;
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case RCC_LSE:
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RCC_BDCR |= RCC_BDCR_LSEON;
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break;
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case RCC_LSI:
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RCC_CSR |= RCC_CSR_LSION;
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break;
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default:
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cm3_assert_not_reached();
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break;
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}
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}
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void rcc_osc_off(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CR &= ~RCC_CR_PLLON;
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break;
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case RCC_HSE:
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RCC_CR &= ~RCC_CR_HSEON;
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break;
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case RCC_HSI:
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RCC_CR &= ~RCC_CR_HSION;
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break;
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case RCC_LSE:
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RCC_BDCR &= ~RCC_BDCR_LSEON;
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break;
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case RCC_LSI:
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RCC_CSR &= ~RCC_CSR_LSION;
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break;
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default:
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cm3_assert_not_reached();
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break;
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}
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}
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bool rcc_is_osc_ready(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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return RCC_CR & RCC_CR_PLLRDY;
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case RCC_HSE:
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return RCC_CR & RCC_CR_HSERDY;
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case RCC_HSI:
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return RCC_CR & RCC_CR_HSIRDY;
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case RCC_LSE:
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return RCC_BDCR & RCC_BDCR_LSERDY;
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case RCC_LSI:
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return RCC_CSR & RCC_CSR_LSIRDY;
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default:
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cm3_assert_not_reached();
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return 0;
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}
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return false;
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}
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void rcc_wait_for_osc_ready(enum rcc_osc osc)
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{
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while (!rcc_is_osc_ready(osc));
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}
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void rcc_css_enable(void)
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{
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RCC_CR |= RCC_CR_CSSON;
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}
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void rcc_css_disable(void)
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{
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RCC_CR &= ~RCC_CR_CSSON;
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}
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void rcc_css_int_clear(void)
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{
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RCC_CICR |= RCC_CICR_CSSC;
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}
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int rcc_css_int_flag(void)
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{
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return ((RCC_CIFR & RCC_CIFR_CSSF) != 0);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Set the Source for the System Clock.
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* @param osc Oscillator to use.
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*/
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void rcc_set_sysclk_source(enum rcc_osc osc)
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{
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uint32_t reg32;
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uint32_t sw = 0;
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switch (osc) {
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case RCC_HSI:
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sw = RCC_CFGR_SW_HSISYS;
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break;
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case RCC_HSE:
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sw = RCC_CFGR_SW_HSE;
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break;
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case RCC_PLL:
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sw = RCC_CFGR_SW_PLLRCLK;
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break;
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case RCC_LSE:
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sw = RCC_CFGR_SW_LSE;
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break;
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case RCC_LSI:
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sw = RCC_CFGR_SW_LSI;
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break;
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default:
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cm3_assert_not_reached();
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return;
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}
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_SW_MASK << RCC_CFGR_SW_SHIFT);
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RCC_CFGR = (reg32 | (sw << RCC_CFGR_SW_SHIFT));
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Return the clock source which is used as system clock.
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* @return rcc_osc system clock source
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*/
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enum rcc_osc rcc_system_clock_source(void)
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{
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switch ((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) {
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case RCC_CFGR_SW_HSISYS:
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return RCC_HSI;
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case RCC_CFGR_SW_HSE:
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return RCC_HSE;
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case RCC_CFGR_SWS_PLLRCLK:
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return RCC_PLL;
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case RCC_CFGR_SW_LSE:
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return RCC_LSE;
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case RCC_CFGR_SW_LSI:
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return RCC_LSI;
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default:
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cm3_assert_not_reached();
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return 0;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Wait until system clock switched to given oscillator.
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* @param osc Oscillator.
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*/
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void rcc_wait_for_sysclk_status(enum rcc_osc osc)
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{
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uint32_t sws = 0;
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switch (osc) {
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case RCC_PLL:
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sws = RCC_CFGR_SWS_PLLRCLK;
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break;
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case RCC_HSE:
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sws = RCC_CFGR_SWS_HSE;
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break;
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case RCC_HSI:
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sws = RCC_CFGR_SWS_HSISYS;
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break;
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case RCC_LSI:
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sws = RCC_CFGR_SWS_LSI;
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break;
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case RCC_LSE:
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sws = RCC_CFGR_SWS_LSE;
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break;
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default:
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cm3_assert_not_reached();
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break;
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}
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while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) != sws);
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}
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/**
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* @brief Configure pll source.
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* @param[in] pllsrc pll clock source @ref rcc_pllcfgr_pllsrc
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*/
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void rcc_set_pll_source(uint32_t pllsrc)
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{
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uint32_t reg32;
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reg32 = RCC_PLLCFGR;
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reg32 &= ~(RCC_PLLCFGR_PLLSRC_MASK << RCC_PLLCFGR_PLLSRC_SHIFT);
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RCC_PLLCFGR = (reg32 | (pllsrc << RCC_PLLCFGR_PLLSRC_SHIFT));
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}
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/**
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* @brief Configure pll source and output frequencies.
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* @param[in] source pll clock source @ref rcc_pllcfgr_pllsrc
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* @param[in] pllm pll vco division factor @ref rcc_pllcfgr_pllm
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* @param[in] plln pll vco multiplation factor @ref rcc_pllcfgr_plln
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* @param[in] pllp pll P clock output division factor @ref rcc_pllcfgr_pllp
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* @param[in] pllq pll Q clock output division factor @ref rcc_pllcfgr_pllq
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* @param[in] pllr pll R clock output (sysclock pll) division factor @ref rcc_pllcfgr_pllr
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*/
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void rcc_set_main_pll(uint32_t source, uint32_t pllm, uint32_t plln, uint32_t pllp,
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uint32_t pllq, uint32_t pllr)
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{
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RCC_PLLCFGR = (source << RCC_PLLCFGR_PLLSRC_SHIFT) |
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(pllm << RCC_PLLCFGR_PLLM_SHIFT) |
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(plln << RCC_PLLCFGR_PLLN_SHIFT) |
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(pllp << RCC_PLLCFGR_PLLP_SHIFT) |
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(pllq << RCC_PLLCFGR_PLLQ_SHIFT) |
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(pllr << RCC_PLLCFGR_PLLR_SHIFT);
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}
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/**
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* @brief Enable PLL P clock output.
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* @param[in] enable or disable P clock output
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*/
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void rcc_enable_pllp(bool enable)
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{
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if (enable) {
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RCC_PLLCFGR |= RCC_PLLCFGR_PLLPEN;
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} else {
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RCC_PLLCFGR &= ~RCC_PLLCFGR_PLLPEN;
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}
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}
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/**
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* @brief Enable PLL Q clock output.
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* @param[in] enable or disable Q clock output
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*/
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void rcc_enable_pllq(bool enable)
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{
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if (enable) {
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RCC_PLLCFGR |= RCC_PLLCFGR_PLLQEN;
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} else {
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RCC_PLLCFGR &= ~RCC_PLLCFGR_PLLQEN;
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}
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}
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/**
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* @brief Enable PLL R clock output.
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* @param[in] enable or disable R clock output
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*/
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void rcc_enable_pllr(bool enable)
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{
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if (enable) {
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RCC_PLLCFGR |= RCC_PLLCFGR_PLLREN;
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} else {
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RCC_PLLCFGR &= ~RCC_PLLCFGR_PLLREN;
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}
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}
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/**
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* @brief Configure APB peripheral clock prescaler
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* @param[in] ppre APB clock prescaler value @ref rcc_cfgr_ppre
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*/
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void rcc_set_ppre(uint32_t ppre)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_PPRE_MASK << RCC_CFGR_PPRE_SHIFT);
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RCC_CFGR = (reg32 | (ppre << RCC_CFGR_PPRE_SHIFT));
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}
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/**
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* @brief Configure AHB peripheral clock prescaler
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* @param[in] hpre AHB clock prescaler value @ref rcc_cfgr_hpre
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*/
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void rcc_set_hpre(uint32_t hpre)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_SHIFT);
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RCC_CFGR = (reg32 | (hpre << RCC_CFGR_HPRE_SHIFT));
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}
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/**
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* @brief Configure HSI16 clock division factor to feed SYSCLK
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* @param[in] hsidiv HSYSSIS clock division factor @ref rcc_cr_hsidiv
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*/
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void rcc_set_hsisys_div(uint32_t hsidiv)
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{
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uint32_t reg32;
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reg32 = RCC_CR;
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reg32 &= ~(RCC_CR_HSIDIV_MASK << RCC_CR_HSIDIV_SHIFT);
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RCC_CR = (reg32 | (hsidiv << RCC_CR_HSIDIV_SHIFT));
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}
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/**
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* @brief Configure mco prescaler.
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* @param[in] mcopre prescaler value @ref rcc_cfgr_mcopre
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*/
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void rcc_set_mcopre(uint32_t mcopre)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_MCOPRE_MASK << RCC_CFGR_MCOPRE_SHIFT);
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RCC_CFGR = (reg32 | (mcopre << RCC_CFGR_MCOPRE_SHIFT));
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}
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/**
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* @brief Setup sysclock with desired source (HSE/HSI/PLL/LSE/LSI). taking care of flash/pwr and src configuration
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* @param clock rcc_clock_scale with desired parameters
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*/
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void rcc_clock_setup(const struct rcc_clock_scale *clock)
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{
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if (clock->sysclock_source == RCC_PLL) {
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enum rcc_osc pll_source;
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if (clock->pll_source == RCC_PLLCFGR_PLLSRC_HSE)
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pll_source = RCC_HSE;
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else
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pll_source = RCC_HSI;
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/* start pll src osc. */
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rcc_osc_on(pll_source);
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rcc_wait_for_osc_ready(pll_source);
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/* stop pll to reconfigure it. */
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rcc_osc_off(RCC_PLL);
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while (rcc_is_osc_ready(RCC_PLL));
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rcc_set_main_pll(clock->pll_source, clock->pll_div, clock->pll_mul, clock->pllp_div, clock->pllq_div, clock->pllr_div);
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rcc_enable_pllr(true);
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} else if (clock->sysclock_source == RCC_HSI) {
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rcc_set_hsisys_div(clock->hsisys_div);
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}
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rcc_periph_clock_enable(RCC_PWR);
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pwr_set_vos_scale(clock->voltage_scale);
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flash_set_ws(clock->flash_waitstates);
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/* enable flash prefetch if we have at least 1WS */
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if (clock->flash_waitstates > FLASH_ACR_LATENCY_0WS)
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flash_prefetch_enable();
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else
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flash_prefetch_disable();
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rcc_set_hpre(clock->hpre);
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rcc_set_ppre(clock->ppre);
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rcc_osc_on(clock->sysclock_source);
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rcc_wait_for_osc_ready(clock->sysclock_source);
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rcc_set_sysclk_source(clock->sysclock_source);
|
|
rcc_wait_for_sysclk_status(clock->sysclock_source);
|
|
|
|
rcc_ahb_frequency = clock->ahb_frequency;
|
|
rcc_apb1_frequency = clock->apb_frequency;
|
|
}
|
|
|
|
/**
|
|
* @brief Setup RNG Peripheral Clock Divider
|
|
* @param rng_div clock divider @ref rcc_ccipr_rngdiv
|
|
*/
|
|
void rcc_set_rng_clk_div(uint32_t rng_div)
|
|
{
|
|
uint32_t reg32 = RCC_CCIPR & ~(RCC_CCIPR_RNGDIV_MASK << RCC_CCIPR_RNGDIV_SHIFT);
|
|
RCC_CCIPR = reg32 | (rng_div << RCC_CCIPR_RNGDIV_SHIFT);
|
|
}
|
|
|
|
/**
|
|
* @brief Set the peripheral clock source
|
|
* @param periph peripheral of choice, eg XXX_BASE
|
|
* @param sel periphral clock source
|
|
*/
|
|
void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t sel)
|
|
{
|
|
uint8_t shift;
|
|
uint32_t mask;
|
|
|
|
switch (periph) {
|
|
case ADC1_BASE:
|
|
shift = RCC_CCIPR_ADCSEL_SHIFT;
|
|
mask = RCC_CCIPR_ADCSEL_MASK;
|
|
break;
|
|
case RNG_BASE:
|
|
shift = RCC_CCIPR_RNGSEL_SHIFT;
|
|
mask = RCC_CCIPR_RNGSEL_MASK;
|
|
break;
|
|
case TIM1_BASE:
|
|
shift = RCC_CCIPR_TIM1SEL_SHIFT;
|
|
mask = RCC_CCIPR_TIM1SEL_MASK;
|
|
break;
|
|
case LPTIM1_BASE:
|
|
shift = RCC_CCIPR_LPTIM1SEL_SHIFT;
|
|
mask = RCC_CCIPR_LPTIM1SEL_MASK;
|
|
break;
|
|
case LPTIM2_BASE:
|
|
shift = RCC_CCIPR_LPTIM2SEL_SHIFT;
|
|
mask = RCC_CCIPR_LPTIM2SEL_MASK;
|
|
break;
|
|
case CEC_BASE:
|
|
shift = RCC_CCIPR_CECSEL_SHIFT;
|
|
mask = RCC_CCIPR_CECSEL_MASK;
|
|
break;
|
|
case USART2_BASE:
|
|
shift = RCC_CCIPR_USART2SEL_SHIFT;
|
|
mask = RCC_CCIPR_USART2SEL_MASK;
|
|
break;
|
|
case USART1_BASE:
|
|
shift = RCC_CCIPR_USART1SEL_SHIFT;
|
|
mask = RCC_CCIPR_USART1SEL_MASK;
|
|
break;
|
|
default:
|
|
cm3_assert_not_reached();
|
|
return;
|
|
}
|
|
|
|
uint32_t reg32 = RCC_CCIPR & ~(mask << shift);
|
|
RCC_CCIPR = reg32 | (sel << shift);
|
|
}
|
|
|
|
/**@}*/
|