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m4_init/3rd/libopencm3/scripts/data/lpc43xx/cgu.yaml

938 lignes
22 KiB
Brut Lien permanent Annotations Historique 

  1. !!omap

  2. - CGU_FREQ_MON:

  3.     fields: !!omap

  4.     - RCNT:

  5.         access: rw

  6.         description: 9-bit reference clock-counter value

  7.         lsb: 0

  8.         reset_value: '0'

  9.         width: 9

  10.     - FCNT:

  11.         access: r

  12.         description: 14-bit selected clock-counter value

  13.         lsb: 9

  14.         reset_value: '0'

  15.         width: 14

  16.     - MEAS:

  17.         access: rw

  18.         description: Measure frequency

  19.         lsb: 23

  20.         reset_value: '0'

  21.         width: 1

  22.     - CLK_SEL:

  23.         access: rw

  24.         description: Clock-source selection for the clock to be measured

  25.         lsb: 24

  26.         reset_value: '0'

  27.         width: 5

  28. - CGU_XTAL_OSC_CTRL:

  29.     fields: !!omap

  30.     - ENABLE:

  31.         access: rw

  32.         description: Oscillator-pad enable

  33.         lsb: 0

  34.         reset_value: '1'

  35.         width: 1

  36.     - BYPASS:

  37.         access: rw

  38.         description: Configure crystal operation or external-clock input pin XTAL1

  39.         lsb: 1

  40.         reset_value: '0'

  41.         width: 1

  42.     - HF:

  43.         access: rw

  44.         description: Select frequency range

  45.         lsb: 2

  46.         reset_value: '1'

  47.         width: 1

  48. - CGU_PLL0USB_STAT:

  49.     fields: !!omap

  50.     - LOCK:

  51.         access: r

  52.         description: PLL0 lock indicator

  53.         lsb: 0

  54.         reset_value: '0'

  55.         width: 1

  56.     - FR:

  57.         access: r

  58.         description: PLL0 free running indicator

  59.         lsb: 1

  60.         reset_value: '0'

  61.         width: 1

  62. - CGU_PLL0USB_CTRL:

  63.     fields: !!omap

  64.     - PD:

  65.         access: rw

  66.         description: PLL0 power down

  67.         lsb: 0

  68.         reset_value: '1'

  69.         width: 1

  70.     - BYPASS:

  71.         access: rw

  72.         description: Input clock bypass control

  73.         lsb: 1

  74.         reset_value: '1'

  75.         width: 1

  76.     - DIRECTI:

  77.         access: rw

  78.         description: PLL0 direct input

  79.         lsb: 2

  80.         reset_value: '0'

  81.         width: 1

  82.     - DIRECTO:

  83.         access: rw

  84.         description: PLL0 direct output

  85.         lsb: 3

  86.         reset_value: '0'

  87.         width: 1

  88.     - CLKEN:

  89.         access: rw

  90.         description: PLL0 clock enable

  91.         lsb: 4

  92.         reset_value: '0'

  93.         width: 1

  94.     - FRM:

  95.         access: rw

  96.         description: Free running mode

  97.         lsb: 6

  98.         reset_value: '0'

  99.         width: 1

  100.     - AUTOBLOCK:

  101.         access: rw

  102.         description: Block clock automatically during frequency change

  103.         lsb: 11

  104.         reset_value: '0'

  105.         width: 1

  106.     - CLK_SEL:

  107.         access: rw

  108.         description: Clock source selection

  109.         lsb: 24

  110.         reset_value: '0x01'

  111.         width: 5

  112. - CGU_PLL0USB_MDIV:

  113.     fields: !!omap

  114.     - MDEC:

  115.         access: rw

  116.         description: Decoded M-divider coefficient value

  117.         lsb: 0

  118.         reset_value: '0x5B6A'

  119.         width: 17

  120.     - SELP:

  121.         access: rw

  122.         description: Bandwidth select P value

  123.         lsb: 17

  124.         reset_value: '0x1C'

  125.         width: 5

  126.     - SELI:

  127.         access: rw

  128.         description: Bandwidth select I value

  129.         lsb: 22

  130.         reset_value: '0x17'

  131.         width: 6

  132.     - SELR:

  133.         access: rw

  134.         description: Bandwidth select R value

  135.         lsb: 28

  136.         reset_value: '0x0'

  137.         width: 4

  138. - CGU_PLL0USB_NP_DIV:

  139.     fields: !!omap

  140.     - PDEC:

  141.         access: rw

  142.         description: Decoded P-divider coefficient value

  143.         lsb: 0

  144.         reset_value: '0x02'

  145.         width: 7

  146.     - NDEC:

  147.         access: rw

  148.         description: Decoded N-divider coefficient value

  149.         lsb: 12

  150.         reset_value: '0xB1'

  151.         width: 10

  152. - CGU_PLL0AUDIO_STAT:

  153.     fields: !!omap

  154.     - LOCK:

  155.         access: r

  156.         description: PLL0 lock indicator

  157.         lsb: 0

  158.         reset_value: '0'

  159.         width: 1

  160.     - FR:

  161.         access: r

  162.         description: PLL0 free running indicator

  163.         lsb: 1

  164.         reset_value: '0'

  165.         width: 1

  166. - CGU_PLL0AUDIO_CTRL:

  167.     fields: !!omap

  168.     - PD:

  169.         access: rw

  170.         description: PLL0 power down

  171.         lsb: 0

  172.         reset_value: '1'

  173.         width: 1

  174.     - BYPASS:

  175.         access: rw

  176.         description: Input clock bypass control

  177.         lsb: 1

  178.         reset_value: '1'

  179.         width: 1

  180.     - DIRECTI:

  181.         access: rw

  182.         description: PLL0 direct input

  183.         lsb: 2

  184.         reset_value: '0'

  185.         width: 1

  186.     - DIRECTO:

  187.         access: rw

  188.         description: PLL0 direct output

  189.         lsb: 3

  190.         reset_value: '0'

  191.         width: 1

  192.     - CLKEN:

  193.         access: rw

  194.         description: PLL0 clock enable

  195.         lsb: 4

  196.         reset_value: '0'

  197.         width: 1

  198.     - FRM:

  199.         access: rw

  200.         description: Free running mode

  201.         lsb: 6

  202.         reset_value: '0'

  203.         width: 1

  204.     - AUTOBLOCK:

  205.         access: rw

  206.         description: Block clock automatically during frequency change

  207.         lsb: 11

  208.         reset_value: '0'

  209.         width: 1

  210.     - PLLFRACT_REQ:

  211.         access: rw

  212.         description: Fractional PLL word write request

  213.         lsb: 12

  214.         reset_value: '0'

  215.         width: 1

  216.     - SEL_EXT:

  217.         access: rw

  218.         description: Select fractional divider

  219.         lsb: 13

  220.         reset_value: '0'

  221.         width: 1

  222.     - MOD_PD:

  223.         access: rw

  224.         description: Sigma-Delta modulator power-down

  225.         lsb: 14

  226.         reset_value: '1'

  227.         width: 1

  228.     - CLK_SEL:

  229.         access: rw

  230.         description: Clock source selection

  231.         lsb: 24

  232.         reset_value: '0x01'

  233.         width: 5

  234. - CGU_PLL0AUDIO_MDIV:

  235.     fields: !!omap

  236.     - MDEC:

  237.         access: rw

  238.         description: Decoded M-divider coefficient value

  239.         lsb: 0

  240.         reset_value: '0x5B6A'

  241.         width: 17

  242. - CGU_PLL0AUDIO_NP_DIV:

  243.     fields: !!omap

  244.     - PDEC:

  245.         access: rw

  246.         description: Decoded P-divider coefficient value

  247.         lsb: 0

  248.         reset_value: '0x02'

  249.         width: 7

  250.     - NDEC:

  251.         access: rw

  252.         description: Decoded N-divider coefficient value

  253.         lsb: 12

  254.         reset_value: '0xB1'

  255.         width: 10

  256. - CGU_PLLAUDIO_FRAC:

  257.     fields: !!omap

  258.     - PLLFRACT_CTRL:

  259.         access: rw

  260.         description: PLL fractional divider control word

  261.         lsb: 0

  262.         reset_value: '0x00'

  263.         width: 22

  264. - CGU_PLL1_STAT:

  265.     fields: !!omap

  266.     - LOCK:

  267.         access: r

  268.         description: PLL1 lock indicator

  269.         lsb: 0

  270.         reset_value: '0'

  271.         width: 1

  272. - CGU_PLL1_CTRL:

  273.     fields: !!omap

  274.     - PD:

  275.         access: rw

  276.         description: PLL1 power down

  277.         lsb: 0

  278.         reset_value: '1'

  279.         width: 1

  280.     - BYPASS:

  281.         access: rw

  282.         description: Input clock bypass control

  283.         lsb: 1

  284.         reset_value: '1'

  285.         width: 1

  286.     - FBSEL:

  287.         access: rw

  288.         description: PLL feedback select

  289.         lsb: 6

  290.         reset_value: '0'

  291.         width: 1

  292.     - DIRECT:

  293.         access: rw

  294.         description: PLL direct CCO output

  295.         lsb: 7

  296.         reset_value: '0'

  297.         width: 1

  298.     - PSEL:

  299.         access: rw

  300.         description: Post-divider division ratio P

  301.         lsb: 8

  302.         reset_value: '0x1'

  303.         width: 2

  304.     - AUTOBLOCK:

  305.         access: rw

  306.         description: Block clock automatically during frequency change

  307.         lsb: 11

  308.         reset_value: '0'

  309.         width: 1

  310.     - NSEL:

  311.         access: rw

  312.         description: Pre-divider division ratio N

  313.         lsb: 12

  314.         reset_value: '0x2'

  315.         width: 2

  316.     - MSEL:

  317.         access: rw

  318.         description: Feedback-divider division ratio (M)

  319.         lsb: 16

  320.         reset_value: '0x18'

  321.         width: 8

  322.     - CLK_SEL:

  323.         access: rw

  324.         description: Clock-source selection

  325.         lsb: 24

  326.         reset_value: '0x01'

  327.         width: 5

  328. - CGU_IDIVA_CTRL:

  329.     fields: !!omap

  330.     - PD:

  331.         access: rw

  332.         description: Integer divider power down

  333.         lsb: 0

  334.         reset_value: '0'

  335.         width: 1

  336.     - IDIV:

  337.         access: rw

  338.         description: Integer divider A divider value (1/(IDIV + 1))

  339.         lsb: 2

  340.         reset_value: '0x0'

  341.         width: 2

  342.     - AUTOBLOCK:

  343.         access: rw

  344.         description: Block clock automatically during frequency change

  345.         lsb: 11

  346.         reset_value: '0'

  347.         width: 1

  348.     - CLK_SEL:

  349.         access: rw

  350.         description: Clock source selection

  351.         lsb: 24

  352.         reset_value: '0x01'

  353.         width: 5

  354. - CGU_IDIVB_CTRL:

  355.     fields: !!omap

  356.     - PD:

  357.         access: rw

  358.         description: Integer divider power down

  359.         lsb: 0

  360.         reset_value: '0'

  361.         width: 1

  362.     - IDIV:

  363.         access: rw

  364.         description: Integer divider B divider value (1/(IDIV + 1))

  365.         lsb: 2

  366.         reset_value: '0x0'

  367.         width: 4

  368.     - AUTOBLOCK:

  369.         access: rw

  370.         description: Block clock automatically during frequency change

  371.         lsb: 11

  372.         reset_value: '0'

  373.         width: 1

  374.     - CLK_SEL:

  375.         access: rw

  376.         description: Clock source selection

  377.         lsb: 24

  378.         reset_value: '0x01'

  379.         width: 5

  380. - CGU_IDIVC_CTRL:

  381.     fields: !!omap

  382.     - PD:

  383.         access: rw

  384.         description: Integer divider power down

  385.         lsb: 0

  386.         reset_value: '0'

  387.         width: 1

  388.     - IDIV:

  389.         access: rw

  390.         description: Integer divider C divider value (1/(IDIV + 1))

  391.         lsb: 2

  392.         reset_value: '0x0'

  393.         width: 4

  394.     - AUTOBLOCK:

  395.         access: rw

  396.         description: Block clock automatically during frequency change

  397.         lsb: 11

  398.         reset_value: '0'

  399.         width: 1

  400.     - CLK_SEL:

  401.         access: rw

  402.         description: Clock source selection

  403.         lsb: 24

  404.         reset_value: '0x01'

  405.         width: 5

  406. - CGU_IDIVD_CTRL:

  407.     fields: !!omap

  408.     - PD:

  409.         access: rw

  410.         description: Integer divider power down

  411.         lsb: 0

  412.         reset_value: '0'

  413.         width: 1

  414.     - IDIV:

  415.         access: rw

  416.         description: Integer divider D divider value (1/(IDIV + 1))

  417.         lsb: 2

  418.         reset_value: '0x0'

  419.         width: 4

  420.     - AUTOBLOCK:

  421.         access: rw

  422.         description: Block clock automatically during frequency change

  423.         lsb: 11

  424.         reset_value: '0'

  425.         width: 1

  426.     - CLK_SEL:

  427.         access: rw

  428.         description: Clock source selection

  429.         lsb: 24

  430.         reset_value: '0x01'

  431.         width: 5

  432. - CGU_IDIVE_CTRL:

  433.     fields: !!omap

  434.     - PD:

  435.         access: rw

  436.         description: Integer divider power down

  437.         lsb: 0

  438.         reset_value: '0'

  439.         width: 1

  440.     - IDIV:

  441.         access: rw

  442.         description: Integer divider E divider value (1/(IDIV + 1))

  443.         lsb: 2

  444.         reset_value: '0x00'

  445.         width: 8

  446.     - AUTOBLOCK:

  447.         access: rw

  448.         description: Block clock automatically during frequency change

  449.         lsb: 11

  450.         reset_value: '0'

  451.         width: 1

  452.     - CLK_SEL:

  453.         access: rw

  454.         description: Clock source selection

  455.         lsb: 24

  456.         reset_value: '0x01'

  457.         width: 5

  458. - CGU_BASE_SAFE_CLK:

  459.     fields: !!omap

  460.     - PD:

  461.         access: r

  462.         description: Output stage power down

  463.         lsb: 0

  464.         reset_value: '0'

  465.         width: 1

  466.     - AUTOBLOCK:

  467.         access: r

  468.         description: Block clock automatically during frequency change

  469.         lsb: 11

  470.         reset_value: '0'

  471.         width: 1

  472.     - CLK_SEL:

  473.         access: r

  474.         description: Clock source selection

  475.         lsb: 24

  476.         reset_value: '0x01'

  477.         width: 5

  478. - CGU_BASE_USB0_CLK:

  479.     fields: !!omap

  480.     - PD:

  481.         access: rw

  482.         description: Output stage power down

  483.         lsb: 0

  484.         reset_value: '0'

  485.         width: 1

  486.     - AUTOBLOCK:

  487.         access: rw

  488.         description: Block clock automatically during frequency change

  489.         lsb: 11

  490.         reset_value: '0'

  491.         width: 1

  492.     - CLK_SEL:

  493.         access: rw

  494.         description: Clock source selection

  495.         lsb: 24

  496.         reset_value: '0x07'

  497.         width: 5

  498. - CGU_BASE_PERIPH_CLK:

  499.     fields: !!omap

  500.     - PD:

  501.         access: rw

  502.         description: Output stage power down

  503.         lsb: 0

  504.         reset_value: '0'

  505.         width: 1

  506.     - AUTOBLOCK:

  507.         access: rw

  508.         description: Block clock automatically during frequency change

  509.         lsb: 11

  510.         reset_value: '0'

  511.         width: 1

  512.     - CLK_SEL:

  513.         access: rw

  514.         description: Clock source selection

  515.         lsb: 24

  516.         reset_value: '0x01'

  517.         width: 5

  518. - CGU_BASE_USB1_CLK:

  519.     fields: !!omap

  520.     - PD:

  521.         access: rw

  522.         description: Output stage power down

  523.         lsb: 0

  524.         reset_value: '0'

  525.         width: 1

  526.     - AUTOBLOCK:

  527.         access: rw

  528.         description: Block clock automatically during frequency change

  529.         lsb: 11

  530.         reset_value: '0'

  531.         width: 1

  532.     - CLK_SEL:

  533.         access: rw

  534.         description: Clock source selection

  535.         lsb: 24

  536.         reset_value: '0x01'

  537.         width: 5

  538. - CGU_BASE_M4_CLK:

  539.     fields: !!omap

  540.     - PD:

  541.         access: rw

  542.         description: Output stage power down

  543.         lsb: 0

  544.         reset_value: '0'

  545.         width: 1

  546.     - AUTOBLOCK:

  547.         access: rw

  548.         description: Block clock automatically during frequency change

  549.         lsb: 11

  550.         reset_value: '0'

  551.         width: 1

  552.     - CLK_SEL:

  553.         access: rw

  554.         description: Clock source selection

  555.         lsb: 24

  556.         reset_value: '0x01'

  557.         width: 5

  558. - CGU_BASE_SPIFI_CLK:

  559.     fields: !!omap

  560.     - PD:

  561.         access: rw

  562.         description: Output stage power down

  563.         lsb: 0

  564.         reset_value: '0'

  565.         width: 1

  566.     - AUTOBLOCK:

  567.         access: rw

  568.         description: Block clock automatically during frequency change

  569.         lsb: 11

  570.         reset_value: '0'

  571.         width: 1

  572.     - CLK_SEL:

  573.         access: rw

  574.         description: Clock source selection

  575.         lsb: 24

  576.         reset_value: '0x01'

  577.         width: 5

  578. - CGU_BASE_SPI_CLK:

  579.     fields: !!omap

  580.     - PD:

  581.         access: rw

  582.         description: Output stage power down

  583.         lsb: 0

  584.         reset_value: '0'

  585.         width: 1

  586.     - AUTOBLOCK:

  587.         access: rw

  588.         description: Block clock automatically during frequency change

  589.         lsb: 11

  590.         reset_value: '0'

  591.         width: 1

  592.     - CLK_SEL:

  593.         access: rw

  594.         description: Clock source selection

  595.         lsb: 24

  596.         reset_value: '0x01'

  597.         width: 5

  598. - CGU_BASE_PHY_RX_CLK:

  599.     fields: !!omap

  600.     - PD:

  601.         access: rw

  602.         description: Output stage power down

  603.         lsb: 0

  604.         reset_value: '0'

  605.         width: 1

  606.     - AUTOBLOCK:

  607.         access: rw

  608.         description: Block clock automatically during frequency change

  609.         lsb: 11

  610.         reset_value: '0'

  611.         width: 1

  612.     - CLK_SEL:

  613.         access: rw

  614.         description: Clock source selection

  615.         lsb: 24

  616.         reset_value: '0x01'

  617.         width: 5

  618. - CGU_BASE_PHY_TX_CLK:

  619.     fields: !!omap

  620.     - PD:

  621.         access: rw

  622.         description: Output stage power down

  623.         lsb: 0

  624.         reset_value: '0'

  625.         width: 1

  626.     - AUTOBLOCK:

  627.         access: rw

  628.         description: Block clock automatically during frequency change

  629.         lsb: 11

  630.         reset_value: '0'

  631.         width: 1

  632.     - CLK_SEL:

  633.         access: rw

  634.         description: Clock source selection

  635.         lsb: 24

  636.         reset_value: '0x01'

  637.         width: 5

  638. - CGU_BASE_APB1_CLK:

  639.     fields: !!omap

  640.     - PD:

  641.         access: rw

  642.         description: Output stage power down

  643.         lsb: 0

  644.         reset_value: '0'

  645.         width: 1

  646.     - AUTOBLOCK:

  647.         access: rw

  648.         description: Block clock automatically during frequency change

  649.         lsb: 11

  650.         reset_value: '0'

  651.         width: 1

  652.     - CLK_SEL:

  653.         access: rw

  654.         description: Clock source selection

  655.         lsb: 24

  656.         reset_value: '0x01'

  657.         width: 5

  658. - CGU_BASE_APB3_CLK:

  659.     fields: !!omap

  660.     - PD:

  661.         access: rw

  662.         description: Output stage power down

  663.         lsb: 0

  664.         reset_value: '0'

  665.         width: 1

  666.     - AUTOBLOCK:

  667.         access: rw

  668.         description: Block clock automatically during frequency change

  669.         lsb: 11

  670.         reset_value: '0'

  671.         width: 1

  672.     - CLK_SEL:

  673.         access: rw

  674.         description: Clock source selection

  675.         lsb: 24

  676.         reset_value: '0x01'

  677.         width: 5

  678. - CGU_BASE_LCD_CLK:

  679.     fields: !!omap

  680.     - PD:

  681.         access: rw

  682.         description: Output stage power down

  683.         lsb: 0

  684.         reset_value: '0'

  685.         width: 1

  686.     - AUTOBLOCK:

  687.         access: rw

  688.         description: Block clock automatically during frequency change

  689.         lsb: 11

  690.         reset_value: '0'

  691.         width: 1

  692.     - CLK_SEL:

  693.         access: rw

  694.         description: Clock source selection

  695.         lsb: 24

  696.         reset_value: '0x01'

  697.         width: 5

  698. - CGU_BASE_VADC_CLK:

  699.     fields: !!omap

  700.     - PD:

  701.         access: rw

  702.         description: Output stage power down

  703.         lsb: 0

  704.         reset_value: '0'

  705.         width: 1

  706.     - AUTOBLOCK:

  707.         access: rw

  708.         description: Block clock automatically during frequency change

  709.         lsb: 11

  710.         reset_value: '0'

  711.         width: 1

  712.     - CLK_SEL:

  713.         access: rw

  714.         description: Clock source selection

  715.         lsb: 24

  716.         reset_value: '0x01'

  717.         width: 5

  718. - CGU_BASE_SDIO_CLK:

  719.     fields: !!omap

  720.     - PD:

  721.         access: rw

  722.         description: Output stage power down

  723.         lsb: 0

  724.         reset_value: '0'

  725.         width: 1

  726.     - AUTOBLOCK:

  727.         access: rw

  728.         description: Block clock automatically during frequency change

  729.         lsb: 11

  730.         reset_value: '0'

  731.         width: 1

  732.     - CLK_SEL:

  733.         access: rw

  734.         description: Clock source selection

  735.         lsb: 24

  736.         reset_value: '0x01'

  737.         width: 5

  738. - CGU_BASE_SSP0_CLK:

  739.     fields: !!omap

  740.     - PD:

  741.         access: rw

  742.         description: Output stage power down

  743.         lsb: 0

  744.         reset_value: '0'

  745.         width: 1

  746.     - AUTOBLOCK:

  747.         access: rw

  748.         description: Block clock automatically during frequency change

  749.         lsb: 11

  750.         reset_value: '0'

  751.         width: 1

  752.     - CLK_SEL:

  753.         access: rw

  754.         description: Clock source selection

  755.         lsb: 24

  756.         reset_value: '0x01'

  757.         width: 5

  758. - CGU_BASE_SSP1_CLK:

  759.     fields: !!omap

  760.     - PD:

  761.         access: rw

  762.         description: Output stage power down

  763.         lsb: 0

  764.         reset_value: '0'

  765.         width: 1

  766.     - AUTOBLOCK:

  767.         access: rw

  768.         description: Block clock automatically during frequency change

  769.         lsb: 11

  770.         reset_value: '0'

  771.         width: 1

  772.     - CLK_SEL:

  773.         access: rw

  774.         description: Clock source selection

  775.         lsb: 24

  776.         reset_value: '0x01'

  777.         width: 5

  778. - CGU_BASE_UART0_CLK:

  779.     fields: !!omap

  780.     - PD:

  781.         access: rw

  782.         description: Output stage power down

  783.         lsb: 0

  784.         reset_value: '0'

  785.         width: 1

  786.     - AUTOBLOCK:

  787.         access: rw

  788.         description: Block clock automatically during frequency change

  789.         lsb: 11

  790.         reset_value: '0'

  791.         width: 1

  792.     - CLK_SEL:

  793.         access: rw

  794.         description: Clock source selection

  795.         lsb: 24

  796.         reset_value: '0x01'

  797.         width: 5

  798. - CGU_BASE_UART1_CLK:

  799.     fields: !!omap

  800.     - PD:

  801.         access: rw

  802.         description: Output stage power down

  803.         lsb: 0

  804.         reset_value: '0'

  805.         width: 1

  806.     - AUTOBLOCK:

  807.         access: rw

  808.         description: Block clock automatically during frequency change

  809.         lsb: 11

  810.         reset_value: '0'

  811.         width: 1

  812.     - CLK_SEL:

  813.         access: rw

  814.         description: Clock source selection

  815.         lsb: 24

  816.         reset_value: '0x01'

  817.         width: 5

  818. - CGU_BASE_UART2_CLK:

  819.     fields: !!omap

  820.     - PD:

  821.         access: rw

  822.         description: Output stage power down

  823.         lsb: 0

  824.         reset_value: '0'

  825.         width: 1

  826.     - AUTOBLOCK:

  827.         access: rw

  828.         description: Block clock automatically during frequency change

  829.         lsb: 11

  830.         reset_value: '0'

  831.         width: 1

  832.     - CLK_SEL:

  833.         access: rw

  834.         description: Clock source selection

  835.         lsb: 24

  836.         reset_value: '0x01'

  837.         width: 5

  838. - CGU_BASE_UART3_CLK:

  839.     fields: !!omap

  840.     - PD:

  841.         access: rw

  842.         description: Output stage power down

  843.         lsb: 0

  844.         reset_value: '0'

  845.         width: 1

  846.     - AUTOBLOCK:

  847.         access: rw

  848.         description: Block clock automatically during frequency change

  849.         lsb: 11

  850.         reset_value: '0'

  851.         width: 1

  852.     - CLK_SEL:

  853.         access: rw

  854.         description: Clock source selection

  855.         lsb: 24

  856.         reset_value: '0x01'

  857.         width: 5

  858. - CGU_BASE_OUT_CLK:

  859.     fields: !!omap

  860.     - PD:

  861.         access: rw

  862.         description: Output stage power down

  863.         lsb: 0

  864.         reset_value: '0'

  865.         width: 1

  866.     - AUTOBLOCK:

  867.         access: rw

  868.         description: Block clock automatically during frequency change

  869.         lsb: 11

  870.         reset_value: '0'

  871.         width: 1

  872.     - CLK_SEL:

  873.         access: rw

  874.         description: Clock source selection

  875.         lsb: 24

  876.         reset_value: '0x01'

  877.         width: 5

  878. - CGU_BASE_APLL_CLK:

  879.     fields: !!omap

  880.     - PD:

  881.         access: rw

  882.         description: Output stage power down

  883.         lsb: 0

  884.         reset_value: '0'

  885.         width: 1

  886.     - AUTOBLOCK:

  887.         access: rw

  888.         description: Block clock automatically during frequency change

  889.         lsb: 11

  890.         reset_value: '0'

  891.         width: 1

  892.     - CLK_SEL:

  893.         access: rw

  894.         description: Clock source selection

  895.         lsb: 24

  896.         reset_value: '0x01'

  897.         width: 5

  898. - CGU_BASE_CGU_OUT0_CLK:

  899.     fields: !!omap

  900.     - PD:

  901.         access: rw

  902.         description: Output stage power down

  903.         lsb: 0

  904.         reset_value: '0'

  905.         width: 1

  906.     - AUTOBLOCK:

  907.         access: rw

  908.         description: Block clock automatically during frequency change

  909.         lsb: 11

  910.         reset_value: '0'

  911.         width: 1

  912.     - CLK_SEL:

  913.         access: rw

  914.         description: Clock source selection

  915.         lsb: 24

  916.         reset_value: '0x01'

  917.         width: 5

  918. - CGU_BASE_CGU_OUT1_CLK:

  919.     fields: !!omap

  920.     - PD:

  921.         access: rw

  922.         description: Output stage power down

  923.         lsb: 0

  924.         reset_value: '0'

  925.         width: 1

  926.     - AUTOBLOCK:

  927.         access: rw

  928.         description: Block clock automatically during frequency change

  929.         lsb: 11

  930.         reset_value: '0'

  931.         width: 1

  932.     - CLK_SEL:

  933.         access: rw

  934.         description: Clock source selection

  935.         lsb: 24

  936.         reset_value: '0x01'

  937.         width: 5