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m4_init/3rd/libopencm3/scripts/data/lpc43xx/eventrouter.yaml

960 line
26 KiB
原始文件 永久連結 Blame 歷史記錄 

  1. !!omap

  2. - EVENTROUTER_HILO:

  3.     fields: !!omap

  4.     - WAKEUP0_L:

  5.         access: rw

  6.         description: Level detect mode for WAKEUP0 event

  7.         lsb: 0

  8.         reset_value: '0'

  9.         width: 1

  10.     - WAKEUP1_L:

  11.         access: rw

  12.         description: Level detect mode for WAKEUP1 event

  13.         lsb: 1

  14.         reset_value: '0'

  15.         width: 1

  16.     - WAKEUP2_L:

  17.         access: rw

  18.         description: Level detect mode for WAKEUP2 event

  19.         lsb: 2

  20.         reset_value: '0'

  21.         width: 1

  22.     - WAKEUP3_L:

  23.         access: rw

  24.         description: Level detect mode for WAKEUP3 event

  25.         lsb: 3

  26.         reset_value: '0'

  27.         width: 1

  28.     - ATIMER_L:

  29.         access: rw

  30.         description: Level detect mode for alarm timer event

  31.         lsb: 4

  32.         reset_value: '0'

  33.         width: 1

  34.     - RTC_L:

  35.         access: rw

  36.         description: Level detect mode for RTC event

  37.         lsb: 5

  38.         reset_value: '0'

  39.         width: 1

  40.     - BOD_L:

  41.         access: rw

  42.         description: Level detect mode for BOD event

  43.         lsb: 6

  44.         reset_value: '0'

  45.         width: 1

  46.     - WWDT_L:

  47.         access: rw

  48.         description: Level detect mode for WWDT event

  49.         lsb: 7

  50.         reset_value: '0'

  51.         width: 1

  52.     - ETH_L:

  53.         access: rw

  54.         description: Level detect mode for Ethernet event

  55.         lsb: 8

  56.         reset_value: '0'

  57.         width: 1

  58.     - USB0_L:

  59.         access: rw

  60.         description: Level detect mode for USB0 event

  61.         lsb: 9

  62.         reset_value: '0'

  63.         width: 1

  64.     - USB1_L:

  65.         access: rw

  66.         description: Level detect mode for USB1 event

  67.         lsb: 10

  68.         reset_value: '0'

  69.         width: 1

  70.     - SDMMC_L:

  71.         access: rw

  72.         description: Level detect mode for SD/MMC event

  73.         lsb: 11

  74.         reset_value: '0'

  75.         width: 1

  76.     - CAN_L:

  77.         access: rw

  78.         description: Level detect mode for C_CAN event

  79.         lsb: 12

  80.         reset_value: '0'

  81.         width: 1

  82.     - TIM2_L:

  83.         access: rw

  84.         description: Level detect mode for combined timer output 2 event

  85.         lsb: 13

  86.         reset_value: '0'

  87.         width: 1

  88.     - TIM6_L:

  89.         access: rw

  90.         description: Level detect mode for combined timer output 6 event

  91.         lsb: 14

  92.         reset_value: '0'

  93.         width: 1

  94.     - QEI_L:

  95.         access: rw

  96.         description: Level detect mode for QEI event

  97.         lsb: 15

  98.         reset_value: '0'

  99.         width: 1

  100.     - TIM14_L:

  101.         access: rw

  102.         description: Level detect mode for combined timer output 14 event

  103.         lsb: 16

  104.         reset_value: '0'

  105.         width: 1

  106.     - RESET_L:

  107.         access: rw

  108.         description: Level detect mode for Reset

  109.         lsb: 19

  110.         reset_value: '0'

  111.         width: 1

  112. - EVENTROUTER_EDGE:

  113.     fields: !!omap

  114.     - WAKEUP0_E:

  115.         access: rw

  116.         description: Edge/Level detect mode for WAKEUP0 event

  117.         lsb: 0

  118.         reset_value: '0'

  119.         width: 1

  120.     - WAKEUP1_E:

  121.         access: rw

  122.         description: Edge/Level detect mode for WAKEUP1 event

  123.         lsb: 1

  124.         reset_value: '0'

  125.         width: 1

  126.     - WAKEUP2_E:

  127.         access: rw

  128.         description: Edge/Level detect mode for WAKEUP2 event

  129.         lsb: 2

  130.         reset_value: '0'

  131.         width: 1

  132.     - WAKEUP3_E:

  133.         access: rw

  134.         description: Edge/Level detect mode for WAKEUP3 event

  135.         lsb: 3

  136.         reset_value: '0'

  137.         width: 1

  138.     - ATIMER_E:

  139.         access: rw

  140.         description: Edge/Level detect mode for alarm timer event

  141.         lsb: 4

  142.         reset_value: '0'

  143.         width: 1

  144.     - RTC_E:

  145.         access: rw

  146.         description: Edge/Level detect mode for RTC event

  147.         lsb: 5

  148.         reset_value: '0'

  149.         width: 1

  150.     - BOD_E:

  151.         access: rw

  152.         description: Edge/Level detect mode for BOD event

  153.         lsb: 6

  154.         reset_value: '0'

  155.         width: 1

  156.     - WWDT_E:

  157.         access: rw

  158.         description: Edge/Level detect mode for WWDT event

  159.         lsb: 7

  160.         reset_value: '0'

  161.         width: 1

  162.     - ETH_E:

  163.         access: rw

  164.         description: Edge/Level detect mode for Ethernet event

  165.         lsb: 8

  166.         reset_value: '0'

  167.         width: 1

  168.     - USB0_E:

  169.         access: rw

  170.         description: Edge/Level detect mode for USB0 event

  171.         lsb: 9

  172.         reset_value: '0'

  173.         width: 1

  174.     - USB1_E:

  175.         access: rw

  176.         description: Edge/Level detect mode for USB1 event

  177.         lsb: 10

  178.         reset_value: '0'

  179.         width: 1

  180.     - SDMMC_E:

  181.         access: rw

  182.         description: Edge/Level detect mode for SD/MMC event

  183.         lsb: 11

  184.         reset_value: '0'

  185.         width: 1

  186.     - CAN_E:

  187.         access: rw

  188.         description: Edge/Level detect mode for C_CAN event

  189.         lsb: 12

  190.         reset_value: '0'

  191.         width: 1

  192.     - TIM2_E:

  193.         access: rw

  194.         description: Edge/Level detect mode for combined timer output 2 event

  195.         lsb: 13

  196.         reset_value: '0'

  197.         width: 1

  198.     - TIM6_E:

  199.         access: rw

  200.         description: Edge/Level detect mode for combined timer output 6 event

  201.         lsb: 14

  202.         reset_value: '0'

  203.         width: 1

  204.     - QEI_E:

  205.         access: rw

  206.         description: Edge/Level detect mode for QEI event

  207.         lsb: 15

  208.         reset_value: '0'

  209.         width: 1

  210.     - TIM14_E:

  211.         access: rw

  212.         description: Edge/Level detect mode for combined timer output 14 event

  213.         lsb: 16

  214.         reset_value: '0'

  215.         width: 1

  216.     - RESET_E:

  217.         access: rw

  218.         description: Edge/Level detect mode for Reset

  219.         lsb: 19

  220.         reset_value: '0'

  221.         width: 1

  222. - EVENTROUTER_CLR_EN:

  223.     fields: !!omap

  224.     - WAKEUP0_CLREN:

  225.         access: w

  226.         description: Writing a 1 to this bit clears the event enable bit 0 in the

  227.           ENABLE register

  228.         lsb: 0

  229.         reset_value: '0'

  230.         width: 1

  231.     - WAKEUP1_CLREN:

  232.         access: w

  233.         description: Writing a 1 to this bit clears the event enable bit 1 in the

  234.           ENABLE register

  235.         lsb: 1

  236.         reset_value: '0'

  237.         width: 1

  238.     - WAKEUP2_CLREN:

  239.         access: w

  240.         description: Writing a 1 to this bit clears the event enable bit 2 in the

  241.           ENABLE register

  242.         lsb: 2

  243.         reset_value: '0'

  244.         width: 1

  245.     - WAKEUP3_CLREN:

  246.         access: w

  247.         description: Writing a 1 to this bit clears the event enable bit 3 in the

  248.           ENABLE register

  249.         lsb: 3

  250.         reset_value: '0'

  251.         width: 1

  252.     - ATIMER_CLREN:

  253.         access: w

  254.         description: Writing a 1 to this bit clears the event enable bit 4 in the

  255.           ENABLE register

  256.         lsb: 4

  257.         reset_value: '0'

  258.         width: 1

  259.     - RTC_CLREN:

  260.         access: w

  261.         description: Writing a 1 to this bit clears the event enable bit 5 in the

  262.           ENABLE register

  263.         lsb: 5

  264.         reset_value: '0'

  265.         width: 1

  266.     - BOD_CLREN:

  267.         access: w

  268.         description: Writing a 1 to this bit clears the event enable bit 6 in the

  269.           ENABLE register

  270.         lsb: 6

  271.         reset_value: '0'

  272.         width: 1

  273.     - WWDT_CLREN:

  274.         access: w

  275.         description: Writing a 1 to this bit clears the event enable bit 7 in the

  276.           ENABLE register

  277.         lsb: 7

  278.         reset_value: '0'

  279.         width: 1

  280.     - ETH_CLREN:

  281.         access: w

  282.         description: Writing a 1 to this bit clears the event enable bit 8 in the

  283.           ENABLE register

  284.         lsb: 8

  285.         reset_value: '0'

  286.         width: 1

  287.     - USB0_CLREN:

  288.         access: w

  289.         description: Writing a 1 to this bit clears the event enable bit 9 in the

  290.           ENABLE register

  291.         lsb: 9

  292.         reset_value: '0'

  293.         width: 1

  294.     - USB1_CLREN:

  295.         access: w

  296.         description: Writing a 1 to this bit clears the event enable bit 10 in the

  297.           ENABLE register

  298.         lsb: 10

  299.         reset_value: '0'

  300.         width: 1

  301.     - SDMCC_CLREN:

  302.         access: w

  303.         description: Writing a 1 to this bit clears the event enable bit 11 in the

  304.           ENABLE register

  305.         lsb: 11

  306.         reset_value: '0'

  307.         width: 1

  308.     - CAN_CLREN:

  309.         access: w

  310.         description: Writing a 1 to this bit clears the event enable bit 12 in the

  311.           ENABLE register

  312.         lsb: 12

  313.         reset_value: '0'

  314.         width: 1

  315.     - TIM2_CLREN:

  316.         access: w

  317.         description: Writing a 1 to this bit clears the event enable bit 13 in the

  318.           ENABLE register

  319.         lsb: 13

  320.         reset_value: '0'

  321.         width: 1

  322.     - TIM6_CLREN:

  323.         access: w

  324.         description: Writing a 1 to this bit clears the event enable bit 14 in the

  325.           ENABLE register

  326.         lsb: 14

  327.         reset_value: '0'

  328.         width: 1

  329.     - QEI_CLREN:

  330.         access: w

  331.         description: Writing a 1 to this bit clears the event enable bit 15 in the

  332.           ENABLE register

  333.         lsb: 15

  334.         reset_value: '0'

  335.         width: 1

  336.     - TIM14_CLREN:

  337.         access: w

  338.         description: Writing a 1 to this bit clears the event enable bit 16 in the

  339.           ENABLE register

  340.         lsb: 16

  341.         reset_value: '0'

  342.         width: 1

  343.     - RESET_CLREN:

  344.         access: w

  345.         description: Writing a 1 to this bit clears the event enable bit 19 in the

  346.           ENABLE register

  347.         lsb: 19

  348.         reset_value: '0'

  349.         width: 1

  350. - EVENTROUTER_SET_EN:

  351.     fields: !!omap

  352.     - WAKEUP0_SETEN:

  353.         access: w

  354.         description: Writing a 1 to this bit sets the event enable bit 0 in the ENABLE

  355.           register

  356.         lsb: 0

  357.         reset_value: '0'

  358.         width: 1

  359.     - WAKEUP1_SETEN:

  360.         access: w

  361.         description: Writing a 1 to this bit sets the event enable bit 1 in the ENABLE

  362.           register

  363.         lsb: 1

  364.         reset_value: '0'

  365.         width: 1

  366.     - WAKEUP2_SETEN:

  367.         access: w

  368.         description: Writing a 1 to this bit sets the event enable bit 2 in the ENABLE

  369.           register

  370.         lsb: 2

  371.         reset_value: '0'

  372.         width: 1

  373.     - WAKEUP3_SETEN:

  374.         access: w

  375.         description: Writing a 1 to this bit sets the event enable bit 3 in the ENABLE

  376.           register

  377.         lsb: 3

  378.         reset_value: '0'

  379.         width: 1

  380.     - ATIMER_SETEN:

  381.         access: w

  382.         description: Writing a 1 to this bit sets the event enable bit 4 in the ENABLE

  383.           register

  384.         lsb: 4

  385.         reset_value: '0'

  386.         width: 1

  387.     - RTC_SETEN:

  388.         access: w

  389.         description: Writing a 1 to this bit sets the event enable bit 5 in the ENABLE

  390.           register

  391.         lsb: 5

  392.         reset_value: '0'

  393.         width: 1

  394.     - BOD_SETEN:

  395.         access: w

  396.         description: Writing a 1 to this bit sets the event enable bit 6 in the ENABLE

  397.           register

  398.         lsb: 6

  399.         reset_value: '0'

  400.         width: 1

  401.     - WWDT_SETEN:

  402.         access: w

  403.         description: Writing a 1 to this bit sets the event enable bit 7 in the ENABLE

  404.           register

  405.         lsb: 7

  406.         reset_value: '0'

  407.         width: 1

  408.     - ETH_SETEN:

  409.         access: w

  410.         description: Writing a 1 to this bit sets the event enable bit 8 in the ENABLE

  411.           register

  412.         lsb: 8

  413.         reset_value: '0'

  414.         width: 1

  415.     - USB0_SETEN:

  416.         access: w

  417.         description: Writing a 1 to this bit sets the event enable bit 9 in the ENABLE

  418.           register

  419.         lsb: 9

  420.         reset_value: '0'

  421.         width: 1

  422.     - USB1_SETEN:

  423.         access: w

  424.         description: Writing a 1 to this bit sets the event enable bit 10 in the ENABLE

  425.           register

  426.         lsb: 10

  427.         reset_value: '0'

  428.         width: 1

  429.     - SDMCC_SETEN:

  430.         access: w

  431.         description: Writing a 1 to this bit sets the event enable bit 11 in the ENABLE

  432.           register

  433.         lsb: 11

  434.         reset_value: '0'

  435.         width: 1

  436.     - CAN_SETEN:

  437.         access: w

  438.         description: Writing a 1 to this bit sets the event enable bit 12 in the ENABLE

  439.           register

  440.         lsb: 12

  441.         reset_value: '0'

  442.         width: 1

  443.     - TIM2_SETEN:

  444.         access: w

  445.         description: Writing a 1 to this bit sets the event enable bit 13 in the ENABLE

  446.           register

  447.         lsb: 13

  448.         reset_value: '0'

  449.         width: 1

  450.     - TIM6_SETEN:

  451.         access: w

  452.         description: Writing a 1 to this bit sets the event enable bit 14 in the ENABLE

  453.           register

  454.         lsb: 14

  455.         reset_value: '0'

  456.         width: 1

  457.     - QEI_SETEN:

  458.         access: w

  459.         description: Writing a 1 to this bit sets the event enable bit 15 in the ENABLE

  460.           register

  461.         lsb: 15

  462.         reset_value: '0'

  463.         width: 1

  464.     - TIM14_SETEN:

  465.         access: w

  466.         description: Writing a 1 to this bit sets the event enable bit 16 in the ENABLE

  467.           register

  468.         lsb: 16

  469.         reset_value: '0'

  470.         width: 1

  471.     - RESET_SETEN:

  472.         access: w

  473.         description: Writing a 1 to this bit sets the event enable bit 19 in the ENABLE

  474.           register

  475.         lsb: 19

  476.         reset_value: '0'

  477.         width: 1

  478. - EVENTROUTER_STATUS:

  479.     fields: !!omap

  480.     - WAKEUP0_ST:

  481.         access: r

  482.         description: A 1 in this bit shows that the WAKEUP0 event has been raised

  483.         lsb: 0

  484.         reset_value: '1'

  485.         width: 1

  486.     - WAKEUP1_ST:

  487.         access: r

  488.         description: A 1 in this bit shows that the WAKEUP1 event has been raised

  489.         lsb: 1

  490.         reset_value: '1'

  491.         width: 1

  492.     - WAKEUP2_ST:

  493.         access: r

  494.         description: A 1 in this bit shows that the WAKEUP2 event has been raised

  495.         lsb: 2

  496.         reset_value: '1'

  497.         width: 1

  498.     - WAKEUP3_ST:

  499.         access: r

  500.         description: A 1 in this bit shows that the WAKEUP3 event has been raised

  501.         lsb: 3

  502.         reset_value: '1'

  503.         width: 1

  504.     - ATIMER_ST:

  505.         access: r

  506.         description: A 1 in this bit shows that the ATIMER event has been raised

  507.         lsb: 4

  508.         reset_value: '1'

  509.         width: 1

  510.     - RTC_ST:

  511.         access: r

  512.         description: A 1 in this bit shows that the RTC event has been raised

  513.         lsb: 5

  514.         reset_value: '1'

  515.         width: 1

  516.     - BOD_ST:

  517.         access: r

  518.         description: A 1 in this bit shows that the BOD event has been raised

  519.         lsb: 6

  520.         reset_value: '1'

  521.         width: 1

  522.     - WWDT_ST:

  523.         access: r

  524.         description: A 1 in this bit shows that the WWDT event has been raised

  525.         lsb: 7

  526.         reset_value: '1'

  527.         width: 1

  528.     - ETH_ST:

  529.         access: r

  530.         description: A 1 in this bit shows that the ETH event has been raised

  531.         lsb: 8

  532.         reset_value: '1'

  533.         width: 1

  534.     - USB0_ST:

  535.         access: r

  536.         description: A 1 in this bit shows that the USB0 event has been raised

  537.         lsb: 9

  538.         reset_value: '1'

  539.         width: 1

  540.     - USB1_ST:

  541.         access: r

  542.         description: A 1 in this bit shows that the USB1 event has been raised

  543.         lsb: 10

  544.         reset_value: '1'

  545.         width: 1

  546.     - SDMMC_ST:

  547.         access: r

  548.         description: A 1 in this bit shows that the SDMMC event has been raised

  549.         lsb: 11

  550.         reset_value: '1'

  551.         width: 1

  552.     - CAN_ST:

  553.         access: r

  554.         description: A 1 in this bit shows that the CAN event has been raised

  555.         lsb: 12

  556.         reset_value: '1'

  557.         width: 1

  558.     - TIM2_ST:

  559.         access: r

  560.         description: A 1 in this bit shows that the combined timer 2 output event

  561.           has been raised

  562.         lsb: 13

  563.         reset_value: '1'

  564.         width: 1

  565.     - TIM6_ST:

  566.         access: r

  567.         description: A 1 in this bit shows that the combined timer 6 output event

  568.           has been raised

  569.         lsb: 14

  570.         reset_value: '1'

  571.         width: 1

  572.     - QEI_ST:

  573.         access: r

  574.         description: A 1 in this bit shows that the QEI event has been raised

  575.         lsb: 15

  576.         reset_value: '1'

  577.         width: 1

  578.     - TIM14_ST:

  579.         access: r

  580.         description: A 1 in this bit shows that the combined timer 14 output event

  581.           has been raised

  582.         lsb: 16

  583.         reset_value: '1'

  584.         width: 1

  585.     - RESET_ST:

  586.         access: r

  587.         description: A 1 in this bit shows that the reset event has been raised

  588.         lsb: 19

  589.         reset_value: '1'

  590.         width: 1

  591. - EVENTROUTER_ENABLE:

  592.     fields: !!omap

  593.     - WAKEUP0_EN:

  594.         access: r

  595.         description: A 1 in this bit shows that the WAKEUP0 event has been enabled

  596.         lsb: 0

  597.         reset_value: '0'

  598.         width: 1

  599.     - WAKEUP1_EN:

  600.         access: r

  601.         description: A 1 in this bit shows that the WAKEUP1 event has been enabled

  602.         lsb: 1

  603.         reset_value: '0'

  604.         width: 1

  605.     - WAKEUP2_EN:

  606.         access: r

  607.         description: A 1 in this bit shows that the WAKEUP2 event has been enabled

  608.         lsb: 2

  609.         reset_value: '0'

  610.         width: 1

  611.     - WAKEUP3_EN:

  612.         access: r

  613.         description: A 1 in this bit shows that the WAKEUP3 event has been enabled

  614.         lsb: 3

  615.         reset_value: '0'

  616.         width: 1

  617.     - ATIMER_EN:

  618.         access: r

  619.         description: A 1 in this bit shows that the ATIMER event has been enabled

  620.         lsb: 4

  621.         reset_value: '0'

  622.         width: 1

  623.     - RTC_EN:

  624.         access: r

  625.         description: A 1 in this bit shows that the RTC event has been enabled

  626.         lsb: 5

  627.         reset_value: '0'

  628.         width: 1

  629.     - BOD_EN:

  630.         access: r

  631.         description: A 1 in this bit shows that the BOD event has been enabled

  632.         lsb: 6

  633.         reset_value: '0'

  634.         width: 1

  635.     - WWDT_EN:

  636.         access: r

  637.         description: A 1 in this bit shows that the WWDT event has been enabled

  638.         lsb: 7

  639.         reset_value: '0'

  640.         width: 1

  641.     - ETH_EN:

  642.         access: r

  643.         description: A 1 in this bit shows that the ETH event has been enabled

  644.         lsb: 8

  645.         reset_value: '0'

  646.         width: 1

  647.     - USB0_EN:

  648.         access: r

  649.         description: A 1 in this bit shows that the USB0 event has been enabled

  650.         lsb: 9

  651.         reset_value: '0'

  652.         width: 1

  653.     - USB1_EN:

  654.         access: r

  655.         description: A 1 in this bit shows that the USB1 event has been enabled

  656.         lsb: 10

  657.         reset_value: '0'

  658.         width: 1

  659.     - SDMMC_EN:

  660.         access: r

  661.         description: A 1 in this bit shows that the SDMMC event has been enabled

  662.         lsb: 11

  663.         reset_value: '0'

  664.         width: 1

  665.     - CAN_EN:

  666.         access: r

  667.         description: A 1 in this bit shows that the CAN event has been enabled

  668.         lsb: 12

  669.         reset_value: '0'

  670.         width: 1

  671.     - TIM2_EN:

  672.         access: r

  673.         description: A 1 in this bit shows that the combined timer 2 output event

  674.           has been enabled

  675.         lsb: 13

  676.         reset_value: '0'

  677.         width: 1

  678.     - TIM6_EN:

  679.         access: r

  680.         description: A 1 in this bit shows that the combined timer 6 output event

  681.           has been enabled

  682.         lsb: 14

  683.         reset_value: '0'

  684.         width: 1

  685.     - QEI_EN:

  686.         access: r

  687.         description: A 1 in this bit shows that the QEI event has been enabled

  688.         lsb: 15

  689.         reset_value: '0'

  690.         width: 1

  691.     - TIM14_EN:

  692.         access: r

  693.         description: A 1 in this bit shows that the combined timer 14 output event

  694.           has been enabled

  695.         lsb: 16

  696.         reset_value: '0'

  697.         width: 1

  698.     - RESET_EN:

  699.         access: r

  700.         description: A 1 in this bit shows that the reset event has been enabled

  701.         lsb: 19

  702.         reset_value: '0'

  703.         width: 1

  704. - EVENTROUTER_CLR_STAT:

  705.     fields: !!omap

  706.     - WAKEUP0_CLRST:

  707.         access: w

  708.         description: Writing a 1 to this bit clears the STATUS event bit 0 in the

  709.           STATUS register

  710.         lsb: 0

  711.         reset_value: '0'

  712.         width: 1

  713.     - WAKEUP1_CLRST:

  714.         access: w

  715.         description: Writing a 1 to this bit clears the STATUS event bit 1 in the

  716.           STATUS register

  717.         lsb: 1

  718.         reset_value: '0'

  719.         width: 1

  720.     - WAKEUP2_CLRST:

  721.         access: w

  722.         description: Writing a 1 to this bit clears the STATUS event bit 2 in the

  723.           STATUS register

  724.         lsb: 2

  725.         reset_value: '0'

  726.         width: 1

  727.     - WAKEUP3_CLRST:

  728.         access: w

  729.         description: Writing a 1 to this bit clears the STATUS event bit 3 in the

  730.           STATUS register

  731.         lsb: 3

  732.         reset_value: '0'

  733.         width: 1

  734.     - ATIMER_CLRST:

  735.         access: w

  736.         description: Writing a 1 to this bit clears the STATUS event bit 4 in the

  737.           STATUS register

  738.         lsb: 4

  739.         reset_value: '0'

  740.         width: 1

  741.     - RTC_CLRST:

  742.         access: w

  743.         description: Writing a 1 to this bit clears the STATUS event bit 5 in the

  744.           STATUS register

  745.         lsb: 5

  746.         reset_value: '0'

  747.         width: 1

  748.     - BOD_CLRST:

  749.         access: w

  750.         description: Writing a 1 to this bit clears the STATUS event bit 6 in the

  751.           STATUS register

  752.         lsb: 6

  753.         reset_value: '0'

  754.         width: 1

  755.     - WWDT_CLRST:

  756.         access: w

  757.         description: Writing a 1 to this bit clears the STATUS event bit 7 in the

  758.           STATUS register

  759.         lsb: 7

  760.         reset_value: '0'

  761.         width: 1

  762.     - ETH_CLRST:

  763.         access: w

  764.         description: Writing a 1 to this bit clears the STATUS event bit 8 in the

  765.           STATUS register

  766.         lsb: 8

  767.         reset_value: '0'

  768.         width: 1

  769.     - USB0_CLRST:

  770.         access: w

  771.         description: Writing a 1 to this bit clears the STATUS event bit 9 in the

  772.           STATUS register

  773.         lsb: 9

  774.         reset_value: '0'

  775.         width: 1

  776.     - USB1_CLRST:

  777.         access: w

  778.         description: Writing a 1 to this bit clears the STATUS event bit 10 in the

  779.           STATUS register

  780.         lsb: 10

  781.         reset_value: '0'

  782.         width: 1

  783.     - SDMCC_CLRST:

  784.         access: w

  785.         description: Writing a 1 to this bit clears the STATUS event bit 11 in the

  786.           STATUS register

  787.         lsb: 11

  788.         reset_value: '0'

  789.         width: 1

  790.     - CAN_CLRST:

  791.         access: w

  792.         description: Writing a 1 to this bit clears the STATUS event bit 12 in the

  793.           STATUS register

  794.         lsb: 12

  795.         reset_value: '0'

  796.         width: 1

  797.     - TIM2_CLRST:

  798.         access: w

  799.         description: Writing a 1 to this bit clears the STATUS event bit 13 in the

  800.           STATUS register

  801.         lsb: 13

  802.         reset_value: '0'

  803.         width: 1

  804.     - TIM6_CLRST:

  805.         access: w

  806.         description: Writing a 1 to this bit clears the STATUS event bit 14 in the

  807.           STATUS register

  808.         lsb: 14

  809.         reset_value: '0'

  810.         width: 1

  811.     - QEI_CLRST:

  812.         access: w

  813.         description: Writing a 1 to this bit clears the STATUS event bit 15 in the

  814.           STATUS register

  815.         lsb: 15

  816.         reset_value: '0'

  817.         width: 1

  818.     - TIM14_CLRST:

  819.         access: w

  820.         description: Writing a 1 to this bit clears the STATUS event bit 16 in the

  821.           STATUS register

  822.         lsb: 16

  823.         reset_value: '0'

  824.         width: 1

  825.     - RESET_CLRST:

  826.         access: w

  827.         description: Writing a 1 to this bit clears the STATUS event bit 19 in the

  828.           STATUS register

  829.         lsb: 19

  830.         reset_value: '0'

  831.         width: 1

  832. - EVENTROUTER_SET_STAT:

  833.     fields: !!omap

  834.     - WAKEUP0_SETST:

  835.         access: w

  836.         description: Writing a 1 to this bit sets the STATUS event bit 0 in the STATUS

  837.           register

  838.         lsb: 0

  839.         reset_value: '0'

  840.         width: 1

  841.     - WAKEUP1_SETST:

  842.         access: w

  843.         description: Writing a 1 to this bit sets the STATUS event bit 1 in the STATUS

  844.           register

  845.         lsb: 1

  846.         reset_value: '0'

  847.         width: 1

  848.     - WAKEUP2_SETST:

  849.         access: w

  850.         description: Writing a 1 to this bit sets the STATUS event bit 2 in the STATUS

  851.           register

  852.         lsb: 2

  853.         reset_value: '0'

  854.         width: 1

  855.     - WAKEUP3_SETST:

  856.         access: w

  857.         description: Writing a 1 to this bit sets the STATUS event bit 3 in the STATUS

  858.           register

  859.         lsb: 3

  860.         reset_value: '0'

  861.         width: 1

  862.     - ATIMER_SETST:

  863.         access: w

  864.         description: Writing a 1 to this bit sets the STATUS event bit 4 in the STATUS

  865.           register

  866.         lsb: 4

  867.         reset_value: '0'

  868.         width: 1

  869.     - RTC_SETST:

  870.         access: w

  871.         description: Writing a 1 to this bit sets the STATUS event bit 5 in the STATUS

  872.           register

  873.         lsb: 5

  874.         reset_value: '0'

  875.         width: 1

  876.     - BOD_SETST:

  877.         access: w

  878.         description: Writing a 1 to this bit sets the STATUS event bit 6 in the STATUS

  879.           register

  880.         lsb: 6

  881.         reset_value: '0'

  882.         width: 1

  883.     - WWDT_SETST:

  884.         access: w

  885.         description: Writing a 1 to this bit sets the STATUS event bit 7 in the STATUS

  886.           register

  887.         lsb: 7

  888.         reset_value: '0'

  889.         width: 1

  890.     - ETH_SETST:

  891.         access: w

  892.         description: Writing a 1 to this bit sets the STATUS event bit 8 in the STATUS

  893.           register

  894.         lsb: 8

  895.         reset_value: '0'

  896.         width: 1

  897.     - USB0_SETST:

  898.         access: w

  899.         description: Writing a 1 to this bit sets the STATUS event bit 9 in the STATUS

  900.           register

  901.         lsb: 9

  902.         reset_value: '0'

  903.         width: 1

  904.     - USB1_SETST:

  905.         access: w

  906.         description: Writing a 1 to this bit sets the STATUS event bit 10 in the STATUS

  907.           register

  908.         lsb: 10

  909.         reset_value: '0'

  910.         width: 1

  911.     - SDMCC_SETST:

  912.         access: w

  913.         description: Writing a 1 to this bit sets the STATUS event bit 11 in the STATUS

  914.           register

  915.         lsb: 11

  916.         reset_value: '0'

  917.         width: 1

  918.     - CAN_SETST:

  919.         access: w

  920.         description: Writing a 1 to this bit sets the STATUS event bit 12 in the STATUS

  921.           register

  922.         lsb: 12

  923.         reset_value: '0'

  924.         width: 1

  925.     - TIM2_SETST:

  926.         access: w

  927.         description: Writing a 1 to this bit sets the STATUS event bit 13 in the STATUS

  928.           register

  929.         lsb: 13

  930.         reset_value: '0'

  931.         width: 1

  932.     - TIM6_SETST:

  933.         access: w

  934.         description: Writing a 1 to this bit sets the STATUS event bit 14 in the STATUS

  935.           register

  936.         lsb: 14

  937.         reset_value: '0'

  938.         width: 1

  939.     - QEI_SETST:

  940.         access: w

  941.         description: Writing a 1 to this bit sets the STATUS event bit 15 in the STATUS

  942.           register

  943.         lsb: 15

  944.         reset_value: '0'

  945.         width: 1

  946.     - TIM14_SETST:

  947.         access: w

  948.         description: Writing a 1 to this bit sets the STATUS event bit 16 in the STATUS

  949.           register

  950.         lsb: 16

  951.         reset_value: '0'

  952.         width: 1

  953.     - RESET_SETST:

  954.         access: w

  955.         description: Writing a 1 to this bit sets the STATUS event bit 19 in the STATUS

  956.           register

  957.         lsb: 19

  958.         reset_value: '0'

  959.         width: 1