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m4_init/3rd/libopencm3/scripts/data/lpc43xx/sgpio.yaml

1954 строки
45 KiB
Исходник Постоянная ссылка Вина История 

  1. !!omap

  2. - SGPIO_OUT_MUX_CFG0:

  3.     fields: !!omap

  4.     - P_OUT_CFG:

  5.         access: rw

  6.         description: Output control of output SGPIOn

  7.         lsb: 0

  8.         reset_value: '0'

  9.         width: 4

  10.     - P_OE_CFG:

  11.         access: rw

  12.         description: Output enable source

  13.         lsb: 4

  14.         reset_value: '0'

  15.         width: 3

  16. - SGPIO_OUT_MUX_CFG1:

  17.     fields: !!omap

  18.     - P_OUT_CFG:

  19.         access: rw

  20.         description: Output control of output SGPIOn

  21.         lsb: 0

  22.         reset_value: '0'

  23.         width: 4

  24.     - P_OE_CFG:

  25.         access: rw

  26.         description: Output enable source

  27.         lsb: 4

  28.         reset_value: '0'

  29.         width: 3

  30. - SGPIO_OUT_MUX_CFG2:

  31.     fields: !!omap

  32.     - P_OUT_CFG:

  33.         access: rw

  34.         description: Output control of output SGPIOn

  35.         lsb: 0

  36.         reset_value: '0'

  37.         width: 4

  38.     - P_OE_CFG:

  39.         access: rw

  40.         description: Output enable source

  41.         lsb: 4

  42.         reset_value: '0'

  43.         width: 3

  44. - SGPIO_OUT_MUX_CFG3:

  45.     fields: !!omap

  46.     - P_OUT_CFG:

  47.         access: rw

  48.         description: Output control of output SGPIOn

  49.         lsb: 0

  50.         reset_value: '0'

  51.         width: 4

  52.     - P_OE_CFG:

  53.         access: rw

  54.         description: Output enable source

  55.         lsb: 4

  56.         reset_value: '0'

  57.         width: 3

  58. - SGPIO_OUT_MUX_CFG4:

  59.     fields: !!omap

  60.     - P_OUT_CFG:

  61.         access: rw

  62.         description: Output control of output SGPIOn

  63.         lsb: 0

  64.         reset_value: '0'

  65.         width: 4

  66.     - P_OE_CFG:

  67.         access: rw

  68.         description: Output enable source

  69.         lsb: 4

  70.         reset_value: '0'

  71.         width: 3

  72. - SGPIO_OUT_MUX_CFG5:

  73.     fields: !!omap

  74.     - P_OUT_CFG:

  75.         access: rw

  76.         description: Output control of output SGPIOn

  77.         lsb: 0

  78.         reset_value: '0'

  79.         width: 4

  80.     - P_OE_CFG:

  81.         access: rw

  82.         description: Output enable source

  83.         lsb: 4

  84.         reset_value: '0'

  85.         width: 3

  86. - SGPIO_OUT_MUX_CFG6:

  87.     fields: !!omap

  88.     - P_OUT_CFG:

  89.         access: rw

  90.         description: Output control of output SGPIOn

  91.         lsb: 0

  92.         reset_value: '0'

  93.         width: 4

  94.     - P_OE_CFG:

  95.         access: rw

  96.         description: Output enable source

  97.         lsb: 4

  98.         reset_value: '0'

  99.         width: 3

  100. - SGPIO_OUT_MUX_CFG7:

  101.     fields: !!omap

  102.     - P_OUT_CFG:

  103.         access: rw

  104.         description: Output control of output SGPIOn

  105.         lsb: 0

  106.         reset_value: '0'

  107.         width: 4

  108.     - P_OE_CFG:

  109.         access: rw

  110.         description: Output enable source

  111.         lsb: 4

  112.         reset_value: '0'

  113.         width: 3

  114. - SGPIO_OUT_MUX_CFG8:

  115.     fields: !!omap

  116.     - P_OUT_CFG:

  117.         access: rw

  118.         description: Output control of output SGPIOn

  119.         lsb: 0

  120.         reset_value: '0'

  121.         width: 4

  122.     - P_OE_CFG:

  123.         access: rw

  124.         description: Output enable source

  125.         lsb: 4

  126.         reset_value: '0'

  127.         width: 3

  128. - SGPIO_OUT_MUX_CFG9:

  129.     fields: !!omap

  130.     - P_OUT_CFG:

  131.         access: rw

  132.         description: Output control of output SGPIOn

  133.         lsb: 0

  134.         reset_value: '0'

  135.         width: 4

  136.     - P_OE_CFG:

  137.         access: rw

  138.         description: Output enable source

  139.         lsb: 4

  140.         reset_value: '0'

  141.         width: 3

  142. - SGPIO_OUT_MUX_CFG10:

  143.     fields: !!omap

  144.     - P_OUT_CFG:

  145.         access: rw

  146.         description: Output control of output SGPIOn

  147.         lsb: 0

  148.         reset_value: '0'

  149.         width: 4

  150.     - P_OE_CFG:

  151.         access: rw

  152.         description: Output enable source

  153.         lsb: 4

  154.         reset_value: '0'

  155.         width: 3

  156. - SGPIO_OUT_MUX_CFG11:

  157.     fields: !!omap

  158.     - P_OUT_CFG:

  159.         access: rw

  160.         description: Output control of output SGPIOn

  161.         lsb: 0

  162.         reset_value: '0'

  163.         width: 4

  164.     - P_OE_CFG:

  165.         access: rw

  166.         description: Output enable source

  167.         lsb: 4

  168.         reset_value: '0'

  169.         width: 3

  170. - SGPIO_OUT_MUX_CFG12:

  171.     fields: !!omap

  172.     - P_OUT_CFG:

  173.         access: rw

  174.         description: Output control of output SGPIOn

  175.         lsb: 0

  176.         reset_value: '0'

  177.         width: 4

  178.     - P_OE_CFG:

  179.         access: rw

  180.         description: Output enable source

  181.         lsb: 4

  182.         reset_value: '0'

  183.         width: 3

  184. - SGPIO_OUT_MUX_CFG13:

  185.     fields: !!omap

  186.     - P_OUT_CFG:

  187.         access: rw

  188.         description: Output control of output SGPIOn

  189.         lsb: 0

  190.         reset_value: '0'

  191.         width: 4

  192.     - P_OE_CFG:

  193.         access: rw

  194.         description: Output enable source

  195.         lsb: 4

  196.         reset_value: '0'

  197.         width: 3

  198. - SGPIO_OUT_MUX_CFG14:

  199.     fields: !!omap

  200.     - P_OUT_CFG:

  201.         access: rw

  202.         description: Output control of output SGPIOn

  203.         lsb: 0

  204.         reset_value: '0'

  205.         width: 4

  206.     - P_OE_CFG:

  207.         access: rw

  208.         description: Output enable source

  209.         lsb: 4

  210.         reset_value: '0'

  211.         width: 3

  212. - SGPIO_OUT_MUX_CFG15:

  213.     fields: !!omap

  214.     - P_OUT_CFG:

  215.         access: rw

  216.         description: Output control of output SGPIOn

  217.         lsb: 0

  218.         reset_value: '0'

  219.         width: 4

  220.     - P_OE_CFG:

  221.         access: rw

  222.         description: Output enable source

  223.         lsb: 4

  224.         reset_value: '0'

  225.         width: 3

  226. - SGPIO_MUX_CFG0:

  227.     fields: !!omap

  228.     - EXT_CLK_ENABLE:

  229.         access: rw

  230.         description: Select clock signal

  231.         lsb: 0

  232.         reset_value: '0'

  233.         width: 1

  234.     - CLK_SOURCE_PIN_MODE:

  235.         access: rw

  236.         description: Select source clock pin

  237.         lsb: 1

  238.         reset_value: '0'

  239.         width: 2

  240.     - CLK_SOURCE_SLICE_MODE:

  241.         access: rw

  242.         description: Select clock source slice

  243.         lsb: 3

  244.         reset_value: '0'

  245.         width: 2

  246.     - QUALIFIER_MODE:

  247.         access: rw

  248.         description: Select qualifier mode

  249.         lsb: 5

  250.         reset_value: '0'

  251.         width: 2

  252.     - QUALIFIER_PIN_MODE:

  253.         access: rw

  254.         description: Select qualifier pin

  255.         lsb: 7

  256.         reset_value: '0'

  257.         width: 2

  258.     - QUALIFIER_SLICE_MODE:

  259.         access: rw

  260.         description: Select qualifier slice

  261.         lsb: 9

  262.         reset_value: '0'

  263.         width: 2

  264.     - CONCAT_ENABLE:

  265.         access: rw

  266.         description: Enable concatenation

  267.         lsb: 11

  268.         reset_value: '0'

  269.         width: 1

  270.     - CONCAT_ORDER:

  271.         access: rw

  272.         description: Select concatenation order

  273.         lsb: 12

  274.         reset_value: '0'

  275.         width: 2

  276. - SGPIO_MUX_CFG1:

  277.     fields: !!omap

  278.     - EXT_CLK_ENABLE:

  279.         access: rw

  280.         description: Select clock signal

  281.         lsb: 0

  282.         reset_value: '0'

  283.         width: 1

  284.     - CLK_SOURCE_PIN_MODE:

  285.         access: rw

  286.         description: Select source clock pin

  287.         lsb: 1

  288.         reset_value: '0'

  289.         width: 2

  290.     - CLK_SOURCE_SLICE_MODE:

  291.         access: rw

  292.         description: Select clock source slice

  293.         lsb: 3

  294.         reset_value: '0'

  295.         width: 2

  296.     - QUALIFIER_MODE:

  297.         access: rw

  298.         description: Select qualifier mode

  299.         lsb: 5

  300.         reset_value: '0'

  301.         width: 2

  302.     - QUALIFIER_PIN_MODE:

  303.         access: rw

  304.         description: Select qualifier pin

  305.         lsb: 7

  306.         reset_value: '0'

  307.         width: 2

  308.     - QUALIFIER_SLICE_MODE:

  309.         access: rw

  310.         description: Select qualifier slice

  311.         lsb: 9

  312.         reset_value: '0'

  313.         width: 2

  314.     - CONCAT_ENABLE:

  315.         access: rw

  316.         description: Enable concatenation

  317.         lsb: 11

  318.         reset_value: '0'

  319.         width: 1

  320.     - CONCAT_ORDER:

  321.         access: rw

  322.         description: Select concatenation order

  323.         lsb: 12

  324.         reset_value: '0'

  325.         width: 2

  326. - SGPIO_MUX_CFG2:

  327.     fields: !!omap

  328.     - EXT_CLK_ENABLE:

  329.         access: rw

  330.         description: Select clock signal

  331.         lsb: 0

  332.         reset_value: '0'

  333.         width: 1

  334.     - CLK_SOURCE_PIN_MODE:

  335.         access: rw

  336.         description: Select source clock pin

  337.         lsb: 1

  338.         reset_value: '0'

  339.         width: 2

  340.     - CLK_SOURCE_SLICE_MODE:

  341.         access: rw

  342.         description: Select clock source slice

  343.         lsb: 3

  344.         reset_value: '0'

  345.         width: 2

  346.     - QUALIFIER_MODE:

  347.         access: rw

  348.         description: Select qualifier mode

  349.         lsb: 5

  350.         reset_value: '0'

  351.         width: 2

  352.     - QUALIFIER_PIN_MODE:

  353.         access: rw

  354.         description: Select qualifier pin

  355.         lsb: 7

  356.         reset_value: '0'

  357.         width: 2

  358.     - QUALIFIER_SLICE_MODE:

  359.         access: rw

  360.         description: Select qualifier slice

  361.         lsb: 9

  362.         reset_value: '0'

  363.         width: 2

  364.     - CONCAT_ENABLE:

  365.         access: rw

  366.         description: Enable concatenation

  367.         lsb: 11

  368.         reset_value: '0'

  369.         width: 1

  370.     - CONCAT_ORDER:

  371.         access: rw

  372.         description: Select concatenation order

  373.         lsb: 12

  374.         reset_value: '0'

  375.         width: 2

  376. - SGPIO_MUX_CFG3:

  377.     fields: !!omap

  378.     - EXT_CLK_ENABLE:

  379.         access: rw

  380.         description: Select clock signal

  381.         lsb: 0

  382.         reset_value: '0'

  383.         width: 1

  384.     - CLK_SOURCE_PIN_MODE:

  385.         access: rw

  386.         description: Select source clock pin

  387.         lsb: 1

  388.         reset_value: '0'

  389.         width: 2

  390.     - CLK_SOURCE_SLICE_MODE:

  391.         access: rw

  392.         description: Select clock source slice

  393.         lsb: 3

  394.         reset_value: '0'

  395.         width: 2

  396.     - QUALIFIER_MODE:

  397.         access: rw

  398.         description: Select qualifier mode

  399.         lsb: 5

  400.         reset_value: '0'

  401.         width: 2

  402.     - QUALIFIER_PIN_MODE:

  403.         access: rw

  404.         description: Select qualifier pin

  405.         lsb: 7

  406.         reset_value: '0'

  407.         width: 2

  408.     - QUALIFIER_SLICE_MODE:

  409.         access: rw

  410.         description: Select qualifier slice

  411.         lsb: 9

  412.         reset_value: '0'

  413.         width: 2

  414.     - CONCAT_ENABLE:

  415.         access: rw

  416.         description: Enable concatenation

  417.         lsb: 11

  418.         reset_value: '0'

  419.         width: 1

  420.     - CONCAT_ORDER:

  421.         access: rw

  422.         description: Select concatenation order

  423.         lsb: 12

  424.         reset_value: '0'

  425.         width: 2

  426. - SGPIO_MUX_CFG4:

  427.     fields: !!omap

  428.     - EXT_CLK_ENABLE:

  429.         access: rw

  430.         description: Select clock signal

  431.         lsb: 0

  432.         reset_value: '0'

  433.         width: 1

  434.     - CLK_SOURCE_PIN_MODE:

  435.         access: rw

  436.         description: Select source clock pin

  437.         lsb: 1

  438.         reset_value: '0'

  439.         width: 2

  440.     - CLK_SOURCE_SLICE_MODE:

  441.         access: rw

  442.         description: Select clock source slice

  443.         lsb: 3

  444.         reset_value: '0'

  445.         width: 2

  446.     - QUALIFIER_MODE:

  447.         access: rw

  448.         description: Select qualifier mode

  449.         lsb: 5

  450.         reset_value: '0'

  451.         width: 2

  452.     - QUALIFIER_PIN_MODE:

  453.         access: rw

  454.         description: Select qualifier pin

  455.         lsb: 7

  456.         reset_value: '0'

  457.         width: 2

  458.     - QUALIFIER_SLICE_MODE:

  459.         access: rw

  460.         description: Select qualifier slice

  461.         lsb: 9

  462.         reset_value: '0'

  463.         width: 2

  464.     - CONCAT_ENABLE:

  465.         access: rw

  466.         description: Enable concatenation

  467.         lsb: 11

  468.         reset_value: '0'

  469.         width: 1

  470.     - CONCAT_ORDER:

  471.         access: rw

  472.         description: Select concatenation order

  473.         lsb: 12

  474.         reset_value: '0'

  475.         width: 2

  476. - SGPIO_MUX_CFG5:

  477.     fields: !!omap

  478.     - EXT_CLK_ENABLE:

  479.         access: rw

  480.         description: Select clock signal

  481.         lsb: 0

  482.         reset_value: '0'

  483.         width: 1

  484.     - CLK_SOURCE_PIN_MODE:

  485.         access: rw

  486.         description: Select source clock pin

  487.         lsb: 1

  488.         reset_value: '0'

  489.         width: 2

  490.     - CLK_SOURCE_SLICE_MODE:

  491.         access: rw

  492.         description: Select clock source slice

  493.         lsb: 3

  494.         reset_value: '0'

  495.         width: 2

  496.     - QUALIFIER_MODE:

  497.         access: rw

  498.         description: Select qualifier mode

  499.         lsb: 5

  500.         reset_value: '0'

  501.         width: 2

  502.     - QUALIFIER_PIN_MODE:

  503.         access: rw

  504.         description: Select qualifier pin

  505.         lsb: 7

  506.         reset_value: '0'

  507.         width: 2

  508.     - QUALIFIER_SLICE_MODE:

  509.         access: rw

  510.         description: Select qualifier slice

  511.         lsb: 9

  512.         reset_value: '0'

  513.         width: 2

  514.     - CONCAT_ENABLE:

  515.         access: rw

  516.         description: Enable concatenation

  517.         lsb: 11

  518.         reset_value: '0'

  519.         width: 1

  520.     - CONCAT_ORDER:

  521.         access: rw

  522.         description: Select concatenation order

  523.         lsb: 12

  524.         reset_value: '0'

  525.         width: 2

  526. - SGPIO_MUX_CFG6:

  527.     fields: !!omap

  528.     - EXT_CLK_ENABLE:

  529.         access: rw

  530.         description: Select clock signal

  531.         lsb: 0

  532.         reset_value: '0'

  533.         width: 1

  534.     - CLK_SOURCE_PIN_MODE:

  535.         access: rw

  536.         description: Select source clock pin

  537.         lsb: 1

  538.         reset_value: '0'

  539.         width: 2

  540.     - CLK_SOURCE_SLICE_MODE:

  541.         access: rw

  542.         description: Select clock source slice

  543.         lsb: 3

  544.         reset_value: '0'

  545.         width: 2

  546.     - QUALIFIER_MODE:

  547.         access: rw

  548.         description: Select qualifier mode

  549.         lsb: 5

  550.         reset_value: '0'

  551.         width: 2

  552.     - QUALIFIER_PIN_MODE:

  553.         access: rw

  554.         description: Select qualifier pin

  555.         lsb: 7

  556.         reset_value: '0'

  557.         width: 2

  558.     - QUALIFIER_SLICE_MODE:

  559.         access: rw

  560.         description: Select qualifier slice

  561.         lsb: 9

  562.         reset_value: '0'

  563.         width: 2

  564.     - CONCAT_ENABLE:

  565.         access: rw

  566.         description: Enable concatenation

  567.         lsb: 11

  568.         reset_value: '0'

  569.         width: 1

  570.     - CONCAT_ORDER:

  571.         access: rw

  572.         description: Select concatenation order

  573.         lsb: 12

  574.         reset_value: '0'

  575.         width: 2

  576. - SGPIO_MUX_CFG7:

  577.     fields: !!omap

  578.     - EXT_CLK_ENABLE:

  579.         access: rw

  580.         description: Select clock signal

  581.         lsb: 0

  582.         reset_value: '0'

  583.         width: 1

  584.     - CLK_SOURCE_PIN_MODE:

  585.         access: rw

  586.         description: Select source clock pin

  587.         lsb: 1

  588.         reset_value: '0'

  589.         width: 2

  590.     - CLK_SOURCE_SLICE_MODE:

  591.         access: rw

  592.         description: Select clock source slice

  593.         lsb: 3

  594.         reset_value: '0'

  595.         width: 2

  596.     - QUALIFIER_MODE:

  597.         access: rw

  598.         description: Select qualifier mode

  599.         lsb: 5

  600.         reset_value: '0'

  601.         width: 2

  602.     - QUALIFIER_PIN_MODE:

  603.         access: rw

  604.         description: Select qualifier pin

  605.         lsb: 7

  606.         reset_value: '0'

  607.         width: 2

  608.     - QUALIFIER_SLICE_MODE:

  609.         access: rw

  610.         description: Select qualifier slice

  611.         lsb: 9

  612.         reset_value: '0'

  613.         width: 2

  614.     - CONCAT_ENABLE:

  615.         access: rw

  616.         description: Enable concatenation

  617.         lsb: 11

  618.         reset_value: '0'

  619.         width: 1

  620.     - CONCAT_ORDER:

  621.         access: rw

  622.         description: Select concatenation order

  623.         lsb: 12

  624.         reset_value: '0'

  625.         width: 2

  626. - SGPIO_MUX_CFG8:

  627.     fields: !!omap

  628.     - EXT_CLK_ENABLE:

  629.         access: rw

  630.         description: Select clock signal

  631.         lsb: 0

  632.         reset_value: '0'

  633.         width: 1

  634.     - CLK_SOURCE_PIN_MODE:

  635.         access: rw

  636.         description: Select source clock pin

  637.         lsb: 1

  638.         reset_value: '0'

  639.         width: 2

  640.     - CLK_SOURCE_SLICE_MODE:

  641.         access: rw

  642.         description: Select clock source slice

  643.         lsb: 3

  644.         reset_value: '0'

  645.         width: 2

  646.     - QUALIFIER_MODE:

  647.         access: rw

  648.         description: Select qualifier mode

  649.         lsb: 5

  650.         reset_value: '0'

  651.         width: 2

  652.     - QUALIFIER_PIN_MODE:

  653.         access: rw

  654.         description: Select qualifier pin

  655.         lsb: 7

  656.         reset_value: '0'

  657.         width: 2

  658.     - QUALIFIER_SLICE_MODE:

  659.         access: rw

  660.         description: Select qualifier slice

  661.         lsb: 9

  662.         reset_value: '0'

  663.         width: 2

  664.     - CONCAT_ENABLE:

  665.         access: rw

  666.         description: Enable concatenation

  667.         lsb: 11

  668.         reset_value: '0'

  669.         width: 1

  670.     - CONCAT_ORDER:

  671.         access: rw

  672.         description: Select concatenation order

  673.         lsb: 12

  674.         reset_value: '0'

  675.         width: 2

  676. - SGPIO_MUX_CFG9:

  677.     fields: !!omap

  678.     - EXT_CLK_ENABLE:

  679.         access: rw

  680.         description: Select clock signal

  681.         lsb: 0

  682.         reset_value: '0'

  683.         width: 1

  684.     - CLK_SOURCE_PIN_MODE:

  685.         access: rw

  686.         description: Select source clock pin

  687.         lsb: 1

  688.         reset_value: '0'

  689.         width: 2

  690.     - CLK_SOURCE_SLICE_MODE:

  691.         access: rw

  692.         description: Select clock source slice

  693.         lsb: 3

  694.         reset_value: '0'

  695.         width: 2

  696.     - QUALIFIER_MODE:

  697.         access: rw

  698.         description: Select qualifier mode

  699.         lsb: 5

  700.         reset_value: '0'

  701.         width: 2

  702.     - QUALIFIER_PIN_MODE:

  703.         access: rw

  704.         description: Select qualifier pin

  705.         lsb: 7

  706.         reset_value: '0'

  707.         width: 2

  708.     - QUALIFIER_SLICE_MODE:

  709.         access: rw

  710.         description: Select qualifier slice

  711.         lsb: 9

  712.         reset_value: '0'

  713.         width: 2

  714.     - CONCAT_ENABLE:

  715.         access: rw

  716.         description: Enable concatenation

  717.         lsb: 11

  718.         reset_value: '0'

  719.         width: 1

  720.     - CONCAT_ORDER:

  721.         access: rw

  722.         description: Select concatenation order

  723.         lsb: 12

  724.         reset_value: '0'

  725.         width: 2

  726. - SGPIO_MUX_CFG10:

  727.     fields: !!omap

  728.     - EXT_CLK_ENABLE:

  729.         access: rw

  730.         description: Select clock signal

  731.         lsb: 0

  732.         reset_value: '0'

  733.         width: 1

  734.     - CLK_SOURCE_PIN_MODE:

  735.         access: rw

  736.         description: Select source clock pin

  737.         lsb: 1

  738.         reset_value: '0'

  739.         width: 2

  740.     - CLK_SOURCE_SLICE_MODE:

  741.         access: rw

  742.         description: Select clock source slice

  743.         lsb: 3

  744.         reset_value: '0'

  745.         width: 2

  746.     - QUALIFIER_MODE:

  747.         access: rw

  748.         description: Select qualifier mode

  749.         lsb: 5

  750.         reset_value: '0'

  751.         width: 2

  752.     - QUALIFIER_PIN_MODE:

  753.         access: rw

  754.         description: Select qualifier pin

  755.         lsb: 7

  756.         reset_value: '0'

  757.         width: 2

  758.     - QUALIFIER_SLICE_MODE:

  759.         access: rw

  760.         description: Select qualifier slice

  761.         lsb: 9

  762.         reset_value: '0'

  763.         width: 2

  764.     - CONCAT_ENABLE:

  765.         access: rw

  766.         description: Enable concatenation

  767.         lsb: 11

  768.         reset_value: '0'

  769.         width: 1

  770.     - CONCAT_ORDER:

  771.         access: rw

  772.         description: Select concatenation order

  773.         lsb: 12

  774.         reset_value: '0'

  775.         width: 2

  776. - SGPIO_MUX_CFG11:

  777.     fields: !!omap

  778.     - EXT_CLK_ENABLE:

  779.         access: rw

  780.         description: Select clock signal

  781.         lsb: 0

  782.         reset_value: '0'

  783.         width: 1

  784.     - CLK_SOURCE_PIN_MODE:

  785.         access: rw

  786.         description: Select source clock pin

  787.         lsb: 1

  788.         reset_value: '0'

  789.         width: 2

  790.     - CLK_SOURCE_SLICE_MODE:

  791.         access: rw

  792.         description: Select clock source slice

  793.         lsb: 3

  794.         reset_value: '0'

  795.         width: 2

  796.     - QUALIFIER_MODE:

  797.         access: rw

  798.         description: Select qualifier mode

  799.         lsb: 5

  800.         reset_value: '0'

  801.         width: 2

  802.     - QUALIFIER_PIN_MODE:

  803.         access: rw

  804.         description: Select qualifier pin

  805.         lsb: 7

  806.         reset_value: '0'

  807.         width: 2

  808.     - QUALIFIER_SLICE_MODE:

  809.         access: rw

  810.         description: Select qualifier slice

  811.         lsb: 9

  812.         reset_value: '0'

  813.         width: 2

  814.     - CONCAT_ENABLE:

  815.         access: rw

  816.         description: Enable concatenation

  817.         lsb: 11

  818.         reset_value: '0'

  819.         width: 1

  820.     - CONCAT_ORDER:

  821.         access: rw

  822.         description: Select concatenation order

  823.         lsb: 12

  824.         reset_value: '0'

  825.         width: 2

  826. - SGPIO_MUX_CFG12:

  827.     fields: !!omap

  828.     - EXT_CLK_ENABLE:

  829.         access: rw

  830.         description: Select clock signal

  831.         lsb: 0

  832.         reset_value: '0'

  833.         width: 1

  834.     - CLK_SOURCE_PIN_MODE:

  835.         access: rw

  836.         description: Select source clock pin

  837.         lsb: 1

  838.         reset_value: '0'

  839.         width: 2

  840.     - CLK_SOURCE_SLICE_MODE:

  841.         access: rw

  842.         description: Select clock source slice

  843.         lsb: 3

  844.         reset_value: '0'

  845.         width: 2

  846.     - QUALIFIER_MODE:

  847.         access: rw

  848.         description: Select qualifier mode

  849.         lsb: 5

  850.         reset_value: '0'

  851.         width: 2

  852.     - QUALIFIER_PIN_MODE:

  853.         access: rw

  854.         description: Select qualifier pin

  855.         lsb: 7

  856.         reset_value: '0'

  857.         width: 2

  858.     - QUALIFIER_SLICE_MODE:

  859.         access: rw

  860.         description: Select qualifier slice

  861.         lsb: 9

  862.         reset_value: '0'

  863.         width: 2

  864.     - CONCAT_ENABLE:

  865.         access: rw

  866.         description: Enable concatenation

  867.         lsb: 11

  868.         reset_value: '0'

  869.         width: 1

  870.     - CONCAT_ORDER:

  871.         access: rw

  872.         description: Select concatenation order

  873.         lsb: 12

  874.         reset_value: '0'

  875.         width: 2

  876. - SGPIO_MUX_CFG13:

  877.     fields: !!omap

  878.     - EXT_CLK_ENABLE:

  879.         access: rw

  880.         description: Select clock signal

  881.         lsb: 0

  882.         reset_value: '0'

  883.         width: 1

  884.     - CLK_SOURCE_PIN_MODE:

  885.         access: rw

  886.         description: Select source clock pin

  887.         lsb: 1

  888.         reset_value: '0'

  889.         width: 2

  890.     - CLK_SOURCE_SLICE_MODE:

  891.         access: rw

  892.         description: Select clock source slice

  893.         lsb: 3

  894.         reset_value: '0'

  895.         width: 2

  896.     - QUALIFIER_MODE:

  897.         access: rw

  898.         description: Select qualifier mode

  899.         lsb: 5

  900.         reset_value: '0'

  901.         width: 2

  902.     - QUALIFIER_PIN_MODE:

  903.         access: rw

  904.         description: Select qualifier pin

  905.         lsb: 7

  906.         reset_value: '0'

  907.         width: 2

  908.     - QUALIFIER_SLICE_MODE:

  909.         access: rw

  910.         description: Select qualifier slice

  911.         lsb: 9

  912.         reset_value: '0'

  913.         width: 2

  914.     - CONCAT_ENABLE:

  915.         access: rw

  916.         description: Enable concatenation

  917.         lsb: 11

  918.         reset_value: '0'

  919.         width: 1

  920.     - CONCAT_ORDER:

  921.         access: rw

  922.         description: Select concatenation order

  923.         lsb: 12

  924.         reset_value: '0'

  925.         width: 2

  926. - SGPIO_MUX_CFG14:

  927.     fields: !!omap

  928.     - EXT_CLK_ENABLE:

  929.         access: rw

  930.         description: Select clock signal

  931.         lsb: 0

  932.         reset_value: '0'

  933.         width: 1

  934.     - CLK_SOURCE_PIN_MODE:

  935.         access: rw

  936.         description: Select source clock pin

  937.         lsb: 1

  938.         reset_value: '0'

  939.         width: 2

  940.     - CLK_SOURCE_SLICE_MODE:

  941.         access: rw

  942.         description: Select clock source slice

  943.         lsb: 3

  944.         reset_value: '0'

  945.         width: 2

  946.     - QUALIFIER_MODE:

  947.         access: rw

  948.         description: Select qualifier mode

  949.         lsb: 5

  950.         reset_value: '0'

  951.         width: 2

  952.     - QUALIFIER_PIN_MODE:

  953.         access: rw

  954.         description: Select qualifier pin

  955.         lsb: 7

  956.         reset_value: '0'

  957.         width: 2

  958.     - QUALIFIER_SLICE_MODE:

  959.         access: rw

  960.         description: Select qualifier slice

  961.         lsb: 9

  962.         reset_value: '0'

  963.         width: 2

  964.     - CONCAT_ENABLE:

  965.         access: rw

  966.         description: Enable concatenation

  967.         lsb: 11

  968.         reset_value: '0'

  969.         width: 1

  970.     - CONCAT_ORDER:

  971.         access: rw

  972.         description: Select concatenation order

  973.         lsb: 12

  974.         reset_value: '0'

  975.         width: 2

  976. - SGPIO_MUX_CFG15:

  977.     fields: !!omap

  978.     - EXT_CLK_ENABLE:

  979.         access: rw

  980.         description: Select clock signal

  981.         lsb: 0

  982.         reset_value: '0'

  983.         width: 1

  984.     - CLK_SOURCE_PIN_MODE:

  985.         access: rw

  986.         description: Select source clock pin

  987.         lsb: 1

  988.         reset_value: '0'

  989.         width: 2

  990.     - CLK_SOURCE_SLICE_MODE:

  991.         access: rw

  992.         description: Select clock source slice

  993.         lsb: 3

  994.         reset_value: '0'

  995.         width: 2

  996.     - QUALIFIER_MODE:

  997.         access: rw

  998.         description: Select qualifier mode

  999.         lsb: 5

  1000.         reset_value: '0'

  1001.         width: 2

  1002.     - QUALIFIER_PIN_MODE:

  1003.         access: rw

  1004.         description: Select qualifier pin

  1005.         lsb: 7

  1006.         reset_value: '0'

  1007.         width: 2

  1008.     - QUALIFIER_SLICE_MODE:

  1009.         access: rw

  1010.         description: Select qualifier slice

  1011.         lsb: 9

  1012.         reset_value: '0'

  1013.         width: 2

  1014.     - CONCAT_ENABLE:

  1015.         access: rw

  1016.         description: Enable concatenation

  1017.         lsb: 11

  1018.         reset_value: '0'

  1019.         width: 1

  1020.     - CONCAT_ORDER:

  1021.         access: rw

  1022.         description: Select concatenation order

  1023.         lsb: 12

  1024.         reset_value: '0'

  1025.         width: 2

  1026. - SGPIO_SLICE_MUX_CFG0:

  1027.     fields: !!omap

  1028.     - MATCH_MODE:

  1029.         access: rw

  1030.         description: Match mode

  1031.         lsb: 0

  1032.         reset_value: '0'

  1033.         width: 1

  1034.     - CLK_CAPTURE_MODE:

  1035.         access: rw

  1036.         description: Capture clock mode

  1037.         lsb: 1

  1038.         reset_value: '0'

  1039.         width: 1

  1040.     - CLKGEN_MODE:

  1041.         access: rw

  1042.         description: Clock generation mode

  1043.         lsb: 2

  1044.         reset_value: '0'

  1045.         width: 1

  1046.     - INV_OUT_CLK:

  1047.         access: rw

  1048.         description: Invert output clock

  1049.         lsb: 3

  1050.         reset_value: '0'

  1051.         width: 1

  1052.     - DATA_CAPTURE_MODE:

  1053.         access: rw

  1054.         description: Condition for input bit match interrupt

  1055.         lsb: 4

  1056.         reset_value: '0'

  1057.         width: 2

  1058.     - PARALLEL_MODE:

  1059.         access: rw

  1060.         description: Parallel mode

  1061.         lsb: 6

  1062.         reset_value: '0'

  1063.         width: 2

  1064.     - INV_QUALIFIER:

  1065.         access: rw

  1066.         description: Inversion qualifier

  1067.         lsb: 8

  1068.         reset_value: '0'

  1069.         width: 1

  1070. - SGPIO_SLICE_MUX_CFG1:

  1071.     fields: !!omap

  1072.     - MATCH_MODE:

  1073.         access: rw

  1074.         description: Match mode

  1075.         lsb: 0

  1076.         reset_value: '0'

  1077.         width: 1

  1078.     - CLK_CAPTURE_MODE:

  1079.         access: rw

  1080.         description: Capture clock mode

  1081.         lsb: 1

  1082.         reset_value: '0'

  1083.         width: 1

  1084.     - CLKGEN_MODE:

  1085.         access: rw

  1086.         description: Clock generation mode

  1087.         lsb: 2

  1088.         reset_value: '0'

  1089.         width: 1

  1090.     - INV_OUT_CLK:

  1091.         access: rw

  1092.         description: Invert output clock

  1093.         lsb: 3

  1094.         reset_value: '0'

  1095.         width: 1

  1096.     - DATA_CAPTURE_MODE:

  1097.         access: rw

  1098.         description: Condition for input bit match interrupt

  1099.         lsb: 4

  1100.         reset_value: '0'

  1101.         width: 2

  1102.     - PARALLEL_MODE:

  1103.         access: rw

  1104.         description: Parallel mode

  1105.         lsb: 6

  1106.         reset_value: '0'

  1107.         width: 2

  1108.     - INV_QUALIFIER:

  1109.         access: rw

  1110.         description: Inversion qualifier

  1111.         lsb: 8

  1112.         reset_value: '0'

  1113.         width: 1

  1114. - SGPIO_SLICE_MUX_CFG2:

  1115.     fields: !!omap

  1116.     - MATCH_MODE:

  1117.         access: rw

  1118.         description: Match mode

  1119.         lsb: 0

  1120.         reset_value: '0'

  1121.         width: 1

  1122.     - CLK_CAPTURE_MODE:

  1123.         access: rw

  1124.         description: Capture clock mode

  1125.         lsb: 1

  1126.         reset_value: '0'

  1127.         width: 1

  1128.     - CLKGEN_MODE:

  1129.         access: rw

  1130.         description: Clock generation mode

  1131.         lsb: 2

  1132.         reset_value: '0'

  1133.         width: 1

  1134.     - INV_OUT_CLK:

  1135.         access: rw

  1136.         description: Invert output clock

  1137.         lsb: 3

  1138.         reset_value: '0'

  1139.         width: 1

  1140.     - DATA_CAPTURE_MODE:

  1141.         access: rw

  1142.         description: Condition for input bit match interrupt

  1143.         lsb: 4

  1144.         reset_value: '0'

  1145.         width: 2

  1146.     - PARALLEL_MODE:

  1147.         access: rw

  1148.         description: Parallel mode

  1149.         lsb: 6

  1150.         reset_value: '0'

  1151.         width: 2

  1152.     - INV_QUALIFIER:

  1153.         access: rw

  1154.         description: Inversion qualifier

  1155.         lsb: 8

  1156.         reset_value: '0'

  1157.         width: 1

  1158. - SGPIO_SLICE_MUX_CFG3:

  1159.     fields: !!omap

  1160.     - MATCH_MODE:

  1161.         access: rw

  1162.         description: Match mode

  1163.         lsb: 0

  1164.         reset_value: '0'

  1165.         width: 1

  1166.     - CLK_CAPTURE_MODE:

  1167.         access: rw

  1168.         description: Capture clock mode

  1169.         lsb: 1

  1170.         reset_value: '0'

  1171.         width: 1

  1172.     - CLKGEN_MODE:

  1173.         access: rw

  1174.         description: Clock generation mode

  1175.         lsb: 2

  1176.         reset_value: '0'

  1177.         width: 1

  1178.     - INV_OUT_CLK:

  1179.         access: rw

  1180.         description: Invert output clock

  1181.         lsb: 3

  1182.         reset_value: '0'

  1183.         width: 1

  1184.     - DATA_CAPTURE_MODE:

  1185.         access: rw

  1186.         description: Condition for input bit match interrupt

  1187.         lsb: 4

  1188.         reset_value: '0'

  1189.         width: 2

  1190.     - PARALLEL_MODE:

  1191.         access: rw

  1192.         description: Parallel mode

  1193.         lsb: 6

  1194.         reset_value: '0'

  1195.         width: 2

  1196.     - INV_QUALIFIER:

  1197.         access: rw

  1198.         description: Inversion qualifier

  1199.         lsb: 8

  1200.         reset_value: '0'

  1201.         width: 1

  1202. - SGPIO_SLICE_MUX_CFG4:

  1203.     fields: !!omap

  1204.     - MATCH_MODE:

  1205.         access: rw

  1206.         description: Match mode

  1207.         lsb: 0

  1208.         reset_value: '0'

  1209.         width: 1

  1210.     - CLK_CAPTURE_MODE:

  1211.         access: rw

  1212.         description: Capture clock mode

  1213.         lsb: 1

  1214.         reset_value: '0'

  1215.         width: 1

  1216.     - CLKGEN_MODE:

  1217.         access: rw

  1218.         description: Clock generation mode

  1219.         lsb: 2

  1220.         reset_value: '0'

  1221.         width: 1

  1222.     - INV_OUT_CLK:

  1223.         access: rw

  1224.         description: Invert output clock

  1225.         lsb: 3

  1226.         reset_value: '0'

  1227.         width: 1

  1228.     - DATA_CAPTURE_MODE:

  1229.         access: rw

  1230.         description: Condition for input bit match interrupt

  1231.         lsb: 4

  1232.         reset_value: '0'

  1233.         width: 2

  1234.     - PARALLEL_MODE:

  1235.         access: rw

  1236.         description: Parallel mode

  1237.         lsb: 6

  1238.         reset_value: '0'

  1239.         width: 2

  1240.     - INV_QUALIFIER:

  1241.         access: rw

  1242.         description: Inversion qualifier

  1243.         lsb: 8

  1244.         reset_value: '0'

  1245.         width: 1

  1246. - SGPIO_SLICE_MUX_CFG5:

  1247.     fields: !!omap

  1248.     - MATCH_MODE:

  1249.         access: rw

  1250.         description: Match mode

  1251.         lsb: 0

  1252.         reset_value: '0'

  1253.         width: 1

  1254.     - CLK_CAPTURE_MODE:

  1255.         access: rw

  1256.         description: Capture clock mode

  1257.         lsb: 1

  1258.         reset_value: '0'

  1259.         width: 1

  1260.     - CLKGEN_MODE:

  1261.         access: rw

  1262.         description: Clock generation mode

  1263.         lsb: 2

  1264.         reset_value: '0'

  1265.         width: 1

  1266.     - INV_OUT_CLK:

  1267.         access: rw

  1268.         description: Invert output clock

  1269.         lsb: 3

  1270.         reset_value: '0'

  1271.         width: 1

  1272.     - DATA_CAPTURE_MODE:

  1273.         access: rw

  1274.         description: Condition for input bit match interrupt

  1275.         lsb: 4

  1276.         reset_value: '0'

  1277.         width: 2

  1278.     - PARALLEL_MODE:

  1279.         access: rw

  1280.         description: Parallel mode

  1281.         lsb: 6

  1282.         reset_value: '0'

  1283.         width: 2

  1284.     - INV_QUALIFIER:

  1285.         access: rw

  1286.         description: Inversion qualifier

  1287.         lsb: 8

  1288.         reset_value: '0'

  1289.         width: 1

  1290. - SGPIO_SLICE_MUX_CFG6:

  1291.     fields: !!omap

  1292.     - MATCH_MODE:

  1293.         access: rw

  1294.         description: Match mode

  1295.         lsb: 0

  1296.         reset_value: '0'

  1297.         width: 1

  1298.     - CLK_CAPTURE_MODE:

  1299.         access: rw

  1300.         description: Capture clock mode

  1301.         lsb: 1

  1302.         reset_value: '0'

  1303.         width: 1

  1304.     - CLKGEN_MODE:

  1305.         access: rw

  1306.         description: Clock generation mode

  1307.         lsb: 2

  1308.         reset_value: '0'

  1309.         width: 1

  1310.     - INV_OUT_CLK:

  1311.         access: rw

  1312.         description: Invert output clock

  1313.         lsb: 3

  1314.         reset_value: '0'

  1315.         width: 1

  1316.     - DATA_CAPTURE_MODE:

  1317.         access: rw

  1318.         description: Condition for input bit match interrupt

  1319.         lsb: 4

  1320.         reset_value: '0'

  1321.         width: 2

  1322.     - PARALLEL_MODE:

  1323.         access: rw

  1324.         description: Parallel mode

  1325.         lsb: 6

  1326.         reset_value: '0'

  1327.         width: 2

  1328.     - INV_QUALIFIER:

  1329.         access: rw

  1330.         description: Inversion qualifier

  1331.         lsb: 8

  1332.         reset_value: '0'

  1333.         width: 1

  1334. - SGPIO_SLICE_MUX_CFG7:

  1335.     fields: !!omap

  1336.     - MATCH_MODE:

  1337.         access: rw

  1338.         description: Match mode

  1339.         lsb: 0

  1340.         reset_value: '0'

  1341.         width: 1

  1342.     - CLK_CAPTURE_MODE:

  1343.         access: rw

  1344.         description: Capture clock mode

  1345.         lsb: 1

  1346.         reset_value: '0'

  1347.         width: 1

  1348.     - CLKGEN_MODE:

  1349.         access: rw

  1350.         description: Clock generation mode

  1351.         lsb: 2

  1352.         reset_value: '0'

  1353.         width: 1

  1354.     - INV_OUT_CLK:

  1355.         access: rw

  1356.         description: Invert output clock

  1357.         lsb: 3

  1358.         reset_value: '0'

  1359.         width: 1

  1360.     - DATA_CAPTURE_MODE:

  1361.         access: rw

  1362.         description: Condition for input bit match interrupt

  1363.         lsb: 4

  1364.         reset_value: '0'

  1365.         width: 2

  1366.     - PARALLEL_MODE:

  1367.         access: rw

  1368.         description: Parallel mode

  1369.         lsb: 6

  1370.         reset_value: '0'

  1371.         width: 2

  1372.     - INV_QUALIFIER:

  1373.         access: rw

  1374.         description: Inversion qualifier

  1375.         lsb: 8

  1376.         reset_value: '0'

  1377.         width: 1

  1378. - SGPIO_SLICE_MUX_CFG8:

  1379.     fields: !!omap

  1380.     - MATCH_MODE:

  1381.         access: rw

  1382.         description: Match mode

  1383.         lsb: 0

  1384.         reset_value: '0'

  1385.         width: 1

  1386.     - CLK_CAPTURE_MODE:

  1387.         access: rw

  1388.         description: Capture clock mode

  1389.         lsb: 1

  1390.         reset_value: '0'

  1391.         width: 1

  1392.     - CLKGEN_MODE:

  1393.         access: rw

  1394.         description: Clock generation mode

  1395.         lsb: 2

  1396.         reset_value: '0'

  1397.         width: 1

  1398.     - INV_OUT_CLK:

  1399.         access: rw

  1400.         description: Invert output clock

  1401.         lsb: 3

  1402.         reset_value: '0'

  1403.         width: 1

  1404.     - DATA_CAPTURE_MODE:

  1405.         access: rw

  1406.         description: Condition for input bit match interrupt

  1407.         lsb: 4

  1408.         reset_value: '0'

  1409.         width: 2

  1410.     - PARALLEL_MODE:

  1411.         access: rw

  1412.         description: Parallel mode

  1413.         lsb: 6

  1414.         reset_value: '0'

  1415.         width: 2

  1416.     - INV_QUALIFIER:

  1417.         access: rw

  1418.         description: Inversion qualifier

  1419.         lsb: 8

  1420.         reset_value: '0'

  1421.         width: 1

  1422. - SGPIO_SLICE_MUX_CFG9:

  1423.     fields: !!omap

  1424.     - MATCH_MODE:

  1425.         access: rw

  1426.         description: Match mode

  1427.         lsb: 0

  1428.         reset_value: '0'

  1429.         width: 1

  1430.     - CLK_CAPTURE_MODE:

  1431.         access: rw

  1432.         description: Capture clock mode

  1433.         lsb: 1

  1434.         reset_value: '0'

  1435.         width: 1

  1436.     - CLKGEN_MODE:

  1437.         access: rw

  1438.         description: Clock generation mode

  1439.         lsb: 2

  1440.         reset_value: '0'

  1441.         width: 1

  1442.     - INV_OUT_CLK:

  1443.         access: rw

  1444.         description: Invert output clock

  1445.         lsb: 3

  1446.         reset_value: '0'

  1447.         width: 1

  1448.     - DATA_CAPTURE_MODE:

  1449.         access: rw

  1450.         description: Condition for input bit match interrupt

  1451.         lsb: 4

  1452.         reset_value: '0'

  1453.         width: 2

  1454.     - PARALLEL_MODE:

  1455.         access: rw

  1456.         description: Parallel mode

  1457.         lsb: 6

  1458.         reset_value: '0'

  1459.         width: 2

  1460.     - INV_QUALIFIER:

  1461.         access: rw

  1462.         description: Inversion qualifier

  1463.         lsb: 8

  1464.         reset_value: '0'

  1465.         width: 1

  1466. - SGPIO_SLICE_MUX_CFG10:

  1467.     fields: !!omap

  1468.     - MATCH_MODE:

  1469.         access: rw

  1470.         description: Match mode

  1471.         lsb: 0

  1472.         reset_value: '0'

  1473.         width: 1

  1474.     - CLK_CAPTURE_MODE:

  1475.         access: rw

  1476.         description: Capture clock mode

  1477.         lsb: 1

  1478.         reset_value: '0'

  1479.         width: 1

  1480.     - CLKGEN_MODE:

  1481.         access: rw

  1482.         description: Clock generation mode

  1483.         lsb: 2

  1484.         reset_value: '0'

  1485.         width: 1

  1486.     - INV_OUT_CLK:

  1487.         access: rw

  1488.         description: Invert output clock

  1489.         lsb: 3

  1490.         reset_value: '0'

  1491.         width: 1

  1492.     - DATA_CAPTURE_MODE:

  1493.         access: rw

  1494.         description: Condition for input bit match interrupt

  1495.         lsb: 4

  1496.         reset_value: '0'

  1497.         width: 2

  1498.     - PARALLEL_MODE:

  1499.         access: rw

  1500.         description: Parallel mode

  1501.         lsb: 6

  1502.         reset_value: '0'

  1503.         width: 2

  1504.     - INV_QUALIFIER:

  1505.         access: rw

  1506.         description: Inversion qualifier

  1507.         lsb: 8

  1508.         reset_value: '0'

  1509.         width: 1

  1510. - SGPIO_SLICE_MUX_CFG11:

  1511.     fields: !!omap

  1512.     - MATCH_MODE:

  1513.         access: rw

  1514.         description: Match mode

  1515.         lsb: 0

  1516.         reset_value: '0'

  1517.         width: 1

  1518.     - CLK_CAPTURE_MODE:

  1519.         access: rw

  1520.         description: Capture clock mode

  1521.         lsb: 1

  1522.         reset_value: '0'

  1523.         width: 1

  1524.     - CLKGEN_MODE:

  1525.         access: rw

  1526.         description: Clock generation mode

  1527.         lsb: 2

  1528.         reset_value: '0'

  1529.         width: 1

  1530.     - INV_OUT_CLK:

  1531.         access: rw

  1532.         description: Invert output clock

  1533.         lsb: 3

  1534.         reset_value: '0'

  1535.         width: 1

  1536.     - DATA_CAPTURE_MODE:

  1537.         access: rw

  1538.         description: Condition for input bit match interrupt

  1539.         lsb: 4

  1540.         reset_value: '0'

  1541.         width: 2

  1542.     - PARALLEL_MODE:

  1543.         access: rw

  1544.         description: Parallel mode

  1545.         lsb: 6

  1546.         reset_value: '0'

  1547.         width: 2

  1548.     - INV_QUALIFIER:

  1549.         access: rw

  1550.         description: Inversion qualifier

  1551.         lsb: 8

  1552.         reset_value: '0'

  1553.         width: 1

  1554. - SGPIO_SLICE_MUX_CFG12:

  1555.     fields: !!omap

  1556.     - MATCH_MODE:

  1557.         access: rw

  1558.         description: Match mode

  1559.         lsb: 0

  1560.         reset_value: '0'

  1561.         width: 1

  1562.     - CLK_CAPTURE_MODE:

  1563.         access: rw

  1564.         description: Capture clock mode

  1565.         lsb: 1

  1566.         reset_value: '0'

  1567.         width: 1

  1568.     - CLKGEN_MODE:

  1569.         access: rw

  1570.         description: Clock generation mode

  1571.         lsb: 2

  1572.         reset_value: '0'

  1573.         width: 1

  1574.     - INV_OUT_CLK:

  1575.         access: rw

  1576.         description: Invert output clock

  1577.         lsb: 3

  1578.         reset_value: '0'

  1579.         width: 1

  1580.     - DATA_CAPTURE_MODE:

  1581.         access: rw

  1582.         description: Condition for input bit match interrupt

  1583.         lsb: 4

  1584.         reset_value: '0'

  1585.         width: 2

  1586.     - PARALLEL_MODE:

  1587.         access: rw

  1588.         description: Parallel mode

  1589.         lsb: 6

  1590.         reset_value: '0'

  1591.         width: 2

  1592.     - INV_QUALIFIER:

  1593.         access: rw

  1594.         description: Inversion qualifier

  1595.         lsb: 8

  1596.         reset_value: '0'

  1597.         width: 1

  1598. - SGPIO_SLICE_MUX_CFG13:

  1599.     fields: !!omap

  1600.     - MATCH_MODE:

  1601.         access: rw

  1602.         description: Match mode

  1603.         lsb: 0

  1604.         reset_value: '0'

  1605.         width: 1

  1606.     - CLK_CAPTURE_MODE:

  1607.         access: rw

  1608.         description: Capture clock mode

  1609.         lsb: 1

  1610.         reset_value: '0'

  1611.         width: 1

  1612.     - CLKGEN_MODE:

  1613.         access: rw

  1614.         description: Clock generation mode

  1615.         lsb: 2

  1616.         reset_value: '0'

  1617.         width: 1

  1618.     - INV_OUT_CLK:

  1619.         access: rw

  1620.         description: Invert output clock

  1621.         lsb: 3

  1622.         reset_value: '0'

  1623.         width: 1

  1624.     - DATA_CAPTURE_MODE:

  1625.         access: rw

  1626.         description: Condition for input bit match interrupt

  1627.         lsb: 4

  1628.         reset_value: '0'

  1629.         width: 2

  1630.     - PARALLEL_MODE:

  1631.         access: rw

  1632.         description: Parallel mode

  1633.         lsb: 6

  1634.         reset_value: '0'

  1635.         width: 2

  1636.     - INV_QUALIFIER:

  1637.         access: rw

  1638.         description: Inversion qualifier

  1639.         lsb: 8

  1640.         reset_value: '0'

  1641.         width: 1

  1642. - SGPIO_SLICE_MUX_CFG14:

  1643.     fields: !!omap

  1644.     - MATCH_MODE:

  1645.         access: rw

  1646.         description: Match mode

  1647.         lsb: 0

  1648.         reset_value: '0'

  1649.         width: 1

  1650.     - CLK_CAPTURE_MODE:

  1651.         access: rw

  1652.         description: Capture clock mode

  1653.         lsb: 1

  1654.         reset_value: '0'

  1655.         width: 1

  1656.     - CLKGEN_MODE:

  1657.         access: rw

  1658.         description: Clock generation mode

  1659.         lsb: 2

  1660.         reset_value: '0'

  1661.         width: 1

  1662.     - INV_OUT_CLK:

  1663.         access: rw

  1664.         description: Invert output clock

  1665.         lsb: 3

  1666.         reset_value: '0'

  1667.         width: 1

  1668.     - DATA_CAPTURE_MODE:

  1669.         access: rw

  1670.         description: Condition for input bit match interrupt

  1671.         lsb: 4

  1672.         reset_value: '0'

  1673.         width: 2

  1674.     - PARALLEL_MODE:

  1675.         access: rw

  1676.         description: Parallel mode

  1677.         lsb: 6

  1678.         reset_value: '0'

  1679.         width: 2

  1680.     - INV_QUALIFIER:

  1681.         access: rw

  1682.         description: Inversion qualifier

  1683.         lsb: 8

  1684.         reset_value: '0'

  1685.         width: 1

  1686. - SGPIO_SLICE_MUX_CFG15:

  1687.     fields: !!omap

  1688.     - MATCH_MODE:

  1689.         access: rw

  1690.         description: Match mode

  1691.         lsb: 0

  1692.         reset_value: '0'

  1693.         width: 1

  1694.     - CLK_CAPTURE_MODE:

  1695.         access: rw

  1696.         description: Capture clock mode

  1697.         lsb: 1

  1698.         reset_value: '0'

  1699.         width: 1

  1700.     - CLKGEN_MODE:

  1701.         access: rw

  1702.         description: Clock generation mode

  1703.         lsb: 2

  1704.         reset_value: '0'

  1705.         width: 1

  1706.     - INV_OUT_CLK:

  1707.         access: rw

  1708.         description: Invert output clock

  1709.         lsb: 3

  1710.         reset_value: '0'

  1711.         width: 1

  1712.     - DATA_CAPTURE_MODE:

  1713.         access: rw

  1714.         description: Condition for input bit match interrupt

  1715.         lsb: 4

  1716.         reset_value: '0'

  1717.         width: 2

  1718.     - PARALLEL_MODE:

  1719.         access: rw

  1720.         description: Parallel mode

  1721.         lsb: 6

  1722.         reset_value: '0'

  1723.         width: 2

  1724.     - INV_QUALIFIER:

  1725.         access: rw

  1726.         description: Inversion qualifier

  1727.         lsb: 8

  1728.         reset_value: '0'

  1729.         width: 1

  1730. - SGPIO_POS0:

  1731.     fields: !!omap

  1732.     - POS:

  1733.         access: rw

  1734.         description: Each time COUNT reaches 0x0 POS counts down

  1735.         lsb: 0

  1736.         reset_value: '0'

  1737.         width: 8

  1738.     - POS_RESET:

  1739.         access: rw

  1740.         description: Reload value for POS after POS reaches 0x0

  1741.         lsb: 8

  1742.         reset_value: '0'

  1743.         width: 8

  1744. - SGPIO_POS1:

  1745.     fields: !!omap

  1746.     - POS:

  1747.         access: rw

  1748.         description: Each time COUNT reaches 0x0 POS counts down

  1749.         lsb: 0

  1750.         reset_value: '0'

  1751.         width: 8

  1752.     - POS_RESET:

  1753.         access: rw

  1754.         description: Reload value for POS after POS reaches 0x0

  1755.         lsb: 8

  1756.         reset_value: '0'

  1757.         width: 8

  1758. - SGPIO_POS2:

  1759.     fields: !!omap

  1760.     - POS:

  1761.         access: rw

  1762.         description: Each time COUNT reaches 0x0 POS counts down

  1763.         lsb: 0

  1764.         reset_value: '0'

  1765.         width: 8

  1766.     - POS_RESET:

  1767.         access: rw

  1768.         description: Reload value for POS after POS reaches 0x0

  1769.         lsb: 8

  1770.         reset_value: '0'

  1771.         width: 8

  1772. - SGPIO_POS3:

  1773.     fields: !!omap

  1774.     - POS:

  1775.         access: rw

  1776.         description: Each time COUNT reaches 0x0 POS counts down

  1777.         lsb: 0

  1778.         reset_value: '0'

  1779.         width: 8

  1780.     - POS_RESET:

  1781.         access: rw

  1782.         description: Reload value for POS after POS reaches 0x0

  1783.         lsb: 8

  1784.         reset_value: '0'

  1785.         width: 8

  1786. - SGPIO_POS4:

  1787.     fields: !!omap

  1788.     - POS:

  1789.         access: rw

  1790.         description: Each time COUNT reaches 0x0 POS counts down

  1791.         lsb: 0

  1792.         reset_value: '0'

  1793.         width: 8

  1794.     - POS_RESET:

  1795.         access: rw

  1796.         description: Reload value for POS after POS reaches 0x0

  1797.         lsb: 8

  1798.         reset_value: '0'

  1799.         width: 8

  1800. - SGPIO_POS5:

  1801.     fields: !!omap

  1802.     - POS:

  1803.         access: rw

  1804.         description: Each time COUNT reaches 0x0 POS counts down

  1805.         lsb: 0

  1806.         reset_value: '0'

  1807.         width: 8

  1808.     - POS_RESET:

  1809.         access: rw

  1810.         description: Reload value for POS after POS reaches 0x0

  1811.         lsb: 8

  1812.         reset_value: '0'

  1813.         width: 8

  1814. - SGPIO_POS6:

  1815.     fields: !!omap

  1816.     - POS:

  1817.         access: rw

  1818.         description: Each time COUNT reaches 0x0 POS counts down

  1819.         lsb: 0

  1820.         reset_value: '0'

  1821.         width: 8

  1822.     - POS_RESET:

  1823.         access: rw

  1824.         description: Reload value for POS after POS reaches 0x0

  1825.         lsb: 8

  1826.         reset_value: '0'

  1827.         width: 8

  1828. - SGPIO_POS7:

  1829.     fields: !!omap

  1830.     - POS:

  1831.         access: rw

  1832.         description: Each time COUNT reaches 0x0 POS counts down

  1833.         lsb: 0

  1834.         reset_value: '0'

  1835.         width: 8

  1836.     - POS_RESET:

  1837.         access: rw

  1838.         description: Reload value for POS after POS reaches 0x0

  1839.         lsb: 8

  1840.         reset_value: '0'

  1841.         width: 8

  1842. - SGPIO_POS8:

  1843.     fields: !!omap

  1844.     - POS:

  1845.         access: rw

  1846.         description: Each time COUNT reaches 0x0 POS counts down

  1847.         lsb: 0

  1848.         reset_value: '0'

  1849.         width: 8

  1850.     - POS_RESET:

  1851.         access: rw

  1852.         description: Reload value for POS after POS reaches 0x0

  1853.         lsb: 8

  1854.         reset_value: '0'

  1855.         width: 8

  1856. - SGPIO_POS9:

  1857.     fields: !!omap

  1858.     - POS:

  1859.         access: rw

  1860.         description: Each time COUNT reaches 0x0 POS counts down

  1861.         lsb: 0

  1862.         reset_value: '0'

  1863.         width: 8

  1864.     - POS_RESET:

  1865.         access: rw

  1866.         description: Reload value for POS after POS reaches 0x0

  1867.         lsb: 8

  1868.         reset_value: '0'

  1869.         width: 8

  1870. - SGPIO_POS10:

  1871.     fields: !!omap

  1872.     - POS:

  1873.         access: rw

  1874.         description: Each time COUNT reaches 0x0 POS counts down

  1875.         lsb: 0

  1876.         reset_value: '0'

  1877.         width: 8

  1878.     - POS_RESET:

  1879.         access: rw

  1880.         description: Reload value for POS after POS reaches 0x0

  1881.         lsb: 8

  1882.         reset_value: '0'

  1883.         width: 8

  1884. - SGPIO_POS11:

  1885.     fields: !!omap

  1886.     - POS:

  1887.         access: rw

  1888.         description: Each time COUNT reaches 0x0 POS counts down

  1889.         lsb: 0

  1890.         reset_value: '0'

  1891.         width: 8

  1892.     - POS_RESET:

  1893.         access: rw

  1894.         description: Reload value for POS after POS reaches 0x0

  1895.         lsb: 8

  1896.         reset_value: '0'

  1897.         width: 8

  1898. - SGPIO_POS12:

  1899.     fields: !!omap

  1900.     - POS:

  1901.         access: rw

  1902.         description: Each time COUNT reaches 0x0 POS counts down

  1903.         lsb: 0

  1904.         reset_value: '0'

  1905.         width: 8

  1906.     - POS_RESET:

  1907.         access: rw

  1908.         description: Reload value for POS after POS reaches 0x0

  1909.         lsb: 8

  1910.         reset_value: '0'

  1911.         width: 8

  1912. - SGPIO_POS13:

  1913.     fields: !!omap

  1914.     - POS:

  1915.         access: rw

  1916.         description: Each time COUNT reaches 0x0 POS counts down

  1917.         lsb: 0

  1918.         reset_value: '0'

  1919.         width: 8

  1920.     - POS_RESET:

  1921.         access: rw

  1922.         description: Reload value for POS after POS reaches 0x0

  1923.         lsb: 8

  1924.         reset_value: '0'

  1925.         width: 8

  1926. - SGPIO_POS14:

  1927.     fields: !!omap

  1928.     - POS:

  1929.         access: rw

  1930.         description: Each time COUNT reaches 0x0 POS counts down

  1931.         lsb: 0

  1932.         reset_value: '0'

  1933.         width: 8

  1934.     - POS_RESET:

  1935.         access: rw

  1936.         description: Reload value for POS after POS reaches 0x0

  1937.         lsb: 8

  1938.         reset_value: '0'

  1939.         width: 8

  1940. - SGPIO_POS15:

  1941.     fields: !!omap

  1942.     - POS:

  1943.         access: rw

  1944.         description: Each time COUNT reaches 0x0 POS counts down

  1945.         lsb: 0

  1946.         reset_value: '0'

  1947.         width: 8

  1948.     - POS_RESET:

  1949.         access: rw

  1950.         description: Reload value for POS after POS reaches 0x0

  1951.         lsb: 8

  1952.         reset_value: '0'

  1953.         width: 8