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m4_init/3rd/libopencm3/scripts/data/lpc43xx/ssp.yaml

446 řádky
11 KiB
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  1. !!omap

  2. - SSP0_CR0:

  3.     fields: !!omap

  4.     - DSS:

  5.         access: rw

  6.         description: Data Size Select

  7.         lsb: 0

  8.         reset_value: '0'

  9.         width: 4

  10.     - FRF:

  11.         access: rw

  12.         description: Frame Format

  13.         lsb: 4

  14.         reset_value: '0'

  15.         width: 2

  16.     - CPOL:

  17.         access: rw

  18.         description: Clock Out Polarity

  19.         lsb: 6

  20.         reset_value: '0'

  21.         width: 1

  22.     - CPHA:

  23.         access: rw

  24.         description: Clock Out Phase

  25.         lsb: 7

  26.         reset_value: '0'

  27.         width: 1

  28.     - SCR:

  29.         access: rw

  30.         description: Serial Clock Rate

  31.         lsb: 8

  32.         reset_value: '0'

  33.         width: 8

  34. - SSP1_CR0:

  35.     fields: !!omap

  36.     - DSS:

  37.         access: rw

  38.         description: Data Size Select

  39.         lsb: 0

  40.         reset_value: '0'

  41.         width: 4

  42.     - FRF:

  43.         access: rw

  44.         description: Frame Format

  45.         lsb: 4

  46.         reset_value: '0'

  47.         width: 2

  48.     - CPOL:

  49.         access: rw

  50.         description: Clock Out Polarity

  51.         lsb: 6

  52.         reset_value: '0'

  53.         width: 1

  54.     - CPHA:

  55.         access: rw

  56.         description: Clock Out Phase

  57.         lsb: 7

  58.         reset_value: '0'

  59.         width: 1

  60.     - SCR:

  61.         access: rw

  62.         description: Serial Clock Rate

  63.         lsb: 8

  64.         reset_value: '0'

  65.         width: 8

  66. - SSP0_CR1:

  67.     fields: !!omap

  68.     - LBM:

  69.         access: rw

  70.         description: Loop Back Mode

  71.         lsb: 0

  72.         reset_value: '0'

  73.         width: 1

  74.     - SSE:

  75.         access: rw

  76.         description: SSP Enable

  77.         lsb: 1

  78.         reset_value: '0'

  79.         width: 1

  80.     - MS:

  81.         access: rw

  82.         description: Master/Slave Mode

  83.         lsb: 2

  84.         reset_value: '0'

  85.         width: 1

  86.     - SOD:

  87.         access: rw

  88.         description: Slave Output Disable

  89.         lsb: 3

  90.         reset_value: '0'

  91.         width: 1

  92. - SSP1_CR1:

  93.     fields: !!omap

  94.     - SSE:

  95.         access: rw

  96.         description: SSP Enable

  97.         lsb: 1

  98.         reset_value: '0'

  99.         width: 1

  100.     - MS:

  101.         access: rw

  102.         description: Master/Slave Mode

  103.         lsb: 2

  104.         reset_value: '0'

  105.         width: 1

  106.     - SOD:

  107.         access: rw

  108.         description: Slave Output Disable

  109.         lsb: 3

  110.         reset_value: '0'

  111.         width: 1

  112. - SSP0_DR:

  113.     fields: !!omap

  114.     - DATA:

  115.         access: rw

  116.         description: Software can write data to be transmitted to this register, and

  117.           read data that has been

  118.         lsb: 0

  119.         reset_value: '0'

  120.         width: 16

  121. - SSP1_DR:

  122.     fields: !!omap

  123.     - DATA:

  124.         access: rw

  125.         description: Software can write data to be transmitted to this register, and

  126.           read data that has been

  127.         lsb: 0

  128.         reset_value: '0'

  129.         width: 16

  130. - SSP0_SR:

  131.     fields: !!omap

  132.     - TFE:

  133.         access: r

  134.         description: Transmit FIFO Empty

  135.         lsb: 0

  136.         reset_value: '1'

  137.         width: 1

  138.     - TNF:

  139.         access: r

  140.         description: Transmit FIFO Not Full

  141.         lsb: 1

  142.         reset_value: '1'

  143.         width: 1

  144.     - RNE:

  145.         access: r

  146.         description: Receive FIFO Not Empty

  147.         lsb: 2

  148.         reset_value: '0'

  149.         width: 1

  150.     - RFF:

  151.         access: r

  152.         description: Receive FIFO Full

  153.         lsb: 3

  154.         reset_value: '0'

  155.         width: 1

  156.     - BSY:

  157.         access: r

  158.         description: Busy.

  159.         lsb: 4

  160.         reset_value: '0'

  161.         width: 1

  162. - SSP1_SR:

  163.     fields: !!omap

  164.     - TFE:

  165.         access: r

  166.         description: Transmit FIFO Empty

  167.         lsb: 0

  168.         reset_value: '1'

  169.         width: 1

  170.     - TNF:

  171.         access: r

  172.         description: Transmit FIFO Not Full

  173.         lsb: 1

  174.         reset_value: '1'

  175.         width: 1

  176.     - RNE:

  177.         access: r

  178.         description: Receive FIFO Not Empty

  179.         lsb: 2

  180.         reset_value: '0'

  181.         width: 1

  182.     - RFF:

  183.         access: r

  184.         description: Receive FIFO Full

  185.         lsb: 3

  186.         reset_value: '0'

  187.         width: 1

  188.     - BSY:

  189.         access: r

  190.         description: Busy.

  191.         lsb: 4

  192.         reset_value: '0'

  193.         width: 1

  194. - SSP0_CPSR:

  195.     fields: !!omap

  196.     - CPSDVSR:

  197.         access: rw

  198.         description: SSP Clock Prescale Register

  199.         lsb: 0

  200.         reset_value: '0'

  201.         width: 8

  202. - SSP1_CPSR:

  203.     fields: !!omap

  204.     - CPSDVSR:

  205.         access: rw

  206.         description: SSP Clock Prescale Register

  207.         lsb: 0

  208.         reset_value: '0'

  209.         width: 8

  210. - SSP0_IMSC:

  211.     fields: !!omap

  212.     - RORIM:

  213.         access: rw

  214.         description: Software should set this bit to enable interrupt when a Receive

  215.           Overrun occurs

  216.         lsb: 0

  217.         reset_value: '0'

  218.         width: 1

  219.     - RTIM:

  220.         access: rw

  221.         description: Software should set this bit to enable interrupt when a Receive

  222.           Time-out condition occurs

  223.         lsb: 1

  224.         reset_value: '0'

  225.         width: 1

  226.     - RXIM:

  227.         access: rw

  228.         description: Software should set this bit to enable interrupt when the Rx

  229.           FIFO is at least half full

  230.         lsb: 2

  231.         reset_value: '0'

  232.         width: 1

  233.     - TXIM:

  234.         access: rw

  235.         description: Software should set this bit to enable interrupt when the Tx

  236.           FIFO is at least half empty

  237.         lsb: 3

  238.         reset_value: '0'

  239.         width: 1

  240. - SSP1_IMSC:

  241.     fields: !!omap

  242.     - RORIM:

  243.         access: rw

  244.         description: Software should set this bit to enable interrupt when a Receive

  245.           Overrun occurs

  246.         lsb: 0

  247.         reset_value: '0'

  248.         width: 1

  249.     - RTIM:

  250.         access: rw

  251.         description: Software should set this bit to enable interrupt when a Receive

  252.           Time-out condition occurs

  253.         lsb: 1

  254.         reset_value: '0'

  255.         width: 1

  256.     - RXIM:

  257.         access: rw

  258.         description: Software should set this bit to enable interrupt when the Rx

  259.           FIFO is at least half full

  260.         lsb: 2

  261.         reset_value: '0'

  262.         width: 1

  263.     - TXIM:

  264.         access: rw

  265.         description: Software should set this bit to enable interrupt when the Tx

  266.           FIFO is at least half empty

  267.         lsb: 3

  268.         reset_value: '0'

  269.         width: 1

  270. - SSP0_RIS:

  271.     fields: !!omap

  272.     - RORRIS:

  273.         access: r

  274.         description: This bit is 1 if another frame was completely received while

  275.           the RxFIFO was full

  276.         lsb: 0

  277.         reset_value: '0'

  278.         width: 1

  279.     - RTRIS:

  280.         access: r

  281.         description: This bit is 1 if the Rx FIFO is not empty, and has not been read

  282.           for a time-out period

  283.         lsb: 1

  284.         reset_value: '0'

  285.         width: 1

  286.     - RXRIS:

  287.         access: r

  288.         description: This bit is 1 if the Rx FIFO is at least half full

  289.         lsb: 2

  290.         reset_value: '0'

  291.         width: 1

  292.     - TXRIS:

  293.         access: r

  294.         description: This bit is 1 if the Tx FIFO is at least half empty

  295.         lsb: 3

  296.         reset_value: '1'

  297.         width: 1

  298. - SSP1_RIS:

  299.     fields: !!omap

  300.     - RORRIS:

  301.         access: r

  302.         description: This bit is 1 if another frame was completely received while

  303.           the RxFIFO was full

  304.         lsb: 0

  305.         reset_value: '0'

  306.         width: 1

  307.     - RTRIS:

  308.         access: r

  309.         description: This bit is 1 if the Rx FIFO is not empty, and has not been read

  310.           for a time-out period

  311.         lsb: 1

  312.         reset_value: '0'

  313.         width: 1

  314.     - RXRIS:

  315.         access: r

  316.         description: This bit is 1 if the Rx FIFO is at least half full

  317.         lsb: 2

  318.         reset_value: '0'

  319.         width: 1

  320.     - TXRIS:

  321.         access: r

  322.         description: This bit is 1 if the Tx FIFO is at least half empty

  323.         lsb: 3

  324.         reset_value: '1'

  325.         width: 1

  326. - SSP0_MIS:

  327.     fields: !!omap

  328.     - RORMIS:

  329.         access: r

  330.         description: This bit is 1 if another frame was completely received while

  331.           the RxFIFO was full, and this interrupt is enabled

  332.         lsb: 0

  333.         reset_value: '0'

  334.         width: 1

  335.     - RTMIS:

  336.         access: r

  337.         description: This bit is 1 if the Rx FIFO is not empty, has not been read

  338.           for a time-out period, and this interrupt is enabled

  339.         lsb: 1

  340.         reset_value: '0'

  341.         width: 1

  342.     - RXMIS:

  343.         access: r

  344.         description: This bit is 1 if the Rx FIFO is at least half full, and this

  345.           interrupt is enabled

  346.         lsb: 2

  347.         reset_value: '0'

  348.         width: 1

  349.     - TXMIS:

  350.         access: r

  351.         description: This bit is 1 if the Tx FIFO is at least half empty, and this

  352.           interrupt is enabled

  353.         lsb: 3

  354.         reset_value: '0'

  355.         width: 1

  356. - SSP1_MIS:

  357.     fields: !!omap

  358.     - RORMIS:

  359.         access: r

  360.         description: This bit is 1 if another frame was completely received while

  361.           the RxFIFO was full, and this interrupt is enabled

  362.         lsb: 0

  363.         reset_value: '0'

  364.         width: 1

  365.     - RTMIS:

  366.         access: r

  367.         description: This bit is 1 if the Rx FIFO is not empty, has not been read

  368.           for a time-out period, and this interrupt is enabled

  369.         lsb: 1

  370.         reset_value: '0'

  371.         width: 1

  372.     - RXMIS:

  373.         access: r

  374.         description: This bit is 1 if the Rx FIFO is at least half full, and this

  375.           interrupt is enabled

  376.         lsb: 2

  377.         reset_value: '0'

  378.         width: 1

  379.     - TXMIS:

  380.         access: r

  381.         description: This bit is 1 if the Tx FIFO is at least half empty, and this

  382.           interrupt is enabled

  383.         lsb: 3

  384.         reset_value: '0'

  385.         width: 1

  386. - SSP0_ICR:

  387.     fields: !!omap

  388.     - RORIC:

  389.         access: w

  390.         description: Writing a 1 to this bit clears the 'frame was received when RxFIFO

  391.           was full' interrupt

  392.         lsb: 0

  393.         reset_value: ''

  394.         width: 1

  395.     - RTIC:

  396.         access: w

  397.         description: Writing a 1 to this bit clears the Rx FIFO was not empty and

  398.           has not been read for a time-out period interrupt

  399.         lsb: 1

  400.         reset_value: ''

  401.         width: 1

  402. - SSP1_ICR:

  403.     fields: !!omap

  404.     - RORIC:

  405.         access: w

  406.         description: Writing a 1 to this bit clears the 'frame was received when RxFIFO

  407.           was full' interrupt

  408.         lsb: 0

  409.         reset_value: ''

  410.         width: 1

  411.     - RTIC:

  412.         access: w

  413.         description: Writing a 1 to this bit clears the Rx FIFO was not empty and

  414.           has not been read for a time-out period interrupt

  415.         lsb: 1

  416.         reset_value: ''

  417.         width: 1

  418. - SSP0_DMACR:

  419.     fields: !!omap

  420.     - RXDMAE:

  421.         access: rw

  422.         description: Receive DMA Enable

  423.         lsb: 0

  424.         reset_value: '0'

  425.         width: 1

  426.     - TXDMAE:

  427.         access: rw

  428.         description: Transmit DMA Enable

  429.         lsb: 1

  430.         reset_value: '0'

  431.         width: 1

  432. - SSP1_DMACR:

  433.     fields: !!omap

  434.     - RXDMAE:

  435.         access: rw

  436.         description: Receive DMA Enable

  437.         lsb: 0

  438.         reset_value: '0'

  439.         width: 1

  440.     - TXDMAE:

  441.         access: rw

  442.         description: Transmit DMA Enable

  443.         lsb: 1

  444.         reset_value: '0'

  445.         width: 1