572 lines
16 KiB
C
572 lines
16 KiB
C
/** @addtogroup i2c_file I2C peripheral API
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* @ingroup peripheral_apis
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@author @htmlonly © @endhtmlonly 2010
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Thomas Otto <tommi@viadmin.org>
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@author @htmlonly © @endhtmlonly 2012
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Ken Sarkies <ksarkies@internode.on.net>
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Devices can have up to three I2C peripherals. The peripherals support SMBus and
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PMBus variants.
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A peripheral begins after reset in Slave mode. To become a Master a start
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condition must be generated. The peripheral will remain in Master mode unless
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a multimaster contention is lost or a stop condition is generated.
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@todo all sorts of lovely stuff like DMA, Interrupts, SMBus variant, Status
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register access, Error conditions
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/stm32/i2c.h>
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#include <libopencm3/stm32/rcc.h>
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/**@{*/
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Reset.
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The I2C peripheral and all its associated configuration registers are placed in
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the reset condition. The reset is effected via the RCC peripheral reset system.
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@param[in] i2c Unsigned int32. I2C peripheral identifier @ref i2c_reg_base.
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*/
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void i2c_reset(uint32_t i2c)
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{
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switch (i2c) {
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case I2C1:
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rcc_periph_reset_pulse(RST_I2C1);
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break;
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#if defined(I2C2_BASE)
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case I2C2:
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rcc_periph_reset_pulse(RST_I2C2);
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break;
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#endif
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#if defined(I2C3_BASE)
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case I2C3:
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rcc_periph_reset_pulse(RST_I2C3);
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break;
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#endif
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#if defined(I2C4_BASE)
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case I2C4:
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rcc_periph_reset_pulse(RST_I2C4);
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break;
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#endif
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default:
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Peripheral Enable.
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_peripheral_enable(uint32_t i2c)
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{
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I2C_CR1(i2c) |= I2C_CR1_PE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Peripheral Disable.
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This must not be reset while in Master mode until a communication has finished.
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In Slave mode, the peripheral is disabled only after communication has ended.
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_peripheral_disable(uint32_t i2c)
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{
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I2C_CR1(i2c) &= ~I2C_CR1_PE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Send Start Condition.
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If in Master mode this will cause a restart condition to occur at the end of the
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current transmission. If in Slave mode, this will initiate a start condition
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when the current bus activity is completed.
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_send_start(uint32_t i2c)
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{
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I2C_CR1(i2c) |= I2C_CR1_START;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Send Stop Condition.
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After the current byte transfer this will initiate a stop condition if in Master
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mode, or simply release the bus if in Slave mode.
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_send_stop(uint32_t i2c)
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{
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I2C_CR1(i2c) |= I2C_CR1_STOP;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Clear Stop Flag.
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Clear the "Send Stop" flag in the I2C config register
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_clear_stop(uint32_t i2c)
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{
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I2C_CR1(i2c) &= ~I2C_CR1_STOP;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Set the 7 bit Slave Address for the Peripheral.
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This sets an address for Slave mode operation, in 7 bit form.
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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@param[in] slave Unsigned int8. Slave address 0...127.
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*/
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void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave)
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{
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uint16_t val = (uint16_t)(slave << 1);
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/* Datasheet: always keep 1 by software. */
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val |= (1 << 14);
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I2C_OAR1(i2c) = val;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Set the 10 bit Slave Address for the Peripheral.
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This sets an address for Slave mode operation, in 10 bit form.
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@todo add "I2C_OAR1(i2c) |= (1 << 14);" as above
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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@param[in] slave Unsigned int16. Slave address 0...1023.
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*/
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void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave)
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{
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I2C_OAR1(i2c) = (uint16_t)(I2C_OAR1_ADDMODE | slave);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Set the secondary 7 bit Slave Address for the Peripheral.
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This sets a secondary address for Slave mode operation, in 7 bit form.
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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@param[in] slave Unsigned int8. Slave address 0...127.
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*/
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void i2c_set_own_7bit_slave_address_two(uint32_t i2c, uint8_t slave)
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{
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uint16_t val = (uint16_t)(slave << 1);
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I2C_OAR2(i2c) = val;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Enable dual addressing mode for the Peripheral.
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Both OAR1 and OAR2 are recognised in 7-bit addressing mode.
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_enable_dual_addressing_mode(uint32_t i2c)
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{
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I2C_OAR2(i2c) |= I2C_OAR2_ENDUAL;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Disable dual addressing mode for the Peripheral.
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Only OAR1 is recognised in 7-bit addressing mode.
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_disable_dual_addressing_mode(uint32_t i2c)
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{
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I2C_OAR2(i2c) &= ~(I2C_OAR2_ENDUAL);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Set Peripheral Clock Frequency.
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Set the peripheral clock frequency: 2MHz to 36MHz (the APB frequency). Note
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that this is <b> not </b> the I2C bus clock. This is set in conjunction with
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the Clock Control register to generate the Master bus clock, see @ref
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i2c_set_ccr
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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@param[in] freq Unsigned int8. Clock Frequency Setting @ref i2c_clock.
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*/
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void i2c_set_clock_frequency(uint32_t i2c, uint8_t freq)
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{
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uint16_t reg16;
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reg16 = I2C_CR2(i2c) & 0xffc0; /* Clear bits [5:0]. */
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reg16 |= freq;
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I2C_CR2(i2c) = reg16;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Send Data.
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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@param[in] data Unsigned int8. Byte to send.
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*/
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void i2c_send_data(uint32_t i2c, uint8_t data)
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{
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I2C_DR(i2c) = data;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Set Fast Mode.
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Set the clock frequency to the high clock rate mode (up to 400kHz). The actual
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clock frequency must be set with @ref i2c_set_clock_frequency
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_set_fast_mode(uint32_t i2c)
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{
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I2C_CCR(i2c) |= I2C_CCR_FS;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Set Standard Mode.
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Set the clock frequency to the standard clock rate mode (up to 100kHz). The
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actual clock frequency must be set with @ref i2c_set_clock_frequency
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_set_standard_mode(uint32_t i2c)
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{
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I2C_CCR(i2c) &= ~I2C_CCR_FS;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Set Bus Clock Frequency.
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Set the bus clock frequency. This is a 12 bit number (0...4095) calculated
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from the formulae given in the STM32F1 reference manual in the description
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of the CCR field. It is a divisor of the peripheral clock frequency
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@ref i2c_set_clock_frequency modified by the fast mode setting
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@ref i2c_set_fast_mode
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@todo provide additional API assitance to set the clock, eg macros
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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@param[in] freq Unsigned int16. Bus Clock Frequency Setting 0...4095.
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*/
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void i2c_set_ccr(uint32_t i2c, uint16_t freq)
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{
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uint16_t reg16;
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reg16 = I2C_CCR(i2c) & 0xf000; /* Clear bits [11:0]. */
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reg16 |= freq;
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I2C_CCR(i2c) = reg16;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Set the Rise Time.
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Set the maximum rise time on the bus according to the I2C specification, as 1
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more than the specified rise time in peripheral clock cycles. This is a 6 bit
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number.
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@todo provide additional APIP assistance.
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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@param[in] trise Unsigned int16. Rise Time Setting 0...63.
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*/
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void i2c_set_trise(uint32_t i2c, uint16_t trise)
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{
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I2C_TRISE(i2c) = trise;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Send the 7-bit Slave Address.
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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@param[in] slave Unsigned int16. Slave address 0...1023.
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@param[in] readwrite Unsigned int8. Single bit to instruct slave to receive or
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send @ref i2c_rw.
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*/
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void i2c_send_7bit_address(uint32_t i2c, uint8_t slave, uint8_t readwrite)
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{
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I2C_DR(i2c) = (uint8_t)((slave << 1) | readwrite);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Get Data.
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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uint8_t i2c_get_data(uint32_t i2c)
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{
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return I2C_DR(i2c) & 0xff;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Enable Interrupt
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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@param[in] interrupt Unsigned int32. Interrupt to enable.
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*/
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void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt)
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{
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I2C_CR2(i2c) |= interrupt;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Disable Interrupt
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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@param[in] interrupt Unsigned int32. Interrupt to disable.
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*/
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void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt)
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{
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I2C_CR2(i2c) &= ~interrupt;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Enable ACK
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Enables acking of own 7/10 bit address
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_enable_ack(uint32_t i2c)
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{
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I2C_CR1(i2c) |= I2C_CR1_ACK;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Disable ACK
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Disables acking of own 7/10 bit address
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_disable_ack(uint32_t i2c)
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{
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I2C_CR1(i2c) &= ~I2C_CR1_ACK;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C NACK Next Byte
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Causes the I2C controller to NACK the reception of the next byte
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_nack_next(uint32_t i2c)
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{
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I2C_CR1(i2c) |= I2C_CR1_POS;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C NACK Next Byte
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Causes the I2C controller to NACK the reception of the current byte
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_nack_current(uint32_t i2c)
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{
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I2C_CR1(i2c) &= ~I2C_CR1_POS;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Set clock duty cycle
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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@param[in] dutycycle Unsigned int32. I2C duty cycle @ref i2c_duty_cycle.
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*/
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void i2c_set_dutycycle(uint32_t i2c, uint32_t dutycycle)
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{
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if (dutycycle == I2C_CCR_DUTY_DIV2) {
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I2C_CCR(i2c) &= ~I2C_CCR_DUTY;
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} else {
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I2C_CCR(i2c) |= I2C_CCR_DUTY;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Enable DMA
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_enable_dma(uint32_t i2c)
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{
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I2C_CR2(i2c) |= I2C_CR2_DMAEN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Disable DMA
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_disable_dma(uint32_t i2c)
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{
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I2C_CR2(i2c) &= ~I2C_CR2_DMAEN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Set DMA last transfer
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_set_dma_last_transfer(uint32_t i2c)
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{
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I2C_CR2(i2c) |= I2C_CR2_LAST;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Clear DMA last transfer
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_clear_dma_last_transfer(uint32_t i2c)
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{
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I2C_CR2(i2c) &= ~I2C_CR2_LAST;
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}
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static void i2c_write7_v1(uint32_t i2c, int addr, uint8_t *data, size_t n)
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{
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while ((I2C_SR2(i2c) & I2C_SR2_BUSY)) {
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}
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i2c_send_start(i2c);
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/* Wait for master mode selected */
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while (!((I2C_SR1(i2c) & I2C_SR1_SB)
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& (I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY))));
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i2c_send_7bit_address(i2c, addr, I2C_WRITE);
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/* Waiting for address is transferred. */
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while (!(I2C_SR1(i2c) & I2C_SR1_ADDR));
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/* Clearing ADDR condition sequence. */
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(void)I2C_SR2(i2c);
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for (size_t i = 0; i < n; i++) {
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i2c_send_data(i2c, data[i]);
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while (!(I2C_SR1(i2c) & (I2C_SR1_BTF)));
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}
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}
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static void i2c_read7_v1(uint32_t i2c, int addr, uint8_t *res, size_t n)
|
|
{
|
|
i2c_send_start(i2c);
|
|
i2c_enable_ack(i2c);
|
|
|
|
/* Wait for master mode selected */
|
|
while (!((I2C_SR1(i2c) & I2C_SR1_SB)
|
|
& (I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY))));
|
|
|
|
i2c_send_7bit_address(i2c, addr, I2C_READ);
|
|
|
|
/* Waiting for address is transferred. */
|
|
while (!(I2C_SR1(i2c) & I2C_SR1_ADDR));
|
|
/* Clearing ADDR condition sequence. */
|
|
(void)I2C_SR2(i2c);
|
|
|
|
for (size_t i = 0; i < n; ++i) {
|
|
if (i == n - 1) {
|
|
i2c_disable_ack(i2c);
|
|
}
|
|
while (!(I2C_SR1(i2c) & I2C_SR1_RxNE));
|
|
res[i] = i2c_get_data(i2c);
|
|
}
|
|
i2c_send_stop(i2c);
|
|
|
|
return;
|
|
}
|
|
|
|
/**
|
|
* Run a write/read transaction to a given 7bit i2c address
|
|
* If both write & read are provided, the read will use repeated start.
|
|
* Both write and read are optional
|
|
* There are likely still issues with repeated start/stop condtions!
|
|
* @param i2c peripheral of choice, eg I2C1
|
|
* @param addr 7 bit i2c device address
|
|
* @param w buffer of data to write
|
|
* @param wn length of w
|
|
* @param r destination buffer to read into
|
|
* @param rn number of bytes to read (r should be at least this long)
|
|
*/
|
|
void i2c_transfer7(uint32_t i2c, uint8_t addr, uint8_t *w, size_t wn, uint8_t *r, size_t rn) {
|
|
if (wn) {
|
|
i2c_write7_v1(i2c, addr, w, wn);
|
|
}
|
|
if (rn) {
|
|
i2c_read7_v1(i2c, addr, r, rn);
|
|
} else {
|
|
i2c_send_stop(i2c);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Set the i2c communication speed.
|
|
* @param i2c peripheral, eg I2C1
|
|
* @param speed one of the listed speed modes @ref i2c_speeds
|
|
* @param clock_megahz i2c peripheral clock speed in MHz. Usually, rcc_apb1_frequency / 1e6
|
|
*/
|
|
void i2c_set_speed(uint32_t i2c, enum i2c_speeds speed, uint32_t clock_megahz)
|
|
{
|
|
i2c_set_clock_frequency(i2c, clock_megahz);
|
|
switch(speed) {
|
|
case i2c_speed_fm_400k:
|
|
i2c_set_fast_mode(i2c);
|
|
i2c_set_ccr(i2c, clock_megahz * 5 / 6);
|
|
i2c_set_trise(i2c, clock_megahz + 1);
|
|
break;
|
|
default:
|
|
/* fall back to standard mode */
|
|
case i2c_speed_sm_100k:
|
|
i2c_set_standard_mode(i2c);
|
|
/* x Mhz / (100kHz * 2) */
|
|
i2c_set_ccr(i2c, clock_megahz * 5);
|
|
/* Sm mode, (100kHz) freqMhz + 1 */
|
|
i2c_set_trise(i2c, clock_megahz + 1);
|
|
break;
|
|
}
|
|
}
|
|
|
|
|
|
/**@}*/
|