1499 lines
35 KiB
YAML
1499 lines
35 KiB
YAML
!!omap
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- GPDMA_INTSTAT:
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fields: !!omap
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- INTSTAT:
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access: r
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description: Status of DMA channel interrupts after masking
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lsb: 0
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reset_value: '0x00'
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width: 8
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- GPDMA_INTTCSTAT:
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fields: !!omap
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- INTTCSTAT:
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access: r
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description: Terminal count interrupt request status for DMA channels
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lsb: 0
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reset_value: '0x00'
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width: 8
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- GPDMA_INTTCCLEAR:
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fields: !!omap
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- INTTCCLEAR:
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access: w
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description: Allows clearing the Terminal count interrupt request (IntTCStat)
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for DMA channels
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lsb: 0
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reset_value: '0x00'
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width: 8
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- GPDMA_INTERRSTAT:
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fields: !!omap
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- INTERRSTAT:
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access: r
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description: Interrupt error status for DMA channels
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lsb: 0
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reset_value: '0x00'
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width: 8
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- GPDMA_INTERRCLR:
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fields: !!omap
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- INTERRCLR:
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access: w
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description: Writing a 1 clears the error interrupt request (IntErrStat) for
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DMA channels
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lsb: 0
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reset_value: '0x00'
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width: 8
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- GPDMA_RAWINTTCSTAT:
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fields: !!omap
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- RAWINTTCSTAT:
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access: r
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description: Status of the terminal count interrupt for DMA channels prior
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to masking
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lsb: 0
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reset_value: '0x00'
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width: 8
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- GPDMA_RAWINTERRSTAT:
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fields: !!omap
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- RAWINTERRSTAT:
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access: r
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description: Status of the error interrupt for DMA channels prior to masking
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lsb: 0
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reset_value: '0x00'
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width: 8
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- GPDMA_ENBLDCHNS:
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fields: !!omap
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- ENABLEDCHANNELS:
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access: r
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description: Enable status for DMA channels
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lsb: 0
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reset_value: '0x00'
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width: 8
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- GPDMA_SOFTBREQ:
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fields: !!omap
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- SOFTBREQ:
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access: rw
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description: Software burst request flags for each of 16 possible sources
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lsb: 0
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reset_value: '0x00'
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width: 16
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- GPDMA_SOFTSREQ:
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fields: !!omap
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- SOFTSREQ:
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access: rw
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description: Software single transfer request flags for each of 16 possible
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sources
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lsb: 0
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reset_value: '0x00'
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width: 16
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- GPDMA_SOFTLBREQ:
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fields: !!omap
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- SOFTLBREQ:
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access: rw
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description: Software last burst request flags for each of 16 possible sources
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lsb: 0
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reset_value: '0x00'
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width: 16
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- GPDMA_SOFTLSREQ:
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fields: !!omap
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- SOFTLSREQ:
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access: rw
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description: Software last single transfer request flags for each of 16 possible
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sources
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lsb: 0
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reset_value: '0x00'
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width: 16
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- GPDMA_CONFIG:
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fields: !!omap
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- E:
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access: rw
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description: DMA Controller enable
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lsb: 0
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reset_value: '0'
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width: 1
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- M0:
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access: rw
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description: AHB Master 0 endianness configuration
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lsb: 1
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reset_value: '0'
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width: 1
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- M1:
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access: rw
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description: AHB Master 1 endianness configuration
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lsb: 2
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reset_value: '0'
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width: 1
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- GPDMA_SYNC:
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fields: !!omap
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- DMACSYNC:
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access: rw
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description: Controls the synchronization logic for DMA request signals
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lsb: 0
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reset_value: '0x00'
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width: 16
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- GPDMA_C0SRCADDR:
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fields: !!omap
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- SRCADDR:
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access: rw
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description: DMA source address
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lsb: 0
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reset_value: '0x00000000'
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width: 32
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- GPDMA_C1SRCADDR:
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fields: !!omap
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- SRCADDR:
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access: rw
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description: DMA source address
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lsb: 0
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reset_value: '0x00000000'
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width: 32
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- GPDMA_C2SRCADDR:
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fields: !!omap
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- SRCADDR:
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access: rw
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description: DMA source address
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lsb: 0
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reset_value: '0x00000000'
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width: 32
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- GPDMA_C3SRCADDR:
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fields: !!omap
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- SRCADDR:
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access: rw
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description: DMA source address
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lsb: 0
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reset_value: '0x00000000'
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width: 32
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- GPDMA_C4SRCADDR:
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fields: !!omap
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- SRCADDR:
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access: rw
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description: DMA source address
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lsb: 0
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reset_value: '0x00000000'
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width: 32
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- GPDMA_C5SRCADDR:
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fields: !!omap
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- SRCADDR:
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access: rw
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description: DMA source address
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lsb: 0
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reset_value: '0x00000000'
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width: 32
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- GPDMA_C6SRCADDR:
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fields: !!omap
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- SRCADDR:
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access: rw
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description: DMA source address
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lsb: 0
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reset_value: '0x00000000'
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width: 32
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- GPDMA_C7SRCADDR:
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fields: !!omap
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- SRCADDR:
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access: rw
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description: DMA source address
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lsb: 0
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reset_value: '0x00000000'
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width: 32
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- GPDMA_C0DESTADDR:
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fields: !!omap
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- DESTADDR:
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access: rw
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description: DMA source address
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lsb: 0
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reset_value: '0x00000000'
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width: 32
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- GPDMA_C1DESTADDR:
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fields: !!omap
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- DESTADDR:
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access: rw
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description: DMA source address
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lsb: 0
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reset_value: '0x00000000'
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width: 32
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- GPDMA_C2DESTADDR:
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fields: !!omap
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- DESTADDR:
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access: rw
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description: DMA source address
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lsb: 0
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reset_value: '0x00000000'
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width: 32
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- GPDMA_C3DESTADDR:
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fields: !!omap
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- DESTADDR:
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access: rw
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description: DMA source address
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lsb: 0
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reset_value: '0x00000000'
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width: 32
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- GPDMA_C4DESTADDR:
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fields: !!omap
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- DESTADDR:
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access: rw
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description: DMA source address
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lsb: 0
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reset_value: '0x00000000'
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width: 32
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- GPDMA_C5DESTADDR:
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fields: !!omap
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- DESTADDR:
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access: rw
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description: DMA source address
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lsb: 0
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reset_value: '0x00000000'
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width: 32
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- GPDMA_C6DESTADDR:
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fields: !!omap
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- DESTADDR:
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access: rw
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description: DMA source address
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lsb: 0
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reset_value: '0x00000000'
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width: 32
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- GPDMA_C7DESTADDR:
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fields: !!omap
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- DESTADDR:
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access: rw
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description: DMA source address
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lsb: 0
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reset_value: '0x00000000'
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width: 32
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- GPDMA_C0LLI:
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fields: !!omap
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- LM:
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access: rw
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description: AHB master select for loading the next LLI
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lsb: 0
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reset_value: '0'
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width: 1
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- LLI:
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access: rw
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description: Linked list item
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lsb: 2
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reset_value: '0x00000000'
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width: 30
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- GPDMA_C1LLI:
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fields: !!omap
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- LM:
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access: rw
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description: AHB master select for loading the next LLI
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lsb: 0
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reset_value: '0'
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width: 1
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- LLI:
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access: rw
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description: Linked list item
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lsb: 2
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reset_value: '0x00000000'
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width: 30
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- GPDMA_C2LLI:
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fields: !!omap
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- LM:
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access: rw
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description: AHB master select for loading the next LLI
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lsb: 0
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reset_value: '0'
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width: 1
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- LLI:
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access: rw
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description: Linked list item
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lsb: 2
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reset_value: '0x00000000'
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width: 30
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- GPDMA_C3LLI:
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fields: !!omap
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- LM:
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access: rw
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description: AHB master select for loading the next LLI
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lsb: 0
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reset_value: '0'
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width: 1
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- LLI:
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access: rw
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description: Linked list item
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lsb: 2
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reset_value: '0x00000000'
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width: 30
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- GPDMA_C4LLI:
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fields: !!omap
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- LM:
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access: rw
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description: AHB master select for loading the next LLI
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lsb: 0
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reset_value: '0'
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width: 1
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- LLI:
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access: rw
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description: Linked list item
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lsb: 2
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reset_value: '0x00000000'
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width: 30
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- GPDMA_C5LLI:
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fields: !!omap
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- LM:
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access: rw
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description: AHB master select for loading the next LLI
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lsb: 0
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reset_value: '0'
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width: 1
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- LLI:
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access: rw
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description: Linked list item
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lsb: 2
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reset_value: '0x00000000'
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width: 30
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- GPDMA_C6LLI:
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fields: !!omap
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- LM:
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access: rw
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description: AHB master select for loading the next LLI
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lsb: 0
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reset_value: '0'
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width: 1
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- LLI:
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access: rw
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description: Linked list item
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lsb: 2
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reset_value: '0x00000000'
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width: 30
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- GPDMA_C7LLI:
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fields: !!omap
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- LM:
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access: rw
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description: AHB master select for loading the next LLI
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lsb: 0
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reset_value: '0'
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width: 1
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- LLI:
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access: rw
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description: Linked list item
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lsb: 2
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reset_value: '0x00000000'
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width: 30
|
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- GPDMA_C0CONTROL:
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fields: !!omap
|
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- TRANSFERSIZE:
|
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access: rw
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description: Transfer size in number of transfers
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lsb: 0
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reset_value: '0x00'
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width: 12
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- SBSIZE:
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access: rw
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description: Source burst size
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lsb: 12
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reset_value: '0x0'
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width: 3
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- DBSIZE:
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access: rw
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description: Destination burst size
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lsb: 15
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reset_value: '0x0'
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width: 3
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- SWIDTH:
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access: rw
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description: Source transfer width
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lsb: 18
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reset_value: '0x0'
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width: 3
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- DWIDTH:
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access: rw
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description: Destination transfer width
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lsb: 21
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reset_value: '0x0'
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width: 3
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- S:
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access: rw
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description: Source AHB master select
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lsb: 24
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reset_value: '0'
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width: 1
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- D:
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access: rw
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description: Destination AHB master select
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lsb: 25
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reset_value: '0'
|
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width: 1
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- SI:
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access: rw
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description: Source increment
|
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lsb: 26
|
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reset_value: '0'
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width: 1
|
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- DI:
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access: rw
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description: Destination increment
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lsb: 27
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reset_value: '0'
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width: 1
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- PROT1:
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access: rw
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description: This information is provided to the peripheral during a DMA bus
|
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access and indicates that the access is in user mode or privileged mode
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lsb: 28
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reset_value: '0'
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width: 1
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- PROT2:
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access: rw
|
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description: This information is provided to the peripheral during a DMA bus
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access and indicates to the peripheral that the access is bufferable or
|
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not bufferable
|
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lsb: 29
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reset_value: '0'
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width: 1
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- PROT3:
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access: rw
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description: This information is provided to the peripheral during a DMA bus
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access and indicates to the peripheral that the access is cacheable or not
|
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cacheable
|
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lsb: 30
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reset_value: '0'
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width: 1
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- I:
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access: rw
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description: Terminal count interrupt enable bit
|
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lsb: 31
|
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reset_value: '0'
|
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width: 1
|
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- GPDMA_C1CONTROL:
|
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fields: !!omap
|
|
- TRANSFERSIZE:
|
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access: rw
|
|
description: Transfer size in number of transfers
|
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lsb: 0
|
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reset_value: '0x00'
|
|
width: 12
|
|
- SBSIZE:
|
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access: rw
|
|
description: Source burst size
|
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lsb: 12
|
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reset_value: '0x0'
|
|
width: 3
|
|
- DBSIZE:
|
|
access: rw
|
|
description: Destination burst size
|
|
lsb: 15
|
|
reset_value: '0x0'
|
|
width: 3
|
|
- SWIDTH:
|
|
access: rw
|
|
description: Source transfer width
|
|
lsb: 18
|
|
reset_value: '0x0'
|
|
width: 3
|
|
- DWIDTH:
|
|
access: rw
|
|
description: Destination transfer width
|
|
lsb: 21
|
|
reset_value: '0x0'
|
|
width: 3
|
|
- S:
|
|
access: rw
|
|
description: Source AHB master select
|
|
lsb: 24
|
|
reset_value: '0'
|
|
width: 1
|
|
- D:
|
|
access: rw
|
|
description: Destination AHB master select
|
|
lsb: 25
|
|
reset_value: '0'
|
|
width: 1
|
|
- SI:
|
|
access: rw
|
|
description: Source increment
|
|
lsb: 26
|
|
reset_value: '0'
|
|
width: 1
|
|
- DI:
|
|
access: rw
|
|
description: Destination increment
|
|
lsb: 27
|
|
reset_value: '0'
|
|
width: 1
|
|
- PROT1:
|
|
access: rw
|
|
description: This information is provided to the peripheral during a DMA bus
|
|
access and indicates that the access is in user mode or privileged mode
|
|
lsb: 28
|
|
reset_value: '0'
|
|
width: 1
|
|
- PROT2:
|
|
access: rw
|
|
description: This information is provided to the peripheral during a DMA bus
|
|
access and indicates to the peripheral that the access is bufferable or
|
|
not bufferable
|
|
lsb: 29
|
|
reset_value: '0'
|
|
width: 1
|
|
- PROT3:
|
|
access: rw
|
|
description: This information is provided to the peripheral during a DMA bus
|
|
access and indicates to the peripheral that the access is cacheable or not
|
|
cacheable
|
|
lsb: 30
|
|
reset_value: '0'
|
|
width: 1
|
|
- I:
|
|
access: rw
|
|
description: Terminal count interrupt enable bit
|
|
lsb: 31
|
|
reset_value: '0'
|
|
width: 1
|
|
- GPDMA_C2CONTROL:
|
|
fields: !!omap
|
|
- TRANSFERSIZE:
|
|
access: rw
|
|
description: Transfer size in number of transfers
|
|
lsb: 0
|
|
reset_value: '0x00'
|
|
width: 12
|
|
- SBSIZE:
|
|
access: rw
|
|
description: Source burst size
|
|
lsb: 12
|
|
reset_value: '0x0'
|
|
width: 3
|
|
- DBSIZE:
|
|
access: rw
|
|
description: Destination burst size
|
|
lsb: 15
|
|
reset_value: '0x0'
|
|
width: 3
|
|
- SWIDTH:
|
|
access: rw
|
|
description: Source transfer width
|
|
lsb: 18
|
|
reset_value: '0x0'
|
|
width: 3
|
|
- DWIDTH:
|
|
access: rw
|
|
description: Destination transfer width
|
|
lsb: 21
|
|
reset_value: '0x0'
|
|
width: 3
|
|
- S:
|
|
access: rw
|
|
description: Source AHB master select
|
|
lsb: 24
|
|
reset_value: '0'
|
|
width: 1
|
|
- D:
|
|
access: rw
|
|
description: Destination AHB master select
|
|
lsb: 25
|
|
reset_value: '0'
|
|
width: 1
|
|
- SI:
|
|
access: rw
|
|
description: Source increment
|
|
lsb: 26
|
|
reset_value: '0'
|
|
width: 1
|
|
- DI:
|
|
access: rw
|
|
description: Destination increment
|
|
lsb: 27
|
|
reset_value: '0'
|
|
width: 1
|
|
- PROT1:
|
|
access: rw
|
|
description: This information is provided to the peripheral during a DMA bus
|
|
access and indicates that the access is in user mode or privileged mode
|
|
lsb: 28
|
|
reset_value: '0'
|
|
width: 1
|
|
- PROT2:
|
|
access: rw
|
|
description: This information is provided to the peripheral during a DMA bus
|
|
access and indicates to the peripheral that the access is bufferable or
|
|
not bufferable
|
|
lsb: 29
|
|
reset_value: '0'
|
|
width: 1
|
|
- PROT3:
|
|
access: rw
|
|
description: This information is provided to the peripheral during a DMA bus
|
|
access and indicates to the peripheral that the access is cacheable or not
|
|
cacheable
|
|
lsb: 30
|
|
reset_value: '0'
|
|
width: 1
|
|
- I:
|
|
access: rw
|
|
description: Terminal count interrupt enable bit
|
|
lsb: 31
|
|
reset_value: '0'
|
|
width: 1
|
|
- GPDMA_C3CONTROL:
|
|
fields: !!omap
|
|
- TRANSFERSIZE:
|
|
access: rw
|
|
description: Transfer size in number of transfers
|
|
lsb: 0
|
|
reset_value: '0x00'
|
|
width: 12
|
|
- SBSIZE:
|
|
access: rw
|
|
description: Source burst size
|
|
lsb: 12
|
|
reset_value: '0x0'
|
|
width: 3
|
|
- DBSIZE:
|
|
access: rw
|
|
description: Destination burst size
|
|
lsb: 15
|
|
reset_value: '0x0'
|
|
width: 3
|
|
- SWIDTH:
|
|
access: rw
|
|
description: Source transfer width
|
|
lsb: 18
|
|
reset_value: '0x0'
|
|
width: 3
|
|
- DWIDTH:
|
|
access: rw
|
|
description: Destination transfer width
|
|
lsb: 21
|
|
reset_value: '0x0'
|
|
width: 3
|
|
- S:
|
|
access: rw
|
|
description: Source AHB master select
|
|
lsb: 24
|
|
reset_value: '0'
|
|
width: 1
|
|
- D:
|
|
access: rw
|
|
description: Destination AHB master select
|
|
lsb: 25
|
|
reset_value: '0'
|
|
width: 1
|
|
- SI:
|
|
access: rw
|
|
description: Source increment
|
|
lsb: 26
|
|
reset_value: '0'
|
|
width: 1
|
|
- DI:
|
|
access: rw
|
|
description: Destination increment
|
|
lsb: 27
|
|
reset_value: '0'
|
|
width: 1
|
|
- PROT1:
|
|
access: rw
|
|
description: This information is provided to the peripheral during a DMA bus
|
|
access and indicates that the access is in user mode or privileged mode
|
|
lsb: 28
|
|
reset_value: '0'
|
|
width: 1
|
|
- PROT2:
|
|
access: rw
|
|
description: This information is provided to the peripheral during a DMA bus
|
|
access and indicates to the peripheral that the access is bufferable or
|
|
not bufferable
|
|
lsb: 29
|
|
reset_value: '0'
|
|
width: 1
|
|
- PROT3:
|
|
access: rw
|
|
description: This information is provided to the peripheral during a DMA bus
|
|
access and indicates to the peripheral that the access is cacheable or not
|
|
cacheable
|
|
lsb: 30
|
|
reset_value: '0'
|
|
width: 1
|
|
- I:
|
|
access: rw
|
|
description: Terminal count interrupt enable bit
|
|
lsb: 31
|
|
reset_value: '0'
|
|
width: 1
|
|
- GPDMA_C4CONTROL:
|
|
fields: !!omap
|
|
- TRANSFERSIZE:
|
|
access: rw
|
|
description: Transfer size in number of transfers
|
|
lsb: 0
|
|
reset_value: '0x00'
|
|
width: 12
|
|
- SBSIZE:
|
|
access: rw
|
|
description: Source burst size
|
|
lsb: 12
|
|
reset_value: '0x0'
|
|
width: 3
|
|
- DBSIZE:
|
|
access: rw
|
|
description: Destination burst size
|
|
lsb: 15
|
|
reset_value: '0x0'
|
|
width: 3
|
|
- SWIDTH:
|
|
access: rw
|
|
description: Source transfer width
|
|
lsb: 18
|
|
reset_value: '0x0'
|
|
width: 3
|
|
- DWIDTH:
|
|
access: rw
|
|
description: Destination transfer width
|
|
lsb: 21
|
|
reset_value: '0x0'
|
|
width: 3
|
|
- S:
|
|
access: rw
|
|
description: Source AHB master select
|
|
lsb: 24
|
|
reset_value: '0'
|
|
width: 1
|
|
- D:
|
|
access: rw
|
|
description: Destination AHB master select
|
|
lsb: 25
|
|
reset_value: '0'
|
|
width: 1
|
|
- SI:
|
|
access: rw
|
|
description: Source increment
|
|
lsb: 26
|
|
reset_value: '0'
|
|
width: 1
|
|
- DI:
|
|
access: rw
|
|
description: Destination increment
|
|
lsb: 27
|
|
reset_value: '0'
|
|
width: 1
|
|
- PROT1:
|
|
access: rw
|
|
description: This information is provided to the peripheral during a DMA bus
|
|
access and indicates that the access is in user mode or privileged mode
|
|
lsb: 28
|
|
reset_value: '0'
|
|
width: 1
|
|
- PROT2:
|
|
access: rw
|
|
description: This information is provided to the peripheral during a DMA bus
|
|
access and indicates to the peripheral that the access is bufferable or
|
|
not bufferable
|
|
lsb: 29
|
|
reset_value: '0'
|
|
width: 1
|
|
- PROT3:
|
|
access: rw
|
|
description: This information is provided to the peripheral during a DMA bus
|
|
access and indicates to the peripheral that the access is cacheable or not
|
|
cacheable
|
|
lsb: 30
|
|
reset_value: '0'
|
|
width: 1
|
|
- I:
|
|
access: rw
|
|
description: Terminal count interrupt enable bit
|
|
lsb: 31
|
|
reset_value: '0'
|
|
width: 1
|
|
- GPDMA_C5CONTROL:
|
|
fields: !!omap
|
|
- TRANSFERSIZE:
|
|
access: rw
|
|
description: Transfer size in number of transfers
|
|
lsb: 0
|
|
reset_value: '0x00'
|
|
width: 12
|
|
- SBSIZE:
|
|
access: rw
|
|
description: Source burst size
|
|
lsb: 12
|
|
reset_value: '0x0'
|
|
width: 3
|
|
- DBSIZE:
|
|
access: rw
|
|
description: Destination burst size
|
|
lsb: 15
|
|
reset_value: '0x0'
|
|
width: 3
|
|
- SWIDTH:
|
|
access: rw
|
|
description: Source transfer width
|
|
lsb: 18
|
|
reset_value: '0x0'
|
|
width: 3
|
|
- DWIDTH:
|
|
access: rw
|
|
description: Destination transfer width
|
|
lsb: 21
|
|
reset_value: '0x0'
|
|
width: 3
|
|
- S:
|
|
access: rw
|
|
description: Source AHB master select
|
|
lsb: 24
|
|
reset_value: '0'
|
|
width: 1
|
|
- D:
|
|
access: rw
|
|
description: Destination AHB master select
|
|
lsb: 25
|
|
reset_value: '0'
|
|
width: 1
|
|
- SI:
|
|
access: rw
|
|
description: Source increment
|
|
lsb: 26
|
|
reset_value: '0'
|
|
width: 1
|
|
- DI:
|
|
access: rw
|
|
description: Destination increment
|
|
lsb: 27
|
|
reset_value: '0'
|
|
width: 1
|
|
- PROT1:
|
|
access: rw
|
|
description: This information is provided to the peripheral during a DMA bus
|
|
access and indicates that the access is in user mode or privileged mode
|
|
lsb: 28
|
|
reset_value: '0'
|
|
width: 1
|
|
- PROT2:
|
|
access: rw
|
|
description: This information is provided to the peripheral during a DMA bus
|
|
access and indicates to the peripheral that the access is bufferable or
|
|
not bufferable
|
|
lsb: 29
|
|
reset_value: '0'
|
|
width: 1
|
|
- PROT3:
|
|
access: rw
|
|
description: This information is provided to the peripheral during a DMA bus
|
|
access and indicates to the peripheral that the access is cacheable or not
|
|
cacheable
|
|
lsb: 30
|
|
reset_value: '0'
|
|
width: 1
|
|
- I:
|
|
access: rw
|
|
description: Terminal count interrupt enable bit
|
|
lsb: 31
|
|
reset_value: '0'
|
|
width: 1
|
|
- GPDMA_C6CONTROL:
|
|
fields: !!omap
|
|
- TRANSFERSIZE:
|
|
access: rw
|
|
description: Transfer size in number of transfers
|
|
lsb: 0
|
|
reset_value: '0x00'
|
|
width: 12
|
|
- SBSIZE:
|
|
access: rw
|
|
description: Source burst size
|
|
lsb: 12
|
|
reset_value: '0x0'
|
|
width: 3
|
|
- DBSIZE:
|
|
access: rw
|
|
description: Destination burst size
|
|
lsb: 15
|
|
reset_value: '0x0'
|
|
width: 3
|
|
- SWIDTH:
|
|
access: rw
|
|
description: Source transfer width
|
|
lsb: 18
|
|
reset_value: '0x0'
|
|
width: 3
|
|
- DWIDTH:
|
|
access: rw
|
|
description: Destination transfer width
|
|
lsb: 21
|
|
reset_value: '0x0'
|
|
width: 3
|
|
- S:
|
|
access: rw
|
|
description: Source AHB master select
|
|
lsb: 24
|
|
reset_value: '0'
|
|
width: 1
|
|
- D:
|
|
access: rw
|
|
description: Destination AHB master select
|
|
lsb: 25
|
|
reset_value: '0'
|
|
width: 1
|
|
- SI:
|
|
access: rw
|
|
description: Source increment
|
|
lsb: 26
|
|
reset_value: '0'
|
|
width: 1
|
|
- DI:
|
|
access: rw
|
|
description: Destination increment
|
|
lsb: 27
|
|
reset_value: '0'
|
|
width: 1
|
|
- PROT1:
|
|
access: rw
|
|
description: This information is provided to the peripheral during a DMA bus
|
|
access and indicates that the access is in user mode or privileged mode
|
|
lsb: 28
|
|
reset_value: '0'
|
|
width: 1
|
|
- PROT2:
|
|
access: rw
|
|
description: This information is provided to the peripheral during a DMA bus
|
|
access and indicates to the peripheral that the access is bufferable or
|
|
not bufferable
|
|
lsb: 29
|
|
reset_value: '0'
|
|
width: 1
|
|
- PROT3:
|
|
access: rw
|
|
description: This information is provided to the peripheral during a DMA bus
|
|
access and indicates to the peripheral that the access is cacheable or not
|
|
cacheable
|
|
lsb: 30
|
|
reset_value: '0'
|
|
width: 1
|
|
- I:
|
|
access: rw
|
|
description: Terminal count interrupt enable bit
|
|
lsb: 31
|
|
reset_value: '0'
|
|
width: 1
|
|
- GPDMA_C7CONTROL:
|
|
fields: !!omap
|
|
- TRANSFERSIZE:
|
|
access: rw
|
|
description: Transfer size in number of transfers
|
|
lsb: 0
|
|
reset_value: '0x00'
|
|
width: 12
|
|
- SBSIZE:
|
|
access: rw
|
|
description: Source burst size
|
|
lsb: 12
|
|
reset_value: '0x0'
|
|
width: 3
|
|
- DBSIZE:
|
|
access: rw
|
|
description: Destination burst size
|
|
lsb: 15
|
|
reset_value: '0x0'
|
|
width: 3
|
|
- SWIDTH:
|
|
access: rw
|
|
description: Source transfer width
|
|
lsb: 18
|
|
reset_value: '0x0'
|
|
width: 3
|
|
- DWIDTH:
|
|
access: rw
|
|
description: Destination transfer width
|
|
lsb: 21
|
|
reset_value: '0x0'
|
|
width: 3
|
|
- S:
|
|
access: rw
|
|
description: Source AHB master select
|
|
lsb: 24
|
|
reset_value: '0'
|
|
width: 1
|
|
- D:
|
|
access: rw
|
|
description: Destination AHB master select
|
|
lsb: 25
|
|
reset_value: '0'
|
|
width: 1
|
|
- SI:
|
|
access: rw
|
|
description: Source increment
|
|
lsb: 26
|
|
reset_value: '0'
|
|
width: 1
|
|
- DI:
|
|
access: rw
|
|
description: Destination increment
|
|
lsb: 27
|
|
reset_value: '0'
|
|
width: 1
|
|
- PROT1:
|
|
access: rw
|
|
description: This information is provided to the peripheral during a DMA bus
|
|
access and indicates that the access is in user mode or privileged mode
|
|
lsb: 28
|
|
reset_value: '0'
|
|
width: 1
|
|
- PROT2:
|
|
access: rw
|
|
description: This information is provided to the peripheral during a DMA bus
|
|
access and indicates to the peripheral that the access is bufferable or
|
|
not bufferable
|
|
lsb: 29
|
|
reset_value: '0'
|
|
width: 1
|
|
- PROT3:
|
|
access: rw
|
|
description: This information is provided to the peripheral during a DMA bus
|
|
access and indicates to the peripheral that the access is cacheable or not
|
|
cacheable
|
|
lsb: 30
|
|
reset_value: '0'
|
|
width: 1
|
|
- I:
|
|
access: rw
|
|
description: Terminal count interrupt enable bit
|
|
lsb: 31
|
|
reset_value: '0'
|
|
width: 1
|
|
- GPDMA_C0CONFIG:
|
|
fields: !!omap
|
|
- E:
|
|
access: rw
|
|
description: Channel enable
|
|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
|
|
- SRCPERIPHERAL:
|
|
access: rw
|
|
description: Source peripheral
|
|
lsb: 1
|
|
reset_value: ''
|
|
width: 5
|
|
- DESTPERIPHERAL:
|
|
access: rw
|
|
description: Destination peripheral
|
|
lsb: 6
|
|
reset_value: ''
|
|
width: 5
|
|
- FLOWCNTRL:
|
|
access: rw
|
|
description: Flow control and transfer type
|
|
lsb: 11
|
|
reset_value: ''
|
|
width: 3
|
|
- IE:
|
|
access: rw
|
|
description: Interrupt error mask
|
|
lsb: 14
|
|
reset_value: ''
|
|
width: 1
|
|
- ITC:
|
|
access: rw
|
|
description: Terminal count interrupt mask
|
|
lsb: 15
|
|
reset_value: ''
|
|
width: 1
|
|
- L:
|
|
access: rw
|
|
description: Lock
|
|
lsb: 16
|
|
reset_value: ''
|
|
width: 1
|
|
- A:
|
|
access: r
|
|
description: Active
|
|
lsb: 17
|
|
reset_value: ''
|
|
width: 1
|
|
- H:
|
|
access: rw
|
|
description: Halt
|
|
lsb: 18
|
|
reset_value: ''
|
|
width: 1
|
|
- GPDMA_C1CONFIG:
|
|
fields: !!omap
|
|
- E:
|
|
access: rw
|
|
description: Channel enable
|
|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
|
|
- SRCPERIPHERAL:
|
|
access: rw
|
|
description: Source peripheral
|
|
lsb: 1
|
|
reset_value: ''
|
|
width: 5
|
|
- DESTPERIPHERAL:
|
|
access: rw
|
|
description: Destination peripheral
|
|
lsb: 6
|
|
reset_value: ''
|
|
width: 5
|
|
- FLOWCNTRL:
|
|
access: rw
|
|
description: Flow control and transfer type
|
|
lsb: 11
|
|
reset_value: ''
|
|
width: 3
|
|
- IE:
|
|
access: rw
|
|
description: Interrupt error mask
|
|
lsb: 14
|
|
reset_value: ''
|
|
width: 1
|
|
- ITC:
|
|
access: rw
|
|
description: Terminal count interrupt mask
|
|
lsb: 15
|
|
reset_value: ''
|
|
width: 1
|
|
- L:
|
|
access: rw
|
|
description: Lock
|
|
lsb: 16
|
|
reset_value: ''
|
|
width: 1
|
|
- A:
|
|
access: r
|
|
description: Active
|
|
lsb: 17
|
|
reset_value: ''
|
|
width: 1
|
|
- H:
|
|
access: rw
|
|
description: Halt
|
|
lsb: 18
|
|
reset_value: ''
|
|
width: 1
|
|
- GPDMA_C2CONFIG:
|
|
fields: !!omap
|
|
- E:
|
|
access: rw
|
|
description: Channel enable
|
|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
|
|
- SRCPERIPHERAL:
|
|
access: rw
|
|
description: Source peripheral
|
|
lsb: 1
|
|
reset_value: ''
|
|
width: 5
|
|
- DESTPERIPHERAL:
|
|
access: rw
|
|
description: Destination peripheral
|
|
lsb: 6
|
|
reset_value: ''
|
|
width: 5
|
|
- FLOWCNTRL:
|
|
access: rw
|
|
description: Flow control and transfer type
|
|
lsb: 11
|
|
reset_value: ''
|
|
width: 3
|
|
- IE:
|
|
access: rw
|
|
description: Interrupt error mask
|
|
lsb: 14
|
|
reset_value: ''
|
|
width: 1
|
|
- ITC:
|
|
access: rw
|
|
description: Terminal count interrupt mask
|
|
lsb: 15
|
|
reset_value: ''
|
|
width: 1
|
|
- L:
|
|
access: rw
|
|
description: Lock
|
|
lsb: 16
|
|
reset_value: ''
|
|
width: 1
|
|
- A:
|
|
access: r
|
|
description: Active
|
|
lsb: 17
|
|
reset_value: ''
|
|
width: 1
|
|
- H:
|
|
access: rw
|
|
description: Halt
|
|
lsb: 18
|
|
reset_value: ''
|
|
width: 1
|
|
- GPDMA_C3CONFIG:
|
|
fields: !!omap
|
|
- E:
|
|
access: rw
|
|
description: Channel enable
|
|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
|
|
- SRCPERIPHERAL:
|
|
access: rw
|
|
description: Source peripheral
|
|
lsb: 1
|
|
reset_value: ''
|
|
width: 5
|
|
- DESTPERIPHERAL:
|
|
access: rw
|
|
description: Destination peripheral
|
|
lsb: 6
|
|
reset_value: ''
|
|
width: 5
|
|
- FLOWCNTRL:
|
|
access: rw
|
|
description: Flow control and transfer type
|
|
lsb: 11
|
|
reset_value: ''
|
|
width: 3
|
|
- IE:
|
|
access: rw
|
|
description: Interrupt error mask
|
|
lsb: 14
|
|
reset_value: ''
|
|
width: 1
|
|
- ITC:
|
|
access: rw
|
|
description: Terminal count interrupt mask
|
|
lsb: 15
|
|
reset_value: ''
|
|
width: 1
|
|
- L:
|
|
access: rw
|
|
description: Lock
|
|
lsb: 16
|
|
reset_value: ''
|
|
width: 1
|
|
- A:
|
|
access: r
|
|
description: Active
|
|
lsb: 17
|
|
reset_value: ''
|
|
width: 1
|
|
- H:
|
|
access: rw
|
|
description: Halt
|
|
lsb: 18
|
|
reset_value: ''
|
|
width: 1
|
|
- GPDMA_C4CONFIG:
|
|
fields: !!omap
|
|
- E:
|
|
access: rw
|
|
description: Channel enable
|
|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
|
|
- SRCPERIPHERAL:
|
|
access: rw
|
|
description: Source peripheral
|
|
lsb: 1
|
|
reset_value: ''
|
|
width: 5
|
|
- DESTPERIPHERAL:
|
|
access: rw
|
|
description: Destination peripheral
|
|
lsb: 6
|
|
reset_value: ''
|
|
width: 5
|
|
- FLOWCNTRL:
|
|
access: rw
|
|
description: Flow control and transfer type
|
|
lsb: 11
|
|
reset_value: ''
|
|
width: 3
|
|
- IE:
|
|
access: rw
|
|
description: Interrupt error mask
|
|
lsb: 14
|
|
reset_value: ''
|
|
width: 1
|
|
- ITC:
|
|
access: rw
|
|
description: Terminal count interrupt mask
|
|
lsb: 15
|
|
reset_value: ''
|
|
width: 1
|
|
- L:
|
|
access: rw
|
|
description: Lock
|
|
lsb: 16
|
|
reset_value: ''
|
|
width: 1
|
|
- A:
|
|
access: r
|
|
description: Active
|
|
lsb: 17
|
|
reset_value: ''
|
|
width: 1
|
|
- H:
|
|
access: rw
|
|
description: Halt
|
|
lsb: 18
|
|
reset_value: ''
|
|
width: 1
|
|
- GPDMA_C5CONFIG:
|
|
fields: !!omap
|
|
- E:
|
|
access: rw
|
|
description: Channel enable
|
|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
|
|
- SRCPERIPHERAL:
|
|
access: rw
|
|
description: Source peripheral
|
|
lsb: 1
|
|
reset_value: ''
|
|
width: 5
|
|
- DESTPERIPHERAL:
|
|
access: rw
|
|
description: Destination peripheral
|
|
lsb: 6
|
|
reset_value: ''
|
|
width: 5
|
|
- FLOWCNTRL:
|
|
access: rw
|
|
description: Flow control and transfer type
|
|
lsb: 11
|
|
reset_value: ''
|
|
width: 3
|
|
- IE:
|
|
access: rw
|
|
description: Interrupt error mask
|
|
lsb: 14
|
|
reset_value: ''
|
|
width: 1
|
|
- ITC:
|
|
access: rw
|
|
description: Terminal count interrupt mask
|
|
lsb: 15
|
|
reset_value: ''
|
|
width: 1
|
|
- L:
|
|
access: rw
|
|
description: Lock
|
|
lsb: 16
|
|
reset_value: ''
|
|
width: 1
|
|
- A:
|
|
access: r
|
|
description: Active
|
|
lsb: 17
|
|
reset_value: ''
|
|
width: 1
|
|
- H:
|
|
access: rw
|
|
description: Halt
|
|
lsb: 18
|
|
reset_value: ''
|
|
width: 1
|
|
- GPDMA_C6CONFIG:
|
|
fields: !!omap
|
|
- E:
|
|
access: rw
|
|
description: Channel enable
|
|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
|
|
- SRCPERIPHERAL:
|
|
access: rw
|
|
description: Source peripheral
|
|
lsb: 1
|
|
reset_value: ''
|
|
width: 5
|
|
- DESTPERIPHERAL:
|
|
access: rw
|
|
description: Destination peripheral
|
|
lsb: 6
|
|
reset_value: ''
|
|
width: 5
|
|
- FLOWCNTRL:
|
|
access: rw
|
|
description: Flow control and transfer type
|
|
lsb: 11
|
|
reset_value: ''
|
|
width: 3
|
|
- IE:
|
|
access: rw
|
|
description: Interrupt error mask
|
|
lsb: 14
|
|
reset_value: ''
|
|
width: 1
|
|
- ITC:
|
|
access: rw
|
|
description: Terminal count interrupt mask
|
|
lsb: 15
|
|
reset_value: ''
|
|
width: 1
|
|
- L:
|
|
access: rw
|
|
description: Lock
|
|
lsb: 16
|
|
reset_value: ''
|
|
width: 1
|
|
- A:
|
|
access: r
|
|
description: Active
|
|
lsb: 17
|
|
reset_value: ''
|
|
width: 1
|
|
- H:
|
|
access: rw
|
|
description: Halt
|
|
lsb: 18
|
|
reset_value: ''
|
|
width: 1
|
|
- GPDMA_C7CONFIG:
|
|
fields: !!omap
|
|
- E:
|
|
access: rw
|
|
description: Channel enable
|
|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
|
|
- SRCPERIPHERAL:
|
|
access: rw
|
|
description: Source peripheral
|
|
lsb: 1
|
|
reset_value: ''
|
|
width: 5
|
|
- DESTPERIPHERAL:
|
|
access: rw
|
|
description: Destination peripheral
|
|
lsb: 6
|
|
reset_value: ''
|
|
width: 5
|
|
- FLOWCNTRL:
|
|
access: rw
|
|
description: Flow control and transfer type
|
|
lsb: 11
|
|
reset_value: ''
|
|
width: 3
|
|
- IE:
|
|
access: rw
|
|
description: Interrupt error mask
|
|
lsb: 14
|
|
reset_value: ''
|
|
width: 1
|
|
- ITC:
|
|
access: rw
|
|
description: Terminal count interrupt mask
|
|
lsb: 15
|
|
reset_value: ''
|
|
width: 1
|
|
- L:
|
|
access: rw
|
|
description: Lock
|
|
lsb: 16
|
|
reset_value: ''
|
|
width: 1
|
|
- A:
|
|
access: r
|
|
description: Active
|
|
lsb: 17
|
|
reset_value: ''
|
|
width: 1
|
|
- H:
|
|
access: rw
|
|
description: Halt
|
|
lsb: 18
|
|
reset_value: ''
|
|
width: 1
|