Mirror von
https://github.com/henrydcase/pqc.git
synchronisiert 2024-11-22 15:39:07 +00:00
NTRU: inline the one call that needed @plt
Dieser Commit ist enthalten in:
John M. Schanck
Ursprung
a008d4ad21
Commit
4c268aae14
@ -23,9 +23,9 @@ auxiliary-submitters:
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- Zhenfei Zhang
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implementations:
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- name: clean
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version: https://github.com/jschanck/ntru/tree/b43afe59 reference implementation
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version: https://github.com/jschanck/ntru/tree/ff3c84e1 reference implementation
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- name: avx2
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version: https://github.com/jschanck/ntru/tree/b43afe59 avx2 implementation
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version: https://github.com/jschanck/ntru/tree/ff3c84e1 avx2 implementation
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supported_platforms:
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- architecture: x86_64
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operating_systems:
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@ -23,9 +23,9 @@ auxiliary-submitters:
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- Zhenfei Zhang
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||||
implementations:
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- name: clean
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||||
version: https://github.com/jschanck/ntru/tree/b43afe59 reference implementation
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version: https://github.com/jschanck/ntru/tree/ff3c84e1 reference implementation
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- name: avx2
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version: https://github.com/jschanck/ntru/tree/b43afe59 avx2 implementation
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version: https://github.com/jschanck/ntru/tree/ff3c84e1 avx2 implementation
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supported_platforms:
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- architecture: x86_64
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operating_systems:
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@ -23,9 +23,9 @@ auxiliary-submitters:
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- Zhenfei Zhang
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||||
implementations:
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- name: clean
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||||
version: https://github.com/jschanck/ntru/tree/b43afe59 reference implementation
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version: https://github.com/jschanck/ntru/tree/ff3c84e1 reference implementation
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- name: avx2
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version: https://github.com/jschanck/ntru/tree/b43afe59 avx2 implementation
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version: https://github.com/jschanck/ntru/tree/ff3c84e1 avx2 implementation
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supported_platforms:
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- architecture: x86_64
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operating_systems:
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@ -23,9 +23,9 @@ auxiliary-submitters:
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- Zhenfei Zhang
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||||
implementations:
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||||
- name: clean
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||||
version: https://github.com/jschanck/ntru/tree/b43afe59 reference implementation
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version: https://github.com/jschanck/ntru/tree/ff3c84e1 reference implementation
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- name: avx2
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version: https://github.com/jschanck/ntru/tree/b43afe59 avx2 implementation
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version: https://github.com/jschanck/ntru/tree/ff3c84e1 avx2 implementation
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supported_platforms:
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- architecture: x86_64
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operating_systems:
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@ -4,7 +4,7 @@ LIB=libntruhrss701_avx2.a
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HEADERS=api.h cmov.h owcpa.h params.h poly.h poly_r2_inv.h sample.h
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OBJECTS=cmov.o kem.o owcpa.o pack3.o packq.o poly.o poly_r2_inv.o sample.o sample_iid.o \
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square_1_701_patience.o square_3_701_patience.o square_6_701_patience.o square_12_701_shufbytes.o square_15_701_shufbytes.o square_27_701_shufbytes.o square_42_701_shufbytes.o square_84_701_shufbytes.o square_168_701_shufbytes.o square_336_701_shufbytes.o \
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poly_mod_3_Phi_n.o poly_mod_q_Phi_n.o poly_r2_mul.o poly_rq_mul.o poly_rq_mul_x_minus_1.o poly_rq_to_s3.o poly_s3_inv.o poly_s3_to_rq.o vec32_sample_iid.o
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poly_lift.o poly_mod_3_Phi_n.o poly_mod_q_Phi_n.o poly_r2_mul.o poly_rq_mul.o poly_rq_to_s3.o poly_s3_inv.o vec32_sample_iid.o
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CFLAGS=-O3 -mavx2 -mbmi2 -Wall -Wextra -Wpedantic -Wvla -Werror -Wredundant-decls -Wmissing-prototypes -std=c99 -I../../../common $(EXTRAFLAGS)
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@ -288,6 +288,90 @@ mask_n:
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.word 0
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.word 0
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.word 0
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mask_mod8192:
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.word 8191
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.word 8191
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.word 8191
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.word 8191
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.word 8191
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.word 8191
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.word 8191
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.word 8191
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.word 8191
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.word 8191
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.word 8191
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.word 8191
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.word 8191
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.word 8191
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.word 8191
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.word 8191
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mask_mod8192_omit_lowest:
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.word 0
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.word 8191
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.word 8191
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.word 8191
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.word 8191
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.word 8191
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.word 8191
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.word 8191
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.word 8191
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.word 8191
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.word 8191
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.word 8191
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.word 8191
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.word 8191
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.word 8191
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.word 8191
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mask_mod8192_only_lowest:
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.word 8191
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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shuf_5_to_0_zerorest:
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.byte 10
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.byte 11
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.byte 255
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.byte 255
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.byte 255
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.byte 255
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.byte 255
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.byte 255
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.byte 255
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.byte 255
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.byte 255
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.byte 255
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.byte 255
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.byte 255
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.byte 255
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.byte 255
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.byte 255
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.byte 255
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.byte 255
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.byte 255
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.byte 255
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.byte 255
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.byte 255
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.byte 255
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.byte 255
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.byte 255
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.byte 255
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.byte 255
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.byte 255
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.byte 255
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.byte 255
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.byte 255
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.text
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.global PQCLEAN_NTRUHRSS701_AVX2_poly_lift
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.global _PQCLEAN_NTRUHRSS701_AVX2_poly_lift
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@ -3112,7 +3196,190 @@ vpand const_modq(%rip), %ymm2, %ymm2
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vpand const_1s(%rip), %ymm3, %ymm3
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vpor %ymm3, %ymm2, %ymm3
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vmovdqa %ymm3, 1376(%rsp)
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mov %rsp, %rsi
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call PQCLEAN_NTRUHRSS701_AVX2_poly_Rq_mul_x_minus_1@plt
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vmovdqu 1374(%rsp), %ymm0
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vpsubw 1376(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 1376(%rdi)
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vextracti128 $1, %ymm0, %xmm4
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vpshufb shuf_5_to_0_zerorest(%rip), %ymm4, %ymm4
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vpsubw 0(%rsp), %ymm4, %ymm4
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vpand mask_mod8192_only_lowest(%rip), %ymm4, %ymm4
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vmovdqu 1342(%rsp), %ymm0
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vpsubw 1344(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 1344(%rdi)
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vmovdqu 1310(%rsp), %ymm0
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vpsubw 1312(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 1312(%rdi)
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vmovdqu 1278(%rsp), %ymm0
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vpsubw 1280(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 1280(%rdi)
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vmovdqu 1246(%rsp), %ymm0
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vpsubw 1248(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 1248(%rdi)
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vmovdqu 1214(%rsp), %ymm0
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vpsubw 1216(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 1216(%rdi)
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vmovdqu 1182(%rsp), %ymm0
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vpsubw 1184(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 1184(%rdi)
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vmovdqu 1150(%rsp), %ymm0
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vpsubw 1152(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 1152(%rdi)
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vmovdqu 1118(%rsp), %ymm0
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vpsubw 1120(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 1120(%rdi)
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vmovdqu 1086(%rsp), %ymm0
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vpsubw 1088(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 1088(%rdi)
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vmovdqu 1054(%rsp), %ymm0
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vpsubw 1056(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 1056(%rdi)
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vmovdqu 1022(%rsp), %ymm0
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vpsubw 1024(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 1024(%rdi)
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vmovdqu 990(%rsp), %ymm0
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vpsubw 992(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 992(%rdi)
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vmovdqu 958(%rsp), %ymm0
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vpsubw 960(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 960(%rdi)
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vmovdqu 926(%rsp), %ymm0
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vpsubw 928(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 928(%rdi)
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vmovdqu 894(%rsp), %ymm0
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vpsubw 896(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 896(%rdi)
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vmovdqu 862(%rsp), %ymm0
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vpsubw 864(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 864(%rdi)
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vmovdqu 830(%rsp), %ymm0
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vpsubw 832(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 832(%rdi)
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vmovdqu 798(%rsp), %ymm0
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vpsubw 800(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 800(%rdi)
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vmovdqu 766(%rsp), %ymm0
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vpsubw 768(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 768(%rdi)
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vmovdqu 734(%rsp), %ymm0
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vpsubw 736(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 736(%rdi)
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vmovdqu 702(%rsp), %ymm0
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vpsubw 704(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 704(%rdi)
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vmovdqu 670(%rsp), %ymm0
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vpsubw 672(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 672(%rdi)
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vmovdqu 638(%rsp), %ymm0
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vpsubw 640(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 640(%rdi)
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vmovdqu 606(%rsp), %ymm0
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vpsubw 608(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 608(%rdi)
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vmovdqu 574(%rsp), %ymm0
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vpsubw 576(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 576(%rdi)
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vmovdqu 542(%rsp), %ymm0
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vpsubw 544(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 544(%rdi)
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vmovdqu 510(%rsp), %ymm0
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vpsubw 512(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 512(%rdi)
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vmovdqu 478(%rsp), %ymm0
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vpsubw 480(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 480(%rdi)
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vmovdqu 446(%rsp), %ymm0
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vpsubw 448(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 448(%rdi)
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vmovdqu 414(%rsp), %ymm0
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vpsubw 416(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 416(%rdi)
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vmovdqu 382(%rsp), %ymm0
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vpsubw 384(%rsp), %ymm0, %ymm1
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vpand mask_mod8192(%rip), %ymm1, %ymm1
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vmovdqa %ymm1, 384(%rdi)
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vmovdqu 350(%rsp), %ymm0
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vpsubw 352(%rsp), %ymm0, %ymm1
|
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vpand mask_mod8192(%rip), %ymm1, %ymm1
|
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vmovdqa %ymm1, 352(%rdi)
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vmovdqu 318(%rsp), %ymm0
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vpsubw 320(%rsp), %ymm0, %ymm1
|
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vpand mask_mod8192(%rip), %ymm1, %ymm1
|
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vmovdqa %ymm1, 320(%rdi)
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vmovdqu 286(%rsp), %ymm0
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vpsubw 288(%rsp), %ymm0, %ymm1
|
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vpand mask_mod8192(%rip), %ymm1, %ymm1
|
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vmovdqa %ymm1, 288(%rdi)
|
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vmovdqu 254(%rsp), %ymm0
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vpsubw 256(%rsp), %ymm0, %ymm1
|
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vpand mask_mod8192(%rip), %ymm1, %ymm1
|
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vmovdqa %ymm1, 256(%rdi)
|
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vmovdqu 222(%rsp), %ymm0
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vpsubw 224(%rsp), %ymm0, %ymm1
|
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vpand mask_mod8192(%rip), %ymm1, %ymm1
|
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vmovdqa %ymm1, 224(%rdi)
|
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vmovdqu 190(%rsp), %ymm0
|
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vpsubw 192(%rsp), %ymm0, %ymm1
|
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vpand mask_mod8192(%rip), %ymm1, %ymm1
|
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vmovdqa %ymm1, 192(%rdi)
|
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vmovdqu 158(%rsp), %ymm0
|
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vpsubw 160(%rsp), %ymm0, %ymm1
|
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vpand mask_mod8192(%rip), %ymm1, %ymm1
|
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vmovdqa %ymm1, 160(%rdi)
|
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vmovdqu 126(%rsp), %ymm0
|
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vpsubw 128(%rsp), %ymm0, %ymm1
|
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vpand mask_mod8192(%rip), %ymm1, %ymm1
|
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vmovdqa %ymm1, 128(%rdi)
|
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vmovdqu 94(%rsp), %ymm0
|
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vpsubw 96(%rsp), %ymm0, %ymm1
|
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vpand mask_mod8192(%rip), %ymm1, %ymm1
|
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vmovdqa %ymm1, 96(%rdi)
|
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vmovdqu 62(%rsp), %ymm0
|
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vpsubw 64(%rsp), %ymm0, %ymm1
|
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vpand mask_mod8192(%rip), %ymm1, %ymm1
|
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vmovdqa %ymm1, 64(%rdi)
|
||||
vmovdqu 30(%rsp), %ymm0
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vpsubw 32(%rsp), %ymm0, %ymm1
|
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vpand mask_mod8192(%rip), %ymm1, %ymm1
|
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vmovdqa %ymm1, 32(%rdi)
|
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vmovdqa 0(%rsp), %ymm3
|
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vpsrlq $48, %ymm3, %ymm0
|
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vpermq $147, %ymm0, %ymm0
|
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vpsllq $16, %ymm3, %ymm2
|
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vpxor %ymm0, %ymm2, %ymm2
|
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vpsubw %ymm3, %ymm2, %ymm3
|
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vpand mask_mod8192_omit_lowest(%rip), %ymm3, %ymm3
|
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vpxor %ymm3, %ymm4, %ymm3
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vmovdqa %ymm3, 0(%rdi)
|
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mov %r8, %rsp
|
||||
ret
|
||||
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