Support AVX-512 instructions with a writemask in delocate.
AVX-512 adds a new text instruction syntax to x86-64 assembly to specify the writemask registers and the merge-masking vs zeroing-masking signal. This change causes these tokens to be passed through. Patch by Jeff McDonald. Change-Id: Ib15b15ac684183cc5fba329a176b63b477bc24a3 Reviewed-on: https://boringssl-review.googlesource.com/24945 Commit-Queue: David Benjamin <davidben@google.com> Reviewed-by: David Benjamin <davidben@google.com> CQ-Verified: CQ bot account: commit-bot@chromium.org <commit-bot@chromium.org>
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@ -55,7 +55,7 @@ SymbolName <- [[A-Z._]][[A-Z.0-9$_]]*
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LocalSymbol <- '.L' [[A-Z.0-9$_]]+
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LocalLabel <- [0-9][0-9$]*
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LocalLabelRef <- [0-9][0-9$]*[bf]
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Instruction <- InstructionName (WS InstructionArg ((WS? ',' WS?) InstructionArg)*)?
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Instruction <- InstructionName (WS InstructionArg ((WS? ',' WS?) InstructionArg)*)? (WS? '{' InstructionArg '}')*
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InstructionName <- [[A-Z]][[A-Z0-9]]* [.+\-]?
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InstructionArg <- IndirectionIndicator? (RegisterOrConstant / LocalLabelRef / TOCRefHigh / TOCRefLow / MemoryRef)
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TOCRefHigh <- '.TOC.-' ('0b' / ('.L' [a-zA-Z_0-9]+)) "@ha"
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Load Diff
2
util/fipstools/testdata/x86_64-Basic/in.s
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2
util/fipstools/testdata/x86_64-Basic/in.s
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@ -35,6 +35,8 @@ foo:
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vpclmulqdq $0x00,%xmm6,%xmm3,%xmm3
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vpxor %xmm0,%xmm1,%xmm4
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vpxor %xmm4,%xmm3,%xmm3
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vmovdqu8 %ymm1,%ymm6{%k1}{z}
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vmovdqu8 %ymm2,%ymm4{%k3}
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.byte 0xf3,0xc3
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movq %rax, %rbx # Comments can be on the same line as an instruction.
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.L3: # Or on the same line as a label.
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util/fipstools/testdata/x86_64-Basic/out.s
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util/fipstools/testdata/x86_64-Basic/out.s
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@ -38,6 +38,8 @@ foo:
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vpclmulqdq $0x00,%xmm6,%xmm3,%xmm3
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vpxor %xmm0,%xmm1,%xmm4
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vpxor %xmm4,%xmm3,%xmm3
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vmovdqu8 %ymm1,%ymm6{%k1}{z}
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vmovdqu8 %ymm2,%ymm4{%k3}
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.byte 0xf3,0xc3
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movq %rax, %rbx # Comments can be on the same line as an instruction.
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.L3:
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