97999919bb
We are leaking asm symbols in Android builds because the asm code isn't affected by -fvisibility=hidden. This change hides all asm symbols. This assumes that no asm symbols are public API and that should be true. Some points to note: In crypto/rc4/asm/rc4-md5-x86_64.pl there are |RC4_set_key| and |RC4_options| functions which aren't getting marked as hidden. That's because those functions aren't actually ever generated. (I'm just trying to minimise drift with upstream here.) In crypto/rc4/asm/rc4-x86_64.pl there's |RC4_options| which is "public" API, except that we've never had it in the header files. So I've just deleted it. Since we have an internal caller, we'll probably have to put it back in the future, but it can just be done in rc4.c to save problems. BUG=448386 Change-Id: I3846617a0e3d73ec9e5ec3638a53364adbbc6260 Reviewed-on: https://boringssl-review.googlesource.com/3520 Reviewed-by: David Benjamin <davidben@chromium.org> Reviewed-by: Adam Langley <agl@google.com>
169 lines
3.9 KiB
Raku
169 lines
3.9 KiB
Raku
#!/usr/bin/env perl
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$flavour = shift;
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$output = shift;
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if ($flavour =~ /\./) { $output = $flavour; undef $flavour; }
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$win64=0; $win64=1 if ($flavour =~ /[nm]asm|mingw64/ || $output =~ /\.asm$/);
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$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
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( $xlate="${dir}x86_64-xlate.pl" and -f $xlate ) or
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( $xlate="${dir}perlasm/x86_64-xlate.pl" and -f $xlate) or
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die "can't locate x86_64-xlate.pl";
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open OUT,"| \"$^X\" $xlate $flavour $output";
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*STDOUT=*OUT;
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($arg1,$arg2,$arg3,$arg4)=$win64?("%rcx","%rdx","%r8", "%r9") : # Win64 order
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("%rdi","%rsi","%rdx","%rcx"); # Unix order
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print<<___;
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.text
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.globl OPENSSL_ia32_cpuid
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.type OPENSSL_ia32_cpuid,\@function,1
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.hidden OPENSSL_ia32_cpuid
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.align 16
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OPENSSL_ia32_cpuid:
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# On Windows, $arg1 is rcx, but that will be clobbered. So make Windows
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# use the same register as Unix.
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mov $arg1,%rdi
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mov %rbx,%r8 # save %rbx
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xor %eax,%eax
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mov %eax,8(%rdi) # clear 3rd word
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cpuid
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mov %eax,%r11d # max value for standard query level
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xor %eax,%eax
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cmp \$0x756e6547,%ebx # "Genu"
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setne %al
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mov %eax,%r9d
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cmp \$0x49656e69,%edx # "ineI"
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setne %al
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or %eax,%r9d
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cmp \$0x6c65746e,%ecx # "ntel"
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setne %al
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or %eax,%r9d # 0 indicates Intel CPU
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jz .Lintel
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cmp \$0x68747541,%ebx # "Auth"
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setne %al
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mov %eax,%r10d
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cmp \$0x69746E65,%edx # "enti"
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setne %al
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or %eax,%r10d
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cmp \$0x444D4163,%ecx # "cAMD"
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setne %al
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or %eax,%r10d # 0 indicates AMD CPU
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jnz .Lintel
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# AMD specific
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# See http://developer.amd.com/wordpress/media/2012/10/254811.pdf (1)
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mov \$0x80000000,%eax
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cpuid
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# Returns "The largest CPUID extended function input value supported by
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# the processor implementation." in EAX.
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cmp \$0x80000001,%eax
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jb .Lintel
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mov %eax,%r10d
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mov \$0x80000001,%eax
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cpuid
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# Returns feature bits in ECX. See page 20 of [1].
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# TODO(fork): I think this should be a MOV.
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or %ecx,%r9d
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and \$0x00000801,%r9d # isolate AMD XOP bit, 1<<11
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cmp \$0x80000008,%r10d
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jb .Lintel
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mov \$0x80000008,%eax
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cpuid
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# Returns APIC ID and number of cores in ECX. See page 27 of [1].
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movzb %cl,%r10 # number of cores - 1
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inc %r10 # number of cores
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mov \$1,%eax
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cpuid
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# See page 13 of [1].
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bt \$28,%edx # test hyper-threading bit
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jnc .Lgeneric
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shr \$16,%ebx # number of logical processors
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cmp %r10b,%bl
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ja .Lgeneric
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and \$0xefffffff,%edx # Clear hyper-threading bit.
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jmp .Lgeneric
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.Lintel:
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cmp \$4,%r11d
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mov \$-1,%r10d
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jb .Lnocacheinfo
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mov \$4,%eax
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mov \$0,%ecx # query L1D
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cpuid
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mov %eax,%r10d
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shr \$14,%r10d
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and \$0xfff,%r10d # number of cores -1 per L1D
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cmp \$7,%r11d
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jb .Lnocacheinfo
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mov \$7,%eax
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xor %ecx,%ecx
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cpuid
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mov %ebx,8(%rdi)
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.Lnocacheinfo:
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mov \$1,%eax
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cpuid
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# Gets feature information. See table 3-21 in the Intel manual.
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and \$0xbfefffff,%edx # force reserved bits to 0
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cmp \$0,%r9d
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jne .Lnotintel
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or \$0x40000000,%edx # set reserved bit#30 on Intel CPUs
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and \$15,%ah
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cmp \$15,%ah # examine Family ID
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jne .Lnotintel
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or \$0x00100000,%edx # set reserved bit#20 to engage RC4_CHAR
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.Lnotintel:
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bt \$28,%edx # test hyper-threading bit
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jnc .Lgeneric
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and \$0xefffffff,%edx # ~(1<<28) - clear hyper-threading.
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cmp \$0,%r10d
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je .Lgeneric
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or \$0x10000000,%edx # 1<<28
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shr \$16,%ebx
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cmp \$1,%bl # see if cache is shared
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ja .Lgeneric
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and \$0xefffffff,%edx # ~(1<<28)
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.Lgeneric:
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and \$0x00000800,%r9d # isolate AMD XOP flag
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and \$0xfffff7ff,%ecx
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or %ecx,%r9d # merge AMD XOP flag
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mov %edx,%r10d # %r9d:%r10d is copy of %ecx:%edx
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bt \$27,%r9d # check OSXSAVE bit
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jnc .Lclear_avx
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xor %ecx,%ecx # XCR0
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.byte 0x0f,0x01,0xd0 # xgetbv
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and \$6,%eax # isolate XMM and YMM state support
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cmp \$6,%eax
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je .Ldone
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.Lclear_avx:
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mov \$0xefffe7ff,%eax # ~(1<<28|1<<12|1<<11)
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and %eax,%r9d # clear AVX, FMA and AMD XOP bits
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andl \$0xffffffdf,8(%rdi) # cleax AVX2, ~(1<<5)
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.Ldone:
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movl %r9d,4(%rdi)
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movl %r10d,0(%rdi)
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mov %r8,%rbx # restore %rbx
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ret
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.size OPENSSL_ia32_cpuid,.-OPENSSL_ia32_cpuid
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___
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close STDOUT; # flush
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