選択できるのは25トピックまでです。 トピックは、先頭が英数字で、英数字とダッシュ('-')を使用した35文字以内のものにしてください。

1年前
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  1. !!omap
  2. - I2C0_CONSET:
  3. fields: !!omap
  4. - AA:
  5. access: rw
  6. description: Assert acknowledge flag
  7. lsb: 2
  8. reset_value: '0'
  9. width: 1
  10. - SI:
  11. access: rw
  12. description: I2C interrupt flag
  13. lsb: 3
  14. reset_value: '0'
  15. width: 1
  16. - STO:
  17. access: rw
  18. description: STOP flag
  19. lsb: 4
  20. reset_value: '0'
  21. width: 1
  22. - STA:
  23. access: rw
  24. description: START flag
  25. lsb: 5
  26. reset_value: '0'
  27. width: 1
  28. - I2EN:
  29. access: rw
  30. description: I2C interface enable
  31. lsb: 6
  32. reset_value: '0'
  33. width: 1
  34. - I2C1_CONSET:
  35. fields: !!omap
  36. - AA:
  37. access: rw
  38. description: Assert acknowledge flag
  39. lsb: 2
  40. reset_value: '0'
  41. width: 1
  42. - SI:
  43. access: rw
  44. description: I2C interrupt flag
  45. lsb: 3
  46. reset_value: '0'
  47. width: 1
  48. - STO:
  49. access: rw
  50. description: STOP flag
  51. lsb: 4
  52. reset_value: '0'
  53. width: 1
  54. - STA:
  55. access: rw
  56. description: START flag
  57. lsb: 5
  58. reset_value: '0'
  59. width: 1
  60. - I2EN:
  61. access: rw
  62. description: I2C interface enable
  63. lsb: 6
  64. reset_value: '0'
  65. width: 1
  66. - I2C0_STAT:
  67. fields: !!omap
  68. - STATUS:
  69. access: r
  70. description: These bits give the actual status information about the I2C interface
  71. lsb: 3
  72. reset_value: '0x1f'
  73. width: 5
  74. - I2C1_STAT:
  75. fields: !!omap
  76. - STATUS:
  77. access: r
  78. description: These bits give the actual status information about the I2C interface
  79. lsb: 3
  80. reset_value: '0x1f'
  81. width: 5
  82. - I2C0_DAT:
  83. fields: !!omap
  84. - DATA:
  85. access: rw
  86. description: This register holds data values that have been received or are
  87. to be transmitted
  88. lsb: 0
  89. reset_value: '0'
  90. width: 8
  91. - I2C1_DAT:
  92. fields: !!omap
  93. - DATA:
  94. access: rw
  95. description: This register holds data values that have been received or are
  96. to be transmitted
  97. lsb: 0
  98. reset_value: '0'
  99. width: 8
  100. - I2C0_ADR0:
  101. fields: !!omap
  102. - GC:
  103. access: rw
  104. description: General Call enable bit
  105. lsb: 0
  106. reset_value: '0'
  107. width: 1
  108. - ADDRESS:
  109. access: rw
  110. description: The I2C device address for slave mode
  111. lsb: 1
  112. reset_value: '0'
  113. width: 7
  114. - I2C1_ADR0:
  115. fields: !!omap
  116. - GC:
  117. access: rw
  118. description: General Call enable bit
  119. lsb: 0
  120. reset_value: '0'
  121. width: 1
  122. - ADDRESS:
  123. access: rw
  124. description: The I2C device address for slave mode
  125. lsb: 1
  126. reset_value: '0'
  127. width: 7
  128. - I2C0_SCLH:
  129. fields: !!omap
  130. - SCLH:
  131. access: rw
  132. description: Count for SCL HIGH time period selection
  133. lsb: 0
  134. reset_value: '0x0004'
  135. width: 16
  136. - I2C1_SCLH:
  137. fields: !!omap
  138. - SCLH:
  139. access: rw
  140. description: Count for SCL HIGH time period selection
  141. lsb: 0
  142. reset_value: '0x0004'
  143. width: 16
  144. - I2C0_SCLL:
  145. fields: !!omap
  146. - SCLL:
  147. access: rw
  148. description: Count for SCL LOW time period selection
  149. lsb: 0
  150. reset_value: '0x0004'
  151. width: 16
  152. - I2C1_SCLL:
  153. fields: !!omap
  154. - SCLL:
  155. access: rw
  156. description: Count for SCL LOW time period selection
  157. lsb: 0
  158. reset_value: '0x0004'
  159. width: 16
  160. - I2C0_CONCLR:
  161. fields: !!omap
  162. - AAC:
  163. access: w
  164. description: Assert acknowledge Clear bit
  165. lsb: 2
  166. reset_value: '0'
  167. width: 1
  168. - SIC:
  169. access: w
  170. description: I2C interrupt Clear bit
  171. lsb: 3
  172. reset_value: '0'
  173. width: 1
  174. - STAC:
  175. access: w
  176. description: START flag Clear bit
  177. lsb: 5
  178. reset_value: '0'
  179. width: 1
  180. - I2ENC:
  181. access: w
  182. description: I2C interface Disable bit
  183. lsb: 6
  184. reset_value: '0'
  185. width: 1
  186. - I2C1_CONCLR:
  187. fields: !!omap
  188. - AAC:
  189. access: w
  190. description: Assert acknowledge Clear bit
  191. lsb: 2
  192. reset_value: '0'
  193. width: 1
  194. - SIC:
  195. access: w
  196. description: I2C interrupt Clear bit
  197. lsb: 3
  198. reset_value: '0'
  199. width: 1
  200. - STAC:
  201. access: w
  202. description: START flag Clear bit
  203. lsb: 5
  204. reset_value: '0'
  205. width: 1
  206. - I2ENC:
  207. access: w
  208. description: I2C interface Disable bit
  209. lsb: 6
  210. reset_value: '0'
  211. width: 1
  212. - I2C0_MMCTRL:
  213. fields: !!omap
  214. - MM_ENA:
  215. access: rw
  216. description: Monitor mode enable
  217. lsb: 0
  218. reset_value: '0'
  219. width: 1
  220. - ENA_SCL:
  221. access: rw
  222. description: SCL output enable
  223. lsb: 1
  224. reset_value: '0'
  225. width: 1
  226. - MATCH_ALL:
  227. access: rw
  228. description: Select interrupt register match
  229. lsb: 2
  230. reset_value: '0'
  231. width: 1
  232. - I2C1_MMCTRL:
  233. fields: !!omap
  234. - MM_ENA:
  235. access: rw
  236. description: Monitor mode enable
  237. lsb: 0
  238. reset_value: '0'
  239. width: 1
  240. - ENA_SCL:
  241. access: rw
  242. description: SCL output enable
  243. lsb: 1
  244. reset_value: '0'
  245. width: 1
  246. - MATCH_ALL:
  247. access: rw
  248. description: Select interrupt register match
  249. lsb: 2
  250. reset_value: '0'
  251. width: 1
  252. - I2C0_ADR1:
  253. fields: !!omap
  254. - GC:
  255. access: rw
  256. description: General Call enable bit
  257. lsb: 0
  258. reset_value: '0'
  259. width: 1
  260. - ADDRESS:
  261. access: rw
  262. description: The I2C device address for slave mode
  263. lsb: 1
  264. reset_value: '0'
  265. width: 7
  266. - I2C1_ADR1:
  267. fields: !!omap
  268. - GC:
  269. access: rw
  270. description: General Call enable bit
  271. lsb: 0
  272. reset_value: '0'
  273. width: 1
  274. - ADDRESS:
  275. access: rw
  276. description: The I2C device address for slave mode
  277. lsb: 1
  278. reset_value: '0'
  279. width: 7
  280. - I2C0_ADR2:
  281. fields: !!omap
  282. - GC:
  283. access: rw
  284. description: General Call enable bit
  285. lsb: 0
  286. reset_value: '0'
  287. width: 1
  288. - ADDRESS:
  289. access: rw
  290. description: The I2C device address for slave mode
  291. lsb: 1
  292. reset_value: '0'
  293. width: 7
  294. - I2C1_ADR2:
  295. fields: !!omap
  296. - GC:
  297. access: rw
  298. description: General Call enable bit
  299. lsb: 0
  300. reset_value: '0'
  301. width: 1
  302. - ADDRESS:
  303. access: rw
  304. description: The I2C device address for slave mode
  305. lsb: 1
  306. reset_value: '0'
  307. width: 7
  308. - I2C0_ADR3:
  309. fields: !!omap
  310. - GC:
  311. access: rw
  312. description: General Call enable bit
  313. lsb: 0
  314. reset_value: '0'
  315. width: 1
  316. - ADDRESS:
  317. access: rw
  318. description: The I2C device address for slave mode
  319. lsb: 1
  320. reset_value: '0'
  321. width: 7
  322. - I2C1_ADR3:
  323. fields: !!omap
  324. - GC:
  325. access: rw
  326. description: General Call enable bit
  327. lsb: 0
  328. reset_value: '0'
  329. width: 1
  330. - ADDRESS:
  331. access: rw
  332. description: The I2C device address for slave mode
  333. lsb: 1
  334. reset_value: '0'
  335. width: 7
  336. - I2C0_DATA_BUFFER:
  337. fields: !!omap
  338. - DATA:
  339. access: r
  340. description: This register holds contents of the 8 MSBs of the DAT shift register
  341. lsb: 0
  342. reset_value: '0'
  343. width: 8
  344. - I2C1_DATA_BUFFER:
  345. fields: !!omap
  346. - DATA:
  347. access: r
  348. description: This register holds contents of the 8 MSBs of the DAT shift register
  349. lsb: 0
  350. reset_value: '0'
  351. width: 8
  352. - I2C0_MASK0:
  353. fields: !!omap
  354. - MASK:
  355. access: rw
  356. description: Mask bits
  357. lsb: 1
  358. reset_value: '0'
  359. width: 7
  360. - I2C1_MASK0:
  361. fields: !!omap
  362. - MASK:
  363. access: rw
  364. description: Mask bits
  365. lsb: 1
  366. reset_value: '0'
  367. width: 7
  368. - I2C0_MASK1:
  369. fields: !!omap
  370. - MASK:
  371. access: rw
  372. description: Mask bits
  373. lsb: 1
  374. reset_value: '0'
  375. width: 7
  376. - I2C1_MASK1:
  377. fields: !!omap
  378. - MASK:
  379. access: rw
  380. description: Mask bits
  381. lsb: 1
  382. reset_value: '0'
  383. width: 7
  384. - I2C0_MASK2:
  385. fields: !!omap
  386. - MASK:
  387. access: rw
  388. description: Mask bits
  389. lsb: 1
  390. reset_value: '0'
  391. width: 7
  392. - I2C1_MASK2:
  393. fields: !!omap
  394. - MASK:
  395. access: rw
  396. description: Mask bits
  397. lsb: 1
  398. reset_value: '0'
  399. width: 7
  400. - I2C0_MASK3:
  401. fields: !!omap
  402. - MASK:
  403. access: rw
  404. description: Mask bits
  405. lsb: 1
  406. reset_value: '0'
  407. width: 7
  408. - I2C1_MASK3:
  409. fields: !!omap
  410. - MASK:
  411. access: rw
  412. description: Mask bits
  413. lsb: 1
  414. reset_value: '0'
  415. width: 7