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m4_init/3rd/libopencm3/scripts/data/lpc43xx/adc.yaml

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  1. !!omap

  2. - ADC0_CR:

  3.     fields: !!omap

  4.     - SEL:

  5.         access: rw

  6.         description: Selects which of the ADCn_[7:0] inputs are to be sampled and

  7.           converted

  8.         lsb: 0

  9.         reset_value: '0'

  10.         width: 8

  11.     - CLKDIV:

  12.         access: rw

  13.         description: The ADC clock is divided by the CLKDIV value plus one to produce

  14.           the clock for the A/D converter

  15.         lsb: 8

  16.         reset_value: '0'

  17.         width: 8

  18.     - BURST:

  19.         access: rw

  20.         description: Controls Burst mode

  21.         lsb: 16

  22.         reset_value: '0'

  23.         width: 1

  24.     - CLKS:

  25.         access: rw

  26.         description: This field selects the number of clocks used for each conversion

  27.           in Burst mode and the number of bits of accuracy of the result in the LS

  28.           bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).

  29.         lsb: 17

  30.         reset_value: '0'

  31.         width: 3

  32.     - PDN:

  33.         access: rw

  34.         description: Power mode

  35.         lsb: 21

  36.         reset_value: '0'

  37.         width: 1

  38.     - START:

  39.         access: rw

  40.         description: Controls the start of an A/D conversion when the BURST bit is

  41.           0

  42.         lsb: 24

  43.         reset_value: '0'

  44.         width: 3

  45.     - EDGE:

  46.         access: rw

  47.         description: Controls rising or falling edge on the selected signal for the

  48.           start of a conversion

  49.         lsb: 27

  50.         reset_value: '0'

  51.         width: 1

  52. - ADC1_CR:

  53.     fields: !!omap

  54.     - SEL:

  55.         access: rw

  56.         description: Selects which of the ADCn_[7:0] inputs are to be sampled and

  57.           converted

  58.         lsb: 0

  59.         reset_value: '0'

  60.         width: 8

  61.     - CLKDIV:

  62.         access: rw

  63.         description: The ADC clock is divided by the CLKDIV value plus one to produce

  64.           the clock for the A/D converter

  65.         lsb: 8

  66.         reset_value: '0'

  67.         width: 8

  68.     - BURST:

  69.         access: rw

  70.         description: Controls Burst mode

  71.         lsb: 16

  72.         reset_value: '0'

  73.         width: 1

  74.     - CLKS:

  75.         access: rw

  76.         description: This field selects the number of clocks used for each conversion

  77.           in Burst mode and the number of bits of accuracy of the result in the LS

  78.           bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).

  79.         lsb: 17

  80.         reset_value: '0'

  81.         width: 3

  82.     - PDN:

  83.         access: rw

  84.         description: Power mode

  85.         lsb: 21

  86.         reset_value: '0'

  87.         width: 1

  88.     - START:

  89.         access: rw

  90.         description: Controls the start of an A/D conversion when the BURST bit is

  91.           0

  92.         lsb: 24

  93.         reset_value: '0'

  94.         width: 3

  95.     - EDGE:

  96.         access: rw

  97.         description: Controls rising or falling edge on the selected signal for the

  98.           start of a conversion

  99.         lsb: 27

  100.         reset_value: '0'

  101.         width: 1

  102. - ADC0_GDR:

  103.     fields: !!omap

  104.     - V_VREF:

  105.         access: r

  106.         description: When DONE is 1, this field contains a binary fraction representing

  107.           the voltage on the ADCn pin selected by the SEL field, divided by the reference

  108.           voltage on the VDDA pin

  109.         lsb: 6

  110.         reset_value: '0'

  111.         width: 10

  112.     - CHN:

  113.         access: r

  114.         description: These bits contain the channel from which the LS bits were converted

  115.         lsb: 24

  116.         reset_value: '0'

  117.         width: 3

  118.     - OVERRUN:

  119.         access: r

  120.         description: This bit is 1 in burst mode if the results of one or more conversions

  121.           was (were) lost and overwritten before the conversion that produced the

  122.           result in the V_VREF bits

  123.         lsb: 30

  124.         reset_value: '0'

  125.         width: 1

  126.     - DONE:

  127.         access: r

  128.         description: This bit is set to 1 when an analog-to-digital conversion completes.

  129.           It is cleared when this register is read and when the AD0/1CR register is

  130.           written

  131.         lsb: 31

  132.         reset_value: '0'

  133.         width: 1

  134. - ADC1_GDR:

  135.     fields: !!omap

  136.     - V_VREF:

  137.         access: r

  138.         description: When DONE is 1, this field contains a binary fraction representing

  139.           the voltage on the ADCn pin selected by the SEL field, divided by the reference

  140.           voltage on the VDDA pin

  141.         lsb: 6

  142.         reset_value: '0'

  143.         width: 10

  144.     - CHN:

  145.         access: r

  146.         description: These bits contain the channel from which the LS bits were converted

  147.         lsb: 24

  148.         reset_value: '0'

  149.         width: 3

  150.     - OVERRUN:

  151.         access: r

  152.         description: This bit is 1 in burst mode if the results of one or more conversions

  153.           was (were) lost and overwritten before the conversion that produced the

  154.           result in the V_VREF bits

  155.         lsb: 30

  156.         reset_value: '0'

  157.         width: 1

  158.     - DONE:

  159.         access: r

  160.         description: This bit is set to 1 when an analog-to-digital conversion completes.

  161.           It is cleared when this register is read and when the AD0/1CR register is

  162.           written

  163.         lsb: 31

  164.         reset_value: '0'

  165.         width: 1

  166. - ADC0_INTEN:

  167.     fields: !!omap

  168.     - ADINTEN:

  169.         access: rw

  170.         description: These bits allow control over which A/D channels generate interrupts

  171.           for conversion completion

  172.         lsb: 0

  173.         reset_value: '0'

  174.         width: 8

  175.     - ADGINTEN:

  176.         access: rw

  177.         description: When 1, enables the global DONE flag in ADDR to generate an interrupt.

  178.           When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate

  179.           interrupts.

  180.         lsb: 8

  181.         reset_value: '1'

  182.         width: 1

  183. - ADC1_INTEN:

  184.     fields: !!omap

  185.     - ADINTEN:

  186.         access: rw

  187.         description: These bits allow control over which A/D channels generate interrupts

  188.           for conversion completion

  189.         lsb: 0

  190.         reset_value: '0'

  191.         width: 8

  192.     - ADGINTEN:

  193.         access: rw

  194.         description: When 1, enables the global DONE flag in ADDR to generate an interrupt.

  195.           When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate

  196.           interrupts.

  197.         lsb: 8

  198.         reset_value: '1'

  199.         width: 1

  200. - ADC0_DR0:

  201.     fields: !!omap

  202.     - V_VREF:

  203.         access: r

  204.         description: When DONE is 1, this field contains a binary fraction representing

  205.           the voltage on the ADC0 pin divided by the reference voltage on the VDDA

  206.           pin

  207.         lsb: 6

  208.         reset_value: '0'

  209.         width: 10

  210.     - OVERRUN:

  211.         access: r

  212.         description: This bit is 1 in burst mode if the results of one or more conversions

  213.           was (were) lost and overwritten before the conversion that produced the

  214.           result in the V_VREF bits in this register.

  215.         lsb: 30

  216.         reset_value: '0'

  217.         width: 1

  218.     - DONE:

  219.         access: r

  220.         description: This bit is set to 1 when an A/D conversion completes.

  221.         lsb: 31

  222.         reset_value: '0'

  223.         width: 1

  224. - ADC1_DR0:

  225.     fields: !!omap

  226.     - V_VREF:

  227.         access: r

  228.         description: When DONE is 1, this field contains a binary fraction representing

  229.           the voltage on the ADC0 pin divided by the reference voltage on the VDDA

  230.           pin

  231.         lsb: 6

  232.         reset_value: '0'

  233.         width: 10

  234.     - OVERRUN:

  235.         access: r

  236.         description: This bit is 1 in burst mode if the results of one or more conversions

  237.           was (were) lost and overwritten before the conversion that produced the

  238.           result in the V_VREF bits in this register.

  239.         lsb: 30

  240.         reset_value: '0'

  241.         width: 1

  242.     - DONE:

  243.         access: r

  244.         description: This bit is set to 1 when an A/D conversion completes.

  245.         lsb: 31

  246.         reset_value: '0'

  247.         width: 1

  248. - ADC0_DR1:

  249.     fields: !!omap

  250.     - V_VREF:

  251.         access: r

  252.         description: When DONE is 1, this field contains a binary fraction representing

  253.           the voltage on the ADC1 pin divided by the reference voltage on the VDDA

  254.           pin

  255.         lsb: 6

  256.         reset_value: '0'

  257.         width: 10

  258.     - OVERRUN:

  259.         access: r

  260.         description: This bit is 1 in burst mode if the results of one or more conversions

  261.           was (were) lost and overwritten before the conversion that produced the

  262.           result in the V_VREF bits in this register.

  263.         lsb: 30

  264.         reset_value: '0'

  265.         width: 1

  266.     - DONE:

  267.         access: r

  268.         description: This bit is set to 1 when an A/D conversion completes.

  269.         lsb: 31

  270.         reset_value: '0'

  271.         width: 1

  272. - ADC1_DR1:

  273.     fields: !!omap

  274.     - V_VREF:

  275.         access: r

  276.         description: When DONE is 1, this field contains a binary fraction representing

  277.           the voltage on the ADC1 pin divided by the reference voltage on the VDDA

  278.           pin

  279.         lsb: 6

  280.         reset_value: '0'

  281.         width: 10

  282.     - OVERRUN:

  283.         access: r

  284.         description: This bit is 1 in burst mode if the results of one or more conversions

  285.           was (were) lost and overwritten before the conversion that produced the

  286.           result in the V_VREF bits in this register.

  287.         lsb: 30

  288.         reset_value: '0'

  289.         width: 1

  290.     - DONE:

  291.         access: r

  292.         description: This bit is set to 1 when an A/D conversion completes.

  293.         lsb: 31

  294.         reset_value: '0'

  295.         width: 1

  296. - ADC0_DR2:

  297.     fields: !!omap

  298.     - V_VREF:

  299.         access: r

  300.         description: When DONE is 1, this field contains a binary fraction representing

  301.           the voltage on the ADC2 pin divided by the reference voltage on the VDDA

  302.           pin

  303.         lsb: 6

  304.         reset_value: '0'

  305.         width: 10

  306.     - OVERRUN:

  307.         access: r

  308.         description: This bit is 1 in burst mode if the results of one or more conversions

  309.           was (were) lost and overwritten before the conversion that produced the

  310.           result in the V_VREF bits in this register.

  311.         lsb: 30

  312.         reset_value: '0'

  313.         width: 1

  314.     - DONE:

  315.         access: r

  316.         description: This bit is set to 1 when an A/D conversion completes.

  317.         lsb: 31

  318.         reset_value: '0'

  319.         width: 1

  320. - ADC1_DR2:

  321.     fields: !!omap

  322.     - V_VREF:

  323.         access: r

  324.         description: When DONE is 1, this field contains a binary fraction representing

  325.           the voltage on the ADC2 pin divided by the reference voltage on the VDDA

  326.           pin

  327.         lsb: 6

  328.         reset_value: '0'

  329.         width: 10

  330.     - OVERRUN:

  331.         access: r

  332.         description: This bit is 1 in burst mode if the results of one or more conversions

  333.           was (were) lost and overwritten before the conversion that produced the

  334.           result in the V_VREF bits in this register.

  335.         lsb: 30

  336.         reset_value: '0'

  337.         width: 1

  338.     - DONE:

  339.         access: r

  340.         description: This bit is set to 1 when an A/D conversion completes.

  341.         lsb: 31

  342.         reset_value: '0'

  343.         width: 1

  344. - ADC0_DR3:

  345.     fields: !!omap

  346.     - V_VREF:

  347.         access: r

  348.         description: When DONE is 1, this field contains a binary fraction representing

  349.           the voltage on the ADC3 pin divided by the reference voltage on the VDDA

  350.           pin

  351.         lsb: 6

  352.         reset_value: '0'

  353.         width: 10

  354.     - OVERRUN:

  355.         access: r

  356.         description: This bit is 1 in burst mode if the results of one or more conversions

  357.           was (were) lost and overwritten before the conversion that produced the

  358.           result in the V_VREF bits in this register.

  359.         lsb: 30

  360.         reset_value: '0'

  361.         width: 1

  362.     - DONE:

  363.         access: r

  364.         description: This bit is set to 1 when an A/D conversion completes.

  365.         lsb: 31

  366.         reset_value: '0'

  367.         width: 1

  368. - ADC1_DR3:

  369.     fields: !!omap

  370.     - V_VREF:

  371.         access: r

  372.         description: When DONE is 1, this field contains a binary fraction representing

  373.           the voltage on the ADC3 pin divided by the reference voltage on the VDDA

  374.           pin

  375.         lsb: 6

  376.         reset_value: '0'

  377.         width: 10

  378.     - OVERRUN:

  379.         access: r

  380.         description: This bit is 1 in burst mode if the results of one or more conversions

  381.           was (were) lost and overwritten before the conversion that produced the

  382.           result in the V_VREF bits in this register.

  383.         lsb: 30

  384.         reset_value: '0'

  385.         width: 1

  386.     - DONE:

  387.         access: r

  388.         description: This bit is set to 1 when an A/D conversion completes.

  389.         lsb: 31

  390.         reset_value: '0'

  391.         width: 1

  392. - ADC0_DR4:

  393.     fields: !!omap

  394.     - V_VREF:

  395.         access: r

  396.         description: When DONE is 1, this field contains a binary fraction representing

  397.           the voltage on the ADC4 pin divided by the reference voltage on the VDDA

  398.           pin

  399.         lsb: 6

  400.         reset_value: '0'

  401.         width: 10

  402.     - OVERRUN:

  403.         access: r

  404.         description: This bit is 1 in burst mode if the results of one or more conversions

  405.           was (were) lost and overwritten before the conversion that produced the

  406.           result in the V_VREF bits in this register.

  407.         lsb: 30

  408.         reset_value: '0'

  409.         width: 1

  410.     - DONE:

  411.         access: r

  412.         description: This bit is set to 1 when an A/D conversion completes.

  413.         lsb: 31

  414.         reset_value: '0'

  415.         width: 1

  416. - ADC1_DR4:

  417.     fields: !!omap

  418.     - V_VREF:

  419.         access: r

  420.         description: When DONE is 1, this field contains a binary fraction representing

  421.           the voltage on the ADC4 pin divided by the reference voltage on the VDDA

  422.           pin

  423.         lsb: 6

  424.         reset_value: '0'

  425.         width: 10

  426.     - OVERRUN:

  427.         access: r

  428.         description: This bit is 1 in burst mode if the results of one or more conversions

  429.           was (were) lost and overwritten before the conversion that produced the

  430.           result in the V_VREF bits in this register.

  431.         lsb: 30

  432.         reset_value: '0'

  433.         width: 1

  434.     - DONE:

  435.         access: r

  436.         description: This bit is set to 1 when an A/D conversion completes.

  437.         lsb: 31

  438.         reset_value: '0'

  439.         width: 1

  440. - ADC0_DR5:

  441.     fields: !!omap

  442.     - V_VREF:

  443.         access: r

  444.         description: When DONE is 1, this field contains a binary fraction representing

  445.           the voltage on the ADC5 pin divided by the reference voltage on the VDDA

  446.           pin

  447.         lsb: 6

  448.         reset_value: '0'

  449.         width: 10

  450.     - OVERRUN:

  451.         access: r

  452.         description: This bit is 1 in burst mode if the results of one or more conversions

  453.           was (were) lost and overwritten before the conversion that produced the

  454.           result in the V_VREF bits in this register.

  455.         lsb: 30

  456.         reset_value: '0'

  457.         width: 1

  458.     - DONE:

  459.         access: r

  460.         description: This bit is set to 1 when an A/D conversion completes.

  461.         lsb: 31

  462.         reset_value: '0'

  463.         width: 1

  464. - ADC1_DR5:

  465.     fields: !!omap

  466.     - V_VREF:

  467.         access: r

  468.         description: When DONE is 1, this field contains a binary fraction representing

  469.           the voltage on the ADC5 pin divided by the reference voltage on the VDDA

  470.           pin

  471.         lsb: 6

  472.         reset_value: '0'

  473.         width: 10

  474.     - OVERRUN:

  475.         access: r

  476.         description: This bit is 1 in burst mode if the results of one or more conversions

  477.           was (were) lost and overwritten before the conversion that produced the

  478.           result in the V_VREF bits in this register.

  479.         lsb: 30

  480.         reset_value: '0'

  481.         width: 1

  482.     - DONE:

  483.         access: r

  484.         description: This bit is set to 1 when an A/D conversion completes.

  485.         lsb: 31

  486.         reset_value: '0'

  487.         width: 1

  488. - ADC0_DR6:

  489.     fields: !!omap

  490.     - V_VREF:

  491.         access: r

  492.         description: When DONE is 1, this field contains a binary fraction representing

  493.           the voltage on the ADC6 pin divided by the reference voltage on the VDDA

  494.           pin

  495.         lsb: 6

  496.         reset_value: '0'

  497.         width: 10

  498.     - OVERRUN:

  499.         access: r

  500.         description: This bit is 1 in burst mode if the results of one or more conversions

  501.           was (were) lost and overwritten before the conversion that produced the

  502.           result in the V_VREF bits in this register.

  503.         lsb: 30

  504.         reset_value: '0'

  505.         width: 1

  506.     - DONE:

  507.         access: r

  508.         description: This bit is set to 1 when an A/D conversion completes.

  509.         lsb: 31

  510.         reset_value: '0'

  511.         width: 1

  512. - ADC1_DR6:

  513.     fields: !!omap

  514.     - V_VREF:

  515.         access: r

  516.         description: When DONE is 1, this field contains a binary fraction representing

  517.           the voltage on the ADC6 pin divided by the reference voltage on the VDDA

  518.           pin

  519.         lsb: 6

  520.         reset_value: '0'

  521.         width: 10

  522.     - OVERRUN:

  523.         access: r

  524.         description: This bit is 1 in burst mode if the results of one or more conversions

  525.           was (were) lost and overwritten before the conversion that produced the

  526.           result in the V_VREF bits in this register.

  527.         lsb: 30

  528.         reset_value: '0'

  529.         width: 1

  530.     - DONE:

  531.         access: r

  532.         description: This bit is set to 1 when an A/D conversion completes.

  533.         lsb: 31

  534.         reset_value: '0'

  535.         width: 1

  536. - ADC0_DR7:

  537.     fields: !!omap

  538.     - V_VREF:

  539.         access: r

  540.         description: When DONE is 1, this field contains a binary fraction representing

  541.           the voltage on the ADC7 pin divided by the reference voltage on the VDDA

  542.           pin

  543.         lsb: 6

  544.         reset_value: '0'

  545.         width: 10

  546.     - OVERRUN:

  547.         access: r

  548.         description: This bit is 1 in burst mode if the results of one or more conversions

  549.           was (were) lost and overwritten before the conversion that produced the

  550.           result in the V_VREF bits in this register.

  551.         lsb: 30

  552.         reset_value: '0'

  553.         width: 1

  554.     - DONE:

  555.         access: r

  556.         description: This bit is set to 1 when an A/D conversion completes.

  557.         lsb: 31

  558.         reset_value: '0'

  559.         width: 1

  560. - ADC1_DR7:

  561.     fields: !!omap

  562.     - V_VREF:

  563.         access: r

  564.         description: When DONE is 1, this field contains a binary fraction representing

  565.           the voltage on the ADC7 pin divided by the reference voltage on the VDDA

  566.           pin

  567.         lsb: 6

  568.         reset_value: '0'

  569.         width: 10

  570.     - OVERRUN:

  571.         access: r

  572.         description: This bit is 1 in burst mode if the results of one or more conversions

  573.           was (were) lost and overwritten before the conversion that produced the

  574.           result in the V_VREF bits in this register.

  575.         lsb: 30

  576.         reset_value: '0'

  577.         width: 1

  578.     - DONE:

  579.         access: r

  580.         description: This bit is set to 1 when an A/D conversion completes.

  581.         lsb: 31

  582.         reset_value: '0'

  583.         width: 1

  584. - ADC0_STAT:

  585.     fields: !!omap

  586.     - DONE:

  587.         access: r

  588.         description: These bits mirror the DONE status flags that appear in the result

  589.           register for each A/D channel.

  590.         lsb: 0

  591.         reset_value: '0'

  592.         width: 8

  593.     - OVERRUN:

  594.         access: r

  595.         description: These bits mirror the OVERRRUN status flags that appear in the

  596.           result register for each A/D channel.

  597.         lsb: 8

  598.         reset_value: '0'

  599.         width: 8

  600.     - ADINT:

  601.         access: r

  602.         description: This bit is the A/D interrupt flag. It is one when any of the

  603.           individual A/D channel Done flags is asserted and enabled to contribute

  604.           to the A/D interrupt via the ADINTEN register.

  605.         lsb: 16

  606.         reset_value: '0'

  607.         width: 1