e6439f96ab
Adds cSHAKE with 0 alloc interface ( #19 )
2019-05-14 01:19:29 +01:00
6f9706df01
CTR-DRBG: Use hardware acceleration on X86 ( #18 )
...
benchmark old ns/op new ns/op delta
BenchmarkInit-4 3403 397 -88.33%
BenchmarkRead-4 14535 1560 -89.27%
2019-04-09 23:50:21 +01:00
71624cdc4c
Improvements to makefile
2019-04-09 17:30:30 +01:00
b184944242
Nits for SIDH
2019-04-09 17:09:34 +01:00
08f7315b64
DRBG: Speed improvements
...
* CTR-DRBG doesn't call "NewCipher" for block encryption
* Changes API of CTR-DRBG, so that read operation implementes io.Reader
Benchmark results:
----------------------
benchmark old ns/op new ns/op delta
BenchmarkInit-4 1118 3579 +220.13%
BenchmarkRead-4 5343 14589 +173.05%
benchmark old allocs new allocs delta
BenchmarkInit-4 15 0 -100.00%
BenchmarkRead-4 67 0 -100.00%
benchmark old bytes new bytes delta
BenchmarkInit-4 1824 0 -100.00%
BenchmarkRead-4 9488 0 -100.00%
2019-04-09 14:37:59 +01:00
e66cc99401
Improves comment
2019-02-19 14:44:11 +00:00
b47a731959
Run tests on ARM64 ( #11 )
2019-02-16 21:29:20 +00:00
90f8cba329
SIDH: Update ( #9 )
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* Change license to BSD-3
* SIDH: Multiple developlemnts
2018-12-03 23:07:01 +00:00
ea2ffa2d61
PERF: sidh-p503: Split sub and add into 2 uops instead of 3 ( #8 )
...
The performance improvement comes from the fact that on Skylake
"add mem, reg" splits into 2 uops - one arithmetic uop and another one
for loading a value from mem.
However, changing operand order to "add reg, mem" splits into 3 uops:
one for arithmetic op, one for load and one additional one for storing
the result back.
Using separated instruction for loading/storing helps to parallelize
execution (load/store and arithmetic instruction is done in parallel
if possible)
For details, see: https://www.agner.org/optimize/instruction_tables.pdf
New: BenchmarkFp503StrongReduce-4 300000000 5.57 ns/op
Old: BenchmarkFp503StrongReduce-4 200000000 8.60 ns/op
This just improves one function, but more functions can be improved
2018-11-18 20:57:29 +00:00
e9ddb6fb45
sidh/csidh: use SEE for performing CSWAP ( #6 )
...
* Makefile
* makefile: tools for profiling
* sidh: use SIMD for performing CSWAP
Loads data into 128-bit XMM registers and performs conditional swap.
This is probably less useful for SIDH, but will be useful for cSIDH
2018-10-29 15:41:09 +00:00
a456dc4dd9
readme: License
2018-10-25 15:22:28 +01:00
ae57368c7b
License BS for sha3
2018-10-25 15:22:28 +01:00
00c16fe97e
License bulshit
2018-10-25 15:22:28 +01:00
65bbafeef5
script used for calculating sliding window startegy in SIDH P34
2018-10-25 15:22:28 +01:00
0531c3479b
Update README.md
2018-10-25 15:22:28 +01:00
1e34845d00
complate rewrite for SIDH and SIKE. adds p503 ( #5 )
2018-10-25 15:22:28 +01:00
d6fc82531f
Doc
2018-10-25 15:22:28 +01:00
b769c88767
Improves some comments and hardcodes precomputed value ( #4 )
...
* Improves some comments and hardcodes precomputed value
* Tests curve coefficients recovery
2018-10-25 15:22:28 +01:00
51688dc4bb
makefile: adds bench target
2018-10-25 15:18:54 +01:00
35e326cf2c
Merge branch 'master' of github.com:henrydcase/nobscrypto
2018-08-03 14:39:10 +01:00
10fb1a7164
x448: Export shared secret size
...
Changes x448Bytes variable to SharedSecretSize
2018-08-03 14:37:38 +01:00
c88bbf0f75
x448: Export shared secret size ( #3 )
...
Changes x448Bytes variable to SharedSecretSize
2018-08-03 14:36:45 +01:00
2ff456da90
Temporarily adds simple x448 implementation
2018-08-02 23:45:28 +01:00
fc932264c3
Merge pull request #2 from henrydcase/x448
...
Temporarily adds simple x448 implementation
2018-08-02 23:44:22 +01:00
22e3d2373f
adds code coverage
2018-07-31 20:26:50 +01:00
ddbd866ee5
additional comments
2018-07-31 20:21:32 +01:00
dc58ebcd23
makefile formatting
2018-07-31 19:14:49 +01:00
771516ce3f
fixes sike tests
2018-07-31 19:14:39 +01:00
2a25a09b4a
improves makefile
2018-07-31 18:20:27 +01:00
34805fc1fb
Improves Makefile
2018-07-31 18:00:55 +01:00
73c9938c59
Use ADCB instead of SBBL in checkLessThanThree238
2018-07-31 17:10:03 +01:00
958dae0be7
tls: git ignore
2018-07-27 17:11:53 +01:00
2fc873ca64
creates package ready to move to tls-tris
2018-07-27 00:38:21 +01:00
105532aa09
sidh: move p751 implementation to p751 folder
2018-07-27 00:09:34 +01:00
431c20d5ff
readme: sike/sidh
2018-07-23 23:23:34 +01:00
a4d12ceaae
adds SIKE and SIDH
2018-07-23 23:18:38 +01:00
bd9a3f2b6b
Temporarily change sha3 import location
2018-07-05 15:51:09 +01:00
4d0f3e5293
AES-256 CTR_DRBG
2018-06-24 09:50:06 +01:00
4b06c1b314
go fmt
2018-06-23 16:48:54 +01:00
8cf7cfdc8d
SM3 and cSHAKE
2018-06-23 16:34:45 +01:00
94bf28a208
first commit
2018-05-31 00:24:43 +01:00
